x600.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. *
  6. * Copyright (C) 2012 Stefan Roese <sr@denx.de>
  7. */
  8. #include <common.h>
  9. #include <flash.h>
  10. #include <init.h>
  11. #include <micrel.h>
  12. #include <nand.h>
  13. #include <net.h>
  14. #include <netdev.h>
  15. #include <phy.h>
  16. #include <rtc.h>
  17. #include <asm/io.h>
  18. #include <asm/mach-types.h>
  19. #include <asm/arch/hardware.h>
  20. #include <asm/arch/spr_defs.h>
  21. #include <asm/arch/spr_misc.h>
  22. #include <linux/mtd/fsmc_nand.h>
  23. #include "fpga.h"
  24. static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
  25. int board_init(void)
  26. {
  27. /*
  28. * X600 is equipped with an M41T82 RTC. This RTC has the
  29. * HT bit (Halt Update), which needs to be cleared upon
  30. * power-up. Otherwise the RTC is halted.
  31. */
  32. rtc_reset();
  33. return spear_board_init(MACH_TYPE_SPEAR600);
  34. }
  35. int board_late_init(void)
  36. {
  37. /*
  38. * Monitor and env protection on by default
  39. */
  40. flash_protect(FLAG_PROTECT_SET,
  41. CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE +
  42. CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN +
  43. 2 * CONFIG_ENV_SECT_SIZE - 1,
  44. &flash_info[0]);
  45. /* Init FPGA subsystem */
  46. x600_init_fpga();
  47. return 0;
  48. }
  49. /*
  50. * board_nand_init - Board specific NAND initialization
  51. * @nand: mtd private chip structure
  52. *
  53. * Called by nand_init_chip to initialize the board specific functions
  54. */
  55. void board_nand_init(void)
  56. {
  57. struct misc_regs *const misc_regs_p =
  58. (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  59. struct nand_chip *nand = &nand_chip[0];
  60. if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
  61. fsmc_nand_init(nand);
  62. }
  63. int board_phy_config(struct phy_device *phydev)
  64. {
  65. unsigned short id1, id2;
  66. /* check whether KSZ9031 or AR8035 has to be configured */
  67. id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
  68. id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
  69. if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
  70. /* PHY configuration for Micrel KSZ9031 */
  71. printf("PHY KSZ9031 detected - ");
  72. phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
  73. /* control data pad skew - devaddr = 0x02, register = 0x04 */
  74. ksz9031_phy_extended_write(phydev, 0x02,
  75. MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  76. MII_KSZ9031_MOD_DATA_NO_POST_INC,
  77. 0x0000);
  78. /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  79. ksz9031_phy_extended_write(phydev, 0x02,
  80. MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  81. MII_KSZ9031_MOD_DATA_NO_POST_INC,
  82. 0x0000);
  83. /* tx data pad skew - devaddr = 0x02, register = 0x05 */
  84. ksz9031_phy_extended_write(phydev, 0x02,
  85. MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  86. MII_KSZ9031_MOD_DATA_NO_POST_INC,
  87. 0x0000);
  88. /* gtx and rx clock pad skew - devaddr = 0x02, reg = 0x08 */
  89. ksz9031_phy_extended_write(phydev, 0x02,
  90. MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  91. MII_KSZ9031_MOD_DATA_NO_POST_INC,
  92. 0x03FF);
  93. } else {
  94. /* PHY configuration for Vitesse VSC8641 */
  95. printf("PHY VSC8641 detected - ");
  96. /* Extended PHY control 1, select GMII */
  97. phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
  98. /* Software reset necessary after GMII mode selction */
  99. phy_reset(phydev);
  100. /* Enable extended page register access */
  101. phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
  102. /* 17e: Enhanced LED behavior, needs to be written twice */
  103. phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
  104. phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
  105. /* 16e: Enhanced LED method select */
  106. phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
  107. /* Disable extended page register access */
  108. phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
  109. /* Enable clock output pin */
  110. phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
  111. }
  112. if (phydev->drv->config)
  113. phydev->drv->config(phydev);
  114. return 0;
  115. }
  116. int board_eth_init(struct bd_info *bis)
  117. {
  118. int ret = 0;
  119. if (designware_initialize(CONFIG_SPEAR_ETHBASE,
  120. PHY_INTERFACE_MODE_GMII) >= 0)
  121. ret++;
  122. return ret;
  123. }