fpga.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <log.h>
  7. #include <spartan3.h>
  8. #include <command.h>
  9. #include <asm/gpio.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/hardware.h>
  12. #include <asm/arch/spr_misc.h>
  13. #include <asm/arch/spr_ssp.h>
  14. #include <linux/delay.h>
  15. /*
  16. * FPGA program pin configuration on X600:
  17. *
  18. * Only PROG and DONE are connected to GPIOs. INIT is not connected to the
  19. * SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use
  20. * 16bit serial writes via this SSP port to write the data bits into the
  21. * FPGA.
  22. */
  23. #define CONFIG_SYS_FPGA_PROG 2
  24. #define CONFIG_SYS_FPGA_DONE 3
  25. /*
  26. * Set the active-low FPGA reset signal.
  27. */
  28. static void fpga_reset(int assert)
  29. {
  30. /*
  31. * On x600 we have no means to toggle the FPGA reset signal
  32. */
  33. debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert);
  34. }
  35. /*
  36. * Set the FPGA's active-low SelectMap program line to the specified level
  37. */
  38. static int fpga_pgm_fn(int assert, int flush, int cookie)
  39. {
  40. debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert);
  41. gpio_set_value(CONFIG_SYS_FPGA_PROG, assert);
  42. return assert;
  43. }
  44. /*
  45. * Test the state of the active-low FPGA INIT line. Return 1 on INIT
  46. * asserted (low).
  47. */
  48. static int fpga_init_fn(int cookie)
  49. {
  50. static int state;
  51. debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state);
  52. /*
  53. * On x600, the FPGA INIT signal is not connected to the SoC.
  54. * We can't read the INIT status. Let's return the "correct"
  55. * INIT signal state generated via a local state-machine.
  56. */
  57. if (++state == 1) {
  58. return 1;
  59. } else {
  60. state = 0;
  61. return 0;
  62. }
  63. }
  64. /*
  65. * Test the state of the active-high FPGA DONE pin
  66. */
  67. static int fpga_done_fn(int cookie)
  68. {
  69. struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
  70. /*
  71. * Wait for Tx-FIFO to become empty before looking for DONE
  72. */
  73. while (!(readl(&ssp->sspsr) & SSPSR_TFE))
  74. ;
  75. if (gpio_get_value(CONFIG_SYS_FPGA_DONE))
  76. return 1;
  77. else
  78. return 0;
  79. }
  80. /*
  81. * FPGA pre-configuration function. Just make sure that
  82. * FPGA reset is asserted to keep the FPGA from starting up after
  83. * configuration.
  84. */
  85. static int fpga_pre_config_fn(int cookie)
  86. {
  87. debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
  88. fpga_reset(true);
  89. return 0;
  90. }
  91. /*
  92. * FPGA post configuration function. Blip the FPGA reset line and then see if
  93. * the FPGA appears to be running.
  94. */
  95. static int fpga_post_config_fn(int cookie)
  96. {
  97. int rc = 0;
  98. debug("%s:%d: FPGA post configuration\n", __func__, __LINE__);
  99. fpga_reset(true);
  100. udelay(100);
  101. fpga_reset(false);
  102. udelay(100);
  103. return rc;
  104. }
  105. static int fpga_clk_fn(int assert_clk, int flush, int cookie)
  106. {
  107. /*
  108. * No dedicated clock signal on x600 (data & clock generated)
  109. * in SSP interface. So we don't have to do anything here.
  110. */
  111. return assert_clk;
  112. }
  113. static int fpga_wr_fn(int assert_write, int flush, int cookie)
  114. {
  115. struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
  116. static int count;
  117. static u16 data;
  118. /*
  119. * First collect 16 bits of data
  120. */
  121. data = data << 1;
  122. if (assert_write)
  123. data |= 1;
  124. /*
  125. * If 16 bits are not available, return for more bits
  126. */
  127. count++;
  128. if (count != 16)
  129. return assert_write;
  130. count = 0;
  131. /*
  132. * Wait for Tx-FIFO to become ready
  133. */
  134. while (!(readl(&ssp->sspsr) & SSPSR_TNF))
  135. ;
  136. /* Send 16 bits to FPGA via SSP bus */
  137. writel(data, &ssp->sspdr);
  138. return assert_write;
  139. }
  140. static xilinx_spartan3_slave_serial_fns x600_fpga_fns = {
  141. fpga_pre_config_fn,
  142. fpga_pgm_fn,
  143. fpga_clk_fn,
  144. fpga_init_fn,
  145. fpga_done_fn,
  146. fpga_wr_fn,
  147. fpga_post_config_fn,
  148. };
  149. static xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
  150. XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0)
  151. };
  152. /*
  153. * Initialize the SelectMap interface. We assume that the mode and the
  154. * initial state of all of the port pins have already been set!
  155. */
  156. static void fpga_serialslave_init(void)
  157. {
  158. debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__);
  159. fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */
  160. }
  161. static int expi_setup(int freq)
  162. {
  163. struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  164. int pll2_m, pll2_n, pll2_p, expi_x, expi_y;
  165. pll2_m = (freq * 2) / 1000;
  166. pll2_n = 15;
  167. pll2_p = 1;
  168. expi_x = 1;
  169. expi_y = 2;
  170. /*
  171. * Disable reset, Low compression, Disable retiming, Enable Expi,
  172. * Enable soft reset, DMA, PLL2, Internal
  173. */
  174. writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST |
  175. EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 |
  176. EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24),
  177. &misc->expi_clk_cfg);
  178. /*
  179. * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters,
  180. * Enable PLL2, Disable reset
  181. */
  182. writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq);
  183. writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE |
  184. PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl);
  185. /*
  186. * Disable soft reset
  187. */
  188. clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST);
  189. return 0;
  190. }
  191. /*
  192. * Initialize the fpga
  193. */
  194. int x600_init_fpga(void)
  195. {
  196. struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
  197. struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  198. /* Enable SSP2 clock */
  199. writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB,
  200. &misc->periph1_clken);
  201. /* Set EXPI clock to 45 MHz */
  202. expi_setup(45000);
  203. /* Configure GPIO directions */
  204. gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0);
  205. gpio_direction_input(CONFIG_SYS_FPGA_DONE);
  206. writel(SSPCR0_DSS_16BITS, &ssp->sspcr0);
  207. writel(SSPCR1_SSE, &ssp->sspcr1);
  208. /*
  209. * Set lowest prescale divisor value (CPSDVSR) of 2 for max download
  210. * speed.
  211. *
  212. * Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1))
  213. * With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz.
  214. */
  215. writel(2, &ssp->sspcpsr);
  216. fpga_init();
  217. fpga_serialslave_init();
  218. debug("%s:%d: Adding fpga 0\n", __func__, __LINE__);
  219. fpga_add(fpga_xilinx, &fpga[0]);
  220. return 0;
  221. }