spr_lowlevel_init.S 2.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2006
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. */
  6. #include <config.h>
  7. /*
  8. * platform specific initializations are already done in Xloader
  9. * Initializations already done include
  10. * DDR, PLLs, IP's clock enable and reset release etc
  11. */
  12. .globl lowlevel_init
  13. lowlevel_init:
  14. mov pc, lr
  15. /* void setfreq(unsigned int device, unsigned int frequency) */
  16. .global setfreq
  17. setfreq:
  18. stmfd sp!,{r14}
  19. stmfd sp!,{r0-r12}
  20. mov r8,sp
  21. ldr sp,SRAM_STACK_V
  22. /* Saving the function arguements for later use */
  23. mov r4,r0
  24. mov r5,r1
  25. /* Putting DDR into self refresh */
  26. ldr r0,DDR_07_V
  27. ldr r1,[r0]
  28. ldr r2,DDR_ACTIVE_V
  29. bic r1, r1, r2
  30. str r1,[r0]
  31. ldr r0,DDR_57_V
  32. ldr r1,[r0]
  33. ldr r2,CYCLES_MASK_V
  34. bic r1, r1, r2
  35. ldr r2,REFRESH_CYCLES_V
  36. orr r1, r1, r2, lsl #16
  37. str r1,[r0]
  38. ldr r0,DDR_07_V
  39. ldr r1,[r0]
  40. ldr r2,SREFRESH_MASK_V
  41. orr r1, r1, r2
  42. str r1,[r0]
  43. /* flush pipeline */
  44. b flush
  45. .align 5
  46. flush:
  47. /* Delay to ensure self refresh mode */
  48. ldr r0,SREFRESH_DELAY_V
  49. delay:
  50. sub r0,r0,#1
  51. cmp r0,#0
  52. bne delay
  53. /* Putting system in slow mode */
  54. ldr r0,SCCTRL_V
  55. mov r1,#2
  56. str r1,[r0]
  57. /* Changing PLL(1/2) frequency */
  58. mov r0,r4
  59. mov r1,r5
  60. cmp r4,#0
  61. beq pll1_freq
  62. /* Change PLL2 (DDR frequency) */
  63. ldr r6,PLL2_FREQ_V
  64. ldr r7,PLL2_CNTL_V
  65. b pll2_freq
  66. pll1_freq:
  67. /* Change PLL1 (CPU frequency) */
  68. ldr r6,PLL1_FREQ_V
  69. ldr r7,PLL1_CNTL_V
  70. pll2_freq:
  71. mov r0,r6
  72. ldr r1,[r0]
  73. ldr r2,PLLFREQ_MASK_V
  74. bic r1,r1,r2
  75. mov r2,r5,lsr#1
  76. orr r1,r1,r2,lsl#24
  77. str r1,[r0]
  78. mov r0,r7
  79. ldr r1,P1C0A_V
  80. str r1,[r0]
  81. ldr r1,P1C0E_V
  82. str r1,[r0]
  83. ldr r1,P1C06_V
  84. str r1,[r0]
  85. ldr r1,P1C0E_V
  86. str r1,[r0]
  87. lock:
  88. ldr r1,[r0]
  89. and r1,r1,#1
  90. cmp r1,#0
  91. beq lock
  92. /* Putting system back to normal mode */
  93. ldr r0,SCCTRL_V
  94. mov r1,#4
  95. str r1,[r0]
  96. /* Putting DDR back to normal */
  97. ldr r0,DDR_07_V
  98. ldr r1,[R0]
  99. ldr r2,SREFRESH_MASK_V
  100. bic r1, r1, r2
  101. str r1,[r0]
  102. ldr r2,DDR_ACTIVE_V
  103. orr r1, r1, r2
  104. str r1,[r0]
  105. /* Delay to ensure self refresh mode */
  106. ldr r0,SREFRESH_DELAY_V
  107. 1:
  108. sub r0,r0,#1
  109. cmp r0,#0
  110. bne 1b
  111. mov sp,r8
  112. /* Resuming back to code */
  113. ldmia sp!,{r0-r12}
  114. ldmia sp!,{pc}
  115. SCCTRL_V:
  116. .word 0xfca00000
  117. PLL1_FREQ_V:
  118. .word 0xfca8000C
  119. PLL1_CNTL_V:
  120. .word 0xfca80008
  121. PLL2_FREQ_V:
  122. .word 0xfca80018
  123. PLL2_CNTL_V:
  124. .word 0xfca80014
  125. PLLFREQ_MASK_V:
  126. .word 0xff000000
  127. P1C0A_V:
  128. .word 0x1C0A
  129. P1C0E_V:
  130. .word 0x1C0E
  131. P1C06_V:
  132. .word 0x1C06
  133. SREFRESH_DELAY_V:
  134. .word 0x9999
  135. SRAM_STACK_V:
  136. .word 0xD2800600
  137. DDR_07_V:
  138. .word 0xfc60001c
  139. DDR_ACTIVE_V:
  140. .word 0x01000000
  141. DDR_57_V:
  142. .word 0xfc6000e4
  143. CYCLES_MASK_V:
  144. .word 0xffff0000
  145. REFRESH_CYCLES_V:
  146. .word 0xf0f0
  147. SREFRESH_MASK_V:
  148. .word 0x00010000
  149. .global setfreq_sz
  150. setfreq_sz:
  151. .word setfreq_sz - setfreq