spear600.c 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2009
  4. * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
  5. * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
  6. */
  7. #include <common.h>
  8. #include <asm/hardware.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/spr_misc.h>
  11. #include <asm/arch/spr_defs.h>
  12. void spear_late_init(void)
  13. {
  14. struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  15. writel(0x80000007, &misc_p->arb_icm_ml1);
  16. writel(0x80000007, &misc_p->arb_icm_ml2);
  17. writel(0x80000007, &misc_p->arb_icm_ml3);
  18. writel(0x80000007, &misc_p->arb_icm_ml4);
  19. writel(0x80000007, &misc_p->arb_icm_ml5);
  20. writel(0x80000007, &misc_p->arb_icm_ml6);
  21. writel(0x80000007, &misc_p->arb_icm_ml7);
  22. writel(0x80000007, &misc_p->arb_icm_ml8);
  23. writel(0x80000007, &misc_p->arb_icm_ml9);
  24. }
  25. static void sel_1v8(void)
  26. {
  27. struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  28. u32 ddr1v8, ddr2v5;
  29. ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
  30. ddr2v5 &= 0x8080ffc0;
  31. ddr2v5 |= 0x78000003;
  32. writel(ddr2v5, &misc_p->ddr_2v5_compensation);
  33. ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
  34. ddr1v8 &= 0x8080ffc0;
  35. ddr1v8 |= 0x78000010;
  36. writel(ddr1v8, &misc_p->ddr_1v8_compensation);
  37. while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
  38. ;
  39. }
  40. static void sel_2v5(void)
  41. {
  42. struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  43. u32 ddr1v8, ddr2v5;
  44. ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
  45. ddr1v8 &= 0x8080ffc0;
  46. ddr1v8 |= 0x78000003;
  47. writel(ddr1v8, &misc_p->ddr_1v8_compensation);
  48. ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
  49. ddr2v5 &= 0x8080ffc0;
  50. ddr2v5 |= 0x78000010;
  51. writel(ddr2v5, &misc_p->ddr_2v5_compensation);
  52. while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
  53. ;
  54. }
  55. /*
  56. * plat_ddr_init:
  57. */
  58. void plat_ddr_init(void)
  59. {
  60. struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  61. u32 ddrpad;
  62. u32 core3v3, ddr1v8, ddr2v5;
  63. /* DDR pad register configurations */
  64. ddrpad = readl(&misc_p->ddr_pad);
  65. ddrpad &= ~DDR_PAD_CNF_MSK;
  66. #if (CONFIG_DDR_HCLK)
  67. ddrpad |= 0xEAAB;
  68. #elif (CONFIG_DDR_2HCLK)
  69. ddrpad |= 0xEAAD;
  70. #elif (CONFIG_DDR_PLL2)
  71. ddrpad |= 0xEAAD;
  72. #endif
  73. writel(ddrpad, &misc_p->ddr_pad);
  74. /* Compensation register configurations */
  75. core3v3 = readl(&misc_p->core_3v3_compensation);
  76. core3v3 &= 0x8080ffe0;
  77. core3v3 |= 0x78000002;
  78. writel(core3v3, &misc_p->core_3v3_compensation);
  79. ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
  80. ddr1v8 &= 0x8080ffc0;
  81. ddr1v8 |= 0x78000004;
  82. writel(ddr1v8, &misc_p->ddr_1v8_compensation);
  83. ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
  84. ddr2v5 &= 0x8080ffc0;
  85. ddr2v5 |= 0x78000004;
  86. writel(ddr2v5, &misc_p->ddr_2v5_compensation);
  87. if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
  88. /* Software memory configuration */
  89. if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
  90. sel_1v8();
  91. else
  92. sel_2v5();
  93. } else {
  94. /* Hardware memory configuration */
  95. if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
  96. sel_1v8();
  97. else
  98. sel_2v5();
  99. }
  100. }
  101. /*
  102. * xxx_boot_selected:
  103. *
  104. * return true if the particular booting option is selected
  105. * return false otherwise
  106. */
  107. static u32 read_bootstrap(void)
  108. {
  109. return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
  110. & CONFIG_SPEAR_BOOTSTRAPMASK;
  111. }
  112. int snor_boot_selected(void)
  113. {
  114. u32 bootstrap = read_bootstrap();
  115. if (SNOR_BOOT_SUPPORTED) {
  116. /* Check whether SNOR boot is selected */
  117. if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
  118. CONFIG_SPEAR_ONLYSNORBOOT)
  119. return true;
  120. if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
  121. CONFIG_SPEAR_NORNAND8BOOT)
  122. return true;
  123. if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
  124. CONFIG_SPEAR_NORNAND16BOOT)
  125. return true;
  126. }
  127. return false;
  128. }
  129. int nand_boot_selected(void)
  130. {
  131. u32 bootstrap = read_bootstrap();
  132. if (NAND_BOOT_SUPPORTED) {
  133. /* Check whether NAND boot is selected */
  134. if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
  135. CONFIG_SPEAR_NORNAND8BOOT)
  136. return true;
  137. if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
  138. CONFIG_SPEAR_NORNAND16BOOT)
  139. return true;
  140. }
  141. return false;
  142. }
  143. int pnor_boot_selected(void)
  144. {
  145. /* Parallel NOR boot is not selected in any SPEAr600 revision */
  146. return false;
  147. }
  148. int usb_boot_selected(void)
  149. {
  150. u32 bootstrap = read_bootstrap();
  151. if (USB_BOOT_SUPPORTED) {
  152. /* Check whether USB boot is selected */
  153. if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
  154. return true;
  155. }
  156. return false;
  157. }
  158. int tftp_boot_selected(void)
  159. {
  160. /* TFTP boot is not selected in any SPEAr600 revision */
  161. return false;
  162. }
  163. int uart_boot_selected(void)
  164. {
  165. /* UART boot is not selected in any SPEAr600 revision */
  166. return false;
  167. }
  168. int spi_boot_selected(void)
  169. {
  170. /* SPI boot is not selected in any SPEAr600 revision */
  171. return false;
  172. }
  173. int i2c_boot_selected(void)
  174. {
  175. /* I2C boot is not selected in any SPEAr600 revision */
  176. return false;
  177. }
  178. int mmc_boot_selected(void)
  179. {
  180. return false;
  181. }
  182. void plat_late_init(void)
  183. {
  184. spear_late_init();
  185. }