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- /* SPDX-License-Identifier: GPL-2.0+ */
- /*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- * 2015 Toradex AG
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
- #define __ASSEMBLY__
- #include <config.h>
- /* image version */
- IMAGE_VERSION 2
- /*
- * Boot Device : sd
- */
- BOOT_FROM sd
- /*
- * Secure boot support
- */
- #ifdef CONFIG_IMX_HAB
- CSF CONFIG_CSF_SIZE
- #endif
- /*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
- /* IOMUXC_GPR_GPR1 */
- DATA 4 0x30340004 0x4F400005
- /* DDR3L */
- /* assuming MEMC_FREQ_RATIO = 2 */
- /* SRC_DDRC_RCR */
- DATA 4 0x30391000 0x00000002
- /* DDRC_MSTR */
- DATA 4 0x307a0000 0x01040001
- /* DDRC_DFIUPD0 */
- DATA 4 0x307a01a0 0x80400003
- /* DDRC_DFIUPD1 */
- DATA 4 0x307a01a4 0x00100020
- /* DDRC_DFIUPD2 */
- DATA 4 0x307a01a8 0x80100004
- /* DDRC_RFSHTMG */
- DATA 4 0x307a0064 0x00400046
- /* DDRC_MP_PCTRL_0 */
- DATA 4 0x307a0490 0x00000001
- /* DDRC_INIT0 */
- DATA 4 0x307a00d0 0x00020083
- /* DDRC_INIT1 */
- DATA 4 0x307a00d4 0x00690000
- /* DDRC_INIT3 MR0/MR1 */
- DATA 4 0x307a00dc 0x09300004
- /* DDRC_INIT4 MR2/MR3 */
- DATA 4 0x307a00e0 0x04480000
- /* DDRC_INIT5 */
- DATA 4 0x307a00e4 0x00100004
- /* DDRC_RANKCTL */
- DATA 4 0x307a00f4 0x0000033f
- /* DDRC_DRAMTMG0 */
- DATA 4 0x307a0100 0x0910090a
- /* DDRC_DRAMTMG1 */
- DATA 4 0x307a0104 0x000d020e
- /* DDRC_DRAMTMG2 */
- DATA 4 0x307a0108 0x03040307
- /* DDRC_DRAMTMG3 */
- DATA 4 0x307a010c 0x00002006
- /* DDRC_DRAMTMG4 */
- DATA 4 0x307a0110 0x04020204
- /* DDRC_DRAMTMG5 */
- DATA 4 0x307a0114 0x03030202
- /* DDRC_DRAMTMG8 */
- DATA 4 0x307a0120 0x00000803
- /* DDRC_ZQCTL0 */
- DATA 4 0x307a0180 0x00800020
- /* DDRC_ZQCTL1 */
- DATA 4 0x307a0184 0x02001000
- /* DDRC_DFITMG0 */
- DATA 4 0x307a0190 0x02098204
- /* DDRC_DFITMG1 */
- DATA 4 0x307a0194 0x00030303
- /* DDRC_ADDRMAP0 */
- DATA 4 0x307a0200 0x0000001f
- /* DDRC_ADDRMAP1 */
- DATA 4 0x307a0204 0x00080808
- /* DDRC_ADDRMAP5 */
- DATA 4 0x307a0214 0x07070707
- /* DDRC_ADDRMAP6 */
- DATA 4 0x307a0218 0x07070707
- /* DDRC_ODTCFG */
- DATA 4 0x307a0240 0x06000601
- /* DDRC_ODTMAP */
- DATA 4 0x307a0244 0x00000001
- /* SRC_DDRC_RCR */
- DATA 4 0x30391000 0x00000000
- /* DDR_PHY_PHY_CON0 */
- DATA 4 0x30790000 0x17420f40
- /* DDR_PHY_PHY_CON1 */
- DATA 4 0x30790004 0x10210100
- /* DDR_PHY_PHY_CON4 */
- DATA 4 0x30790010 0x00060807
- /* DDR_PHY_MDLL_CON0 */
- DATA 4 0x307900b0 0x1010007e
- /* DDR_PHY_DRVDS_CON0 */
- DATA 4 0x3079009c 0x00000d6e
- /* DDR_PHY_OFFSET_RD_CON0 */
- DATA 4 0x30790020 0x08080808
- /* DDR_PHY_OFFSET_WR_CON0 */
- DATA 4 0x30790030 0x08080808
- /* DDR_PHY_CMD_SDLL_CON0 */
- DATA 4 0x30790050 0x01000010
- DATA 4 0x30790050 0x00000010
- /* DDR_PHY_ZQ_CON0 */
- DATA 4 0x307900c0 0x0e407304
- DATA 4 0x307900c0 0x0e447304
- DATA 4 0x307900c0 0x0e447306
- /* DDR_PHY_ZQ_CON1 */
- CHECK_BITS_SET 4 0x307900c4 0x1
- /* DDR_PHY_ZQ_CON0 */
- DATA 4 0x307900c0 0x0e447304
- DATA 4 0x307900c0 0x0e407304
- /* CCM_CCGRn */
- DATA 4 0x30384130 0x00000000
- /* IOMUXC_GPR_GPR8 */
- DATA 4 0x30340020 0x00000178
- /* CCM_CCGRn */
- DATA 4 0x30384130 0x00000002
- /* DDR_PHY_LP_CON0 */
- DATA 4 0x30790018 0x0000000f
- /* DDRC_STAT */
- CHECK_BITS_SET 4 0x307a0004 0x1
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