mx6sllevk.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <asm/arch/clock.h>
  6. #include <asm/arch/crm_regs.h>
  7. #include <asm/arch/iomux.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/mx6-pins.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <asm/gpio.h>
  12. #include <asm/mach-imx/iomux-v3.h>
  13. #include <asm/mach-imx/boot_mode.h>
  14. #include <asm/io.h>
  15. #include <common.h>
  16. #include <linux/sizes.h>
  17. #include <mmc.h>
  18. #include <power/pmic.h>
  19. #include <power/pfuze100_pmic.h>
  20. #include "../common/pfuze.h"
  21. DECLARE_GLOBAL_DATA_PTR;
  22. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  23. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  24. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  25. int dram_init(void)
  26. {
  27. gd->ram_size = imx_ddr_size();
  28. return 0;
  29. }
  30. static iomux_v3_cfg_t const uart1_pads[] = {
  31. MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  32. MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  33. };
  34. static iomux_v3_cfg_t const wdog_pads[] = {
  35. MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  36. };
  37. static void setup_iomux_uart(void)
  38. {
  39. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  40. }
  41. #ifdef CONFIG_DM_PMIC_PFUZE100
  42. int power_init_board(void)
  43. {
  44. struct udevice *dev;
  45. int ret;
  46. u32 dev_id, rev_id, i;
  47. u32 switch_num = 6;
  48. u32 offset = PFUZE100_SW1CMODE;
  49. ret = pmic_get("pfuze100", &dev);
  50. if (ret == -ENODEV)
  51. return 0;
  52. if (ret != 0)
  53. return ret;
  54. dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
  55. rev_id = pmic_reg_read(dev, PFUZE100_REVID);
  56. printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
  57. /* Init mode to APS_PFM */
  58. pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
  59. for (i = 0; i < switch_num - 1; i++)
  60. pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
  61. /* set SW1AB staby volatage 0.975V */
  62. pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
  63. /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
  64. pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
  65. /* set SW1C staby volatage 0.975V */
  66. pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
  67. /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
  68. pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
  69. return 0;
  70. }
  71. #endif
  72. int board_early_init_f(void)
  73. {
  74. setup_iomux_uart();
  75. return 0;
  76. }
  77. int board_init(void)
  78. {
  79. /* Address of boot parameters */
  80. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  81. return 0;
  82. }
  83. int board_late_init(void)
  84. {
  85. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  86. return 0;
  87. }
  88. int checkboard(void)
  89. {
  90. puts("Board: MX6SLL EVK\n");
  91. return 0;
  92. }
  93. int board_mmc_get_env_dev(int devno)
  94. {
  95. return devno;
  96. }
  97. int mmc_map_to_kernel_blk(int devno)
  98. {
  99. return devno;
  100. }