nitrogen6x.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <malloc.h>
  14. #include <asm/arch/mx6-pins.h>
  15. #include <linux/errno.h>
  16. #include <asm/gpio.h>
  17. #include <asm/mach-imx/iomux-v3.h>
  18. #include <asm/mach-imx/mxc_i2c.h>
  19. #include <asm/mach-imx/sata.h>
  20. #include <asm/mach-imx/spi.h>
  21. #include <asm/mach-imx/boot_mode.h>
  22. #include <asm/mach-imx/video.h>
  23. #include <mmc.h>
  24. #include <fsl_esdhc_imx.h>
  25. #include <micrel.h>
  26. #include <miiphy.h>
  27. #include <netdev.h>
  28. #include <asm/arch/crm_regs.h>
  29. #include <asm/arch/mxc_hdmi.h>
  30. #include <i2c.h>
  31. #include <input.h>
  32. #include <netdev.h>
  33. #include <usb/ehci-ci.h>
  34. DECLARE_GLOBAL_DATA_PTR;
  35. #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
  36. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  37. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  38. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  39. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  40. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  41. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  42. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  43. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  44. #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  45. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  46. #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  47. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  48. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  49. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  50. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  51. #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
  52. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  53. PAD_CTL_SRE_SLOW)
  54. #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
  55. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  56. PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  57. #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  58. int dram_init(void)
  59. {
  60. gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
  61. return 0;
  62. }
  63. static iomux_v3_cfg_t const uart1_pads[] = {
  64. MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  65. MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  66. };
  67. static iomux_v3_cfg_t const uart2_pads[] = {
  68. MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  69. MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  70. };
  71. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  72. /* I2C1, SGTL5000 */
  73. static struct i2c_pads_info i2c_pad_info0 = {
  74. .scl = {
  75. .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
  76. .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
  77. .gp = IMX_GPIO_NR(3, 21)
  78. },
  79. .sda = {
  80. .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
  81. .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
  82. .gp = IMX_GPIO_NR(3, 28)
  83. }
  84. };
  85. /* I2C2 Camera, MIPI */
  86. static struct i2c_pads_info i2c_pad_info1 = {
  87. .scl = {
  88. .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
  89. .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
  90. .gp = IMX_GPIO_NR(4, 12)
  91. },
  92. .sda = {
  93. .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
  94. .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  95. .gp = IMX_GPIO_NR(4, 13)
  96. }
  97. };
  98. /* I2C3, J15 - RGB connector */
  99. static struct i2c_pads_info i2c_pad_info2 = {
  100. .scl = {
  101. .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
  102. .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
  103. .gp = IMX_GPIO_NR(1, 5)
  104. },
  105. .sda = {
  106. .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
  107. .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
  108. .gp = IMX_GPIO_NR(7, 11)
  109. }
  110. };
  111. static iomux_v3_cfg_t const usdhc2_pads[] = {
  112. MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  113. MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  114. MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  115. MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  116. MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  117. MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  118. };
  119. static iomux_v3_cfg_t const usdhc3_pads[] = {
  120. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  121. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  122. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  123. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  124. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  125. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  126. MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  127. };
  128. static iomux_v3_cfg_t const usdhc4_pads[] = {
  129. MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  130. MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  131. MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  132. MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  133. MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  134. MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  135. MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  136. };
  137. static iomux_v3_cfg_t const enet_pads1[] = {
  138. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  139. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  140. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  141. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  142. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  143. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  144. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  145. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  146. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  147. /* pin 35 - 1 (PHY_AD2) on reset */
  148. MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
  149. /* pin 32 - 1 - (MODE0) all */
  150. MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
  151. /* pin 31 - 1 - (MODE1) all */
  152. MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
  153. /* pin 28 - 1 - (MODE2) all */
  154. MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  155. /* pin 27 - 1 - (MODE3) all */
  156. MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  157. /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
  158. MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
  159. /* pin 42 PHY nRST */
  160. MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
  161. MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
  162. };
  163. static iomux_v3_cfg_t const enet_pads2[] = {
  164. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  165. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  166. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  167. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  168. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  169. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  170. };
  171. static iomux_v3_cfg_t const misc_pads[] = {
  172. MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
  173. MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP),
  174. MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP),
  175. /* OTG Power enable */
  176. MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM),
  177. };
  178. /* wl1271 pads on nitrogen6x */
  179. static iomux_v3_cfg_t const wl12xx_pads[] = {
  180. (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
  181. | MUX_PAD_CTRL(WEAK_PULLDOWN),
  182. (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
  183. | MUX_PAD_CTRL(OUTPUT_40OHM),
  184. (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK)
  185. | MUX_PAD_CTRL(OUTPUT_40OHM),
  186. };
  187. #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
  188. #define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15)
  189. #define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16)
  190. /* Button assignments for J14 */
  191. static iomux_v3_cfg_t const button_pads[] = {
  192. /* Menu */
  193. MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  194. /* Back */
  195. MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  196. /* Labelled Search (mapped to Power under Android) */
  197. MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  198. /* Home */
  199. MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  200. /* Volume Down */
  201. MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  202. /* Volume Up */
  203. MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  204. };
  205. static void setup_iomux_enet(void)
  206. {
  207. gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
  208. gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
  209. gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
  210. gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
  211. gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
  212. gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
  213. gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
  214. imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
  215. gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
  216. /* Need delay 10ms according to KSZ9021 spec */
  217. udelay(1000 * 10);
  218. gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
  219. gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
  220. imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
  221. udelay(100); /* Wait 100 us before using mii interface */
  222. }
  223. static iomux_v3_cfg_t const usb_pads[] = {
  224. MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
  225. };
  226. static void setup_iomux_uart(void)
  227. {
  228. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  229. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  230. }
  231. #ifdef CONFIG_USB_EHCI_MX6
  232. int board_ehci_hcd_init(int port)
  233. {
  234. imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
  235. /* Reset USB hub */
  236. gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
  237. mdelay(2);
  238. gpio_set_value(IMX_GPIO_NR(7, 12), 1);
  239. return 0;
  240. }
  241. int board_ehci_power(int port, int on)
  242. {
  243. if (port)
  244. return 0;
  245. gpio_set_value(GP_USB_OTG_PWR, on);
  246. return 0;
  247. }
  248. #endif
  249. #ifdef CONFIG_FSL_ESDHC_IMX
  250. static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  251. {USDHC3_BASE_ADDR},
  252. {USDHC4_BASE_ADDR},
  253. };
  254. int board_mmc_getcd(struct mmc *mmc)
  255. {
  256. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  257. int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
  258. IMX_GPIO_NR(2, 6);
  259. gpio_direction_input(gp_cd);
  260. return !gpio_get_value(gp_cd);
  261. }
  262. int board_mmc_init(bd_t *bis)
  263. {
  264. int ret;
  265. u32 index = 0;
  266. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  267. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  268. usdhc_cfg[0].max_bus_width = 4;
  269. usdhc_cfg[1].max_bus_width = 4;
  270. for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
  271. switch (index) {
  272. case 0:
  273. imx_iomux_v3_setup_multiple_pads(
  274. usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  275. break;
  276. case 1:
  277. imx_iomux_v3_setup_multiple_pads(
  278. usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  279. break;
  280. default:
  281. printf("Warning: you configured more USDHC controllers"
  282. "(%d) then supported by the board (%d)\n",
  283. index + 1, CONFIG_SYS_FSL_USDHC_NUM);
  284. return -EINVAL;
  285. }
  286. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  287. if (ret)
  288. return ret;
  289. }
  290. return 0;
  291. }
  292. #endif
  293. #ifdef CONFIG_MXC_SPI
  294. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  295. {
  296. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
  297. }
  298. static iomux_v3_cfg_t const ecspi1_pads[] = {
  299. /* SS1 */
  300. MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
  301. MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  302. MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  303. MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  304. };
  305. static void setup_spi(void)
  306. {
  307. imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
  308. ARRAY_SIZE(ecspi1_pads));
  309. }
  310. #endif
  311. int board_phy_config(struct phy_device *phydev)
  312. {
  313. /* min rx data delay */
  314. ksz9021_phy_extended_write(phydev,
  315. MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
  316. /* min tx data delay */
  317. ksz9021_phy_extended_write(phydev,
  318. MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
  319. /* max rx/tx clock delay, min rx/tx control */
  320. ksz9021_phy_extended_write(phydev,
  321. MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
  322. if (phydev->drv->config)
  323. phydev->drv->config(phydev);
  324. return 0;
  325. }
  326. int board_eth_init(bd_t *bis)
  327. {
  328. uint32_t base = IMX_FEC_BASE;
  329. struct mii_dev *bus = NULL;
  330. struct phy_device *phydev = NULL;
  331. int ret;
  332. gpio_request(WL12XX_WL_IRQ_GP, "wifi_irq");
  333. gpio_request(IMX_GPIO_NR(6, 30), "rgmii_rxc");
  334. gpio_request(IMX_GPIO_NR(6, 25), "rgmii_rd0");
  335. gpio_request(IMX_GPIO_NR(6, 27), "rgmii_rd1");
  336. gpio_request(IMX_GPIO_NR(6, 28), "rgmii_rd2");
  337. gpio_request(IMX_GPIO_NR(6, 29), "rgmii_rd3");
  338. gpio_request(IMX_GPIO_NR(6, 24), "rgmii_rx_ctl");
  339. gpio_request(IMX_GPIO_NR(3, 23), "rgmii_reset_sabrelite");
  340. gpio_request(IMX_GPIO_NR(1, 27), "rgmii_reset_nitrogen6x");
  341. setup_iomux_enet();
  342. #ifdef CONFIG_FEC_MXC
  343. bus = fec_get_miibus(base, -1);
  344. if (!bus)
  345. return -EINVAL;
  346. /* scan phy 4,5,6,7 */
  347. phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
  348. if (!phydev) {
  349. ret = -EINVAL;
  350. goto free_bus;
  351. }
  352. printf("using phy at %d\n", phydev->addr);
  353. ret = fec_probe(bis, -1, base, bus, phydev);
  354. if (ret)
  355. goto free_phydev;
  356. #endif
  357. #ifdef CONFIG_CI_UDC
  358. /* For otg ethernet*/
  359. usb_eth_initialize(bis);
  360. #endif
  361. return 0;
  362. free_phydev:
  363. free(phydev);
  364. free_bus:
  365. free(bus);
  366. return ret;
  367. }
  368. static void setup_buttons(void)
  369. {
  370. imx_iomux_v3_setup_multiple_pads(button_pads,
  371. ARRAY_SIZE(button_pads));
  372. }
  373. #if defined(CONFIG_VIDEO_IPUV3)
  374. static iomux_v3_cfg_t const backlight_pads[] = {
  375. /* Backlight on RGB connector: J15 */
  376. MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
  377. #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
  378. /* Backlight on LVDS connector: J6 */
  379. MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
  380. #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
  381. };
  382. static iomux_v3_cfg_t const rgb_pads[] = {
  383. MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
  384. MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
  385. MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
  386. MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
  387. MX6_PAD_DI0_PIN4__GPIO4_IO20,
  388. MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
  389. MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
  390. MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
  391. MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
  392. MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
  393. MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
  394. MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
  395. MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
  396. MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
  397. MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
  398. MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
  399. MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
  400. MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
  401. MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
  402. MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
  403. MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
  404. MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
  405. MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
  406. MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
  407. MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
  408. MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
  409. MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
  410. MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
  411. MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
  412. };
  413. static void do_enable_hdmi(struct display_info_t const *dev)
  414. {
  415. imx_enable_hdmi_phy();
  416. }
  417. static int detect_i2c(struct display_info_t const *dev)
  418. {
  419. return ((0 == i2c_set_bus_num(dev->bus))
  420. &&
  421. (0 == i2c_probe(dev->addr)));
  422. }
  423. static void enable_lvds(struct display_info_t const *dev)
  424. {
  425. struct iomuxc *iomux = (struct iomuxc *)
  426. IOMUXC_BASE_ADDR;
  427. u32 reg = readl(&iomux->gpr[2]);
  428. reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
  429. writel(reg, &iomux->gpr[2]);
  430. gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
  431. }
  432. static void enable_lvds_jeida(struct display_info_t const *dev)
  433. {
  434. struct iomuxc *iomux = (struct iomuxc *)
  435. IOMUXC_BASE_ADDR;
  436. u32 reg = readl(&iomux->gpr[2]);
  437. reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
  438. |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
  439. writel(reg, &iomux->gpr[2]);
  440. gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
  441. }
  442. static void enable_rgb(struct display_info_t const *dev)
  443. {
  444. imx_iomux_v3_setup_multiple_pads(
  445. rgb_pads,
  446. ARRAY_SIZE(rgb_pads));
  447. gpio_direction_output(RGB_BACKLIGHT_GP, 1);
  448. }
  449. struct display_info_t const displays[] = {{
  450. .bus = 1,
  451. .addr = 0x50,
  452. .pixfmt = IPU_PIX_FMT_RGB24,
  453. .detect = detect_i2c,
  454. .enable = do_enable_hdmi,
  455. .mode = {
  456. .name = "HDMI",
  457. .refresh = 60,
  458. .xres = 1024,
  459. .yres = 768,
  460. .pixclock = 15385,
  461. .left_margin = 220,
  462. .right_margin = 40,
  463. .upper_margin = 21,
  464. .lower_margin = 7,
  465. .hsync_len = 60,
  466. .vsync_len = 10,
  467. .sync = FB_SYNC_EXT,
  468. .vmode = FB_VMODE_NONINTERLACED
  469. } }, {
  470. .bus = 0,
  471. .addr = 0,
  472. .pixfmt = IPU_PIX_FMT_RGB24,
  473. .detect = NULL,
  474. .enable = enable_lvds_jeida,
  475. .mode = {
  476. .name = "LDB-WXGA",
  477. .refresh = 60,
  478. .xres = 1280,
  479. .yres = 800,
  480. .pixclock = 14065,
  481. .left_margin = 40,
  482. .right_margin = 40,
  483. .upper_margin = 3,
  484. .lower_margin = 80,
  485. .hsync_len = 10,
  486. .vsync_len = 10,
  487. .sync = FB_SYNC_EXT,
  488. .vmode = FB_VMODE_NONINTERLACED
  489. } }, {
  490. .bus = 0,
  491. .addr = 0,
  492. .pixfmt = IPU_PIX_FMT_RGB24,
  493. .detect = NULL,
  494. .enable = enable_lvds,
  495. .mode = {
  496. .name = "LDB-WXGA-S",
  497. .refresh = 60,
  498. .xres = 1280,
  499. .yres = 800,
  500. .pixclock = 14065,
  501. .left_margin = 40,
  502. .right_margin = 40,
  503. .upper_margin = 3,
  504. .lower_margin = 80,
  505. .hsync_len = 10,
  506. .vsync_len = 10,
  507. .sync = FB_SYNC_EXT,
  508. .vmode = FB_VMODE_NONINTERLACED
  509. } }, {
  510. .bus = 2,
  511. .addr = 0x4,
  512. .pixfmt = IPU_PIX_FMT_LVDS666,
  513. .detect = detect_i2c,
  514. .enable = enable_lvds,
  515. .mode = {
  516. .name = "Hannstar-XGA",
  517. .refresh = 60,
  518. .xres = 1024,
  519. .yres = 768,
  520. .pixclock = 15385,
  521. .left_margin = 220,
  522. .right_margin = 40,
  523. .upper_margin = 21,
  524. .lower_margin = 7,
  525. .hsync_len = 60,
  526. .vsync_len = 10,
  527. .sync = FB_SYNC_EXT,
  528. .vmode = FB_VMODE_NONINTERLACED
  529. } }, {
  530. .bus = 0,
  531. .addr = 0,
  532. .pixfmt = IPU_PIX_FMT_LVDS666,
  533. .detect = NULL,
  534. .enable = enable_lvds,
  535. .mode = {
  536. .name = "LG-9.7",
  537. .refresh = 60,
  538. .xres = 1024,
  539. .yres = 768,
  540. .pixclock = 15385, /* ~65MHz */
  541. .left_margin = 480,
  542. .right_margin = 260,
  543. .upper_margin = 16,
  544. .lower_margin = 6,
  545. .hsync_len = 250,
  546. .vsync_len = 10,
  547. .sync = FB_SYNC_EXT,
  548. .vmode = FB_VMODE_NONINTERLACED
  549. } }, {
  550. .bus = 2,
  551. .addr = 0x38,
  552. .pixfmt = IPU_PIX_FMT_LVDS666,
  553. .detect = detect_i2c,
  554. .enable = enable_lvds,
  555. .mode = {
  556. .name = "wsvga-lvds",
  557. .refresh = 60,
  558. .xres = 1024,
  559. .yres = 600,
  560. .pixclock = 15385,
  561. .left_margin = 220,
  562. .right_margin = 40,
  563. .upper_margin = 21,
  564. .lower_margin = 7,
  565. .hsync_len = 60,
  566. .vsync_len = 10,
  567. .sync = FB_SYNC_EXT,
  568. .vmode = FB_VMODE_NONINTERLACED
  569. } }, {
  570. .bus = 2,
  571. .addr = 0x10,
  572. .pixfmt = IPU_PIX_FMT_RGB666,
  573. .detect = detect_i2c,
  574. .enable = enable_rgb,
  575. .mode = {
  576. .name = "fusion7",
  577. .refresh = 60,
  578. .xres = 800,
  579. .yres = 480,
  580. .pixclock = 33898,
  581. .left_margin = 96,
  582. .right_margin = 24,
  583. .upper_margin = 3,
  584. .lower_margin = 10,
  585. .hsync_len = 72,
  586. .vsync_len = 7,
  587. .sync = 0x40000002,
  588. .vmode = FB_VMODE_NONINTERLACED
  589. } }, {
  590. .bus = 0,
  591. .addr = 0,
  592. .pixfmt = IPU_PIX_FMT_RGB666,
  593. .detect = NULL,
  594. .enable = enable_rgb,
  595. .mode = {
  596. .name = "svga",
  597. .refresh = 60,
  598. .xres = 800,
  599. .yres = 600,
  600. .pixclock = 15385,
  601. .left_margin = 220,
  602. .right_margin = 40,
  603. .upper_margin = 21,
  604. .lower_margin = 7,
  605. .hsync_len = 60,
  606. .vsync_len = 10,
  607. .sync = 0,
  608. .vmode = FB_VMODE_NONINTERLACED
  609. } }, {
  610. .bus = 2,
  611. .addr = 0x41,
  612. .pixfmt = IPU_PIX_FMT_LVDS666,
  613. .detect = detect_i2c,
  614. .enable = enable_lvds,
  615. .mode = {
  616. .name = "amp1024x600",
  617. .refresh = 60,
  618. .xres = 1024,
  619. .yres = 600,
  620. .pixclock = 15385,
  621. .left_margin = 220,
  622. .right_margin = 40,
  623. .upper_margin = 21,
  624. .lower_margin = 7,
  625. .hsync_len = 60,
  626. .vsync_len = 10,
  627. .sync = FB_SYNC_EXT,
  628. .vmode = FB_VMODE_NONINTERLACED
  629. } }, {
  630. .bus = 0,
  631. .addr = 0,
  632. .pixfmt = IPU_PIX_FMT_LVDS666,
  633. .detect = 0,
  634. .enable = enable_lvds,
  635. .mode = {
  636. .name = "wvga-lvds",
  637. .refresh = 57,
  638. .xres = 800,
  639. .yres = 480,
  640. .pixclock = 15385,
  641. .left_margin = 220,
  642. .right_margin = 40,
  643. .upper_margin = 21,
  644. .lower_margin = 7,
  645. .hsync_len = 60,
  646. .vsync_len = 10,
  647. .sync = FB_SYNC_EXT,
  648. .vmode = FB_VMODE_NONINTERLACED
  649. } }, {
  650. .bus = 2,
  651. .addr = 0x48,
  652. .pixfmt = IPU_PIX_FMT_RGB666,
  653. .detect = detect_i2c,
  654. .enable = enable_rgb,
  655. .mode = {
  656. .name = "wvga-rgb",
  657. .refresh = 57,
  658. .xres = 800,
  659. .yres = 480,
  660. .pixclock = 37037,
  661. .left_margin = 40,
  662. .right_margin = 60,
  663. .upper_margin = 10,
  664. .lower_margin = 10,
  665. .hsync_len = 20,
  666. .vsync_len = 10,
  667. .sync = 0,
  668. .vmode = FB_VMODE_NONINTERLACED
  669. } }, {
  670. .bus = 0,
  671. .addr = 0,
  672. .pixfmt = IPU_PIX_FMT_RGB24,
  673. .detect = NULL,
  674. .enable = enable_rgb,
  675. .mode = {
  676. .name = "qvga",
  677. .refresh = 60,
  678. .xres = 320,
  679. .yres = 240,
  680. .pixclock = 37037,
  681. .left_margin = 38,
  682. .right_margin = 37,
  683. .upper_margin = 16,
  684. .lower_margin = 15,
  685. .hsync_len = 30,
  686. .vsync_len = 3,
  687. .sync = 0,
  688. .vmode = FB_VMODE_NONINTERLACED
  689. } } };
  690. size_t display_count = ARRAY_SIZE(displays);
  691. int board_cfb_skip(void)
  692. {
  693. return NULL != env_get("novideo");
  694. }
  695. static void setup_display(void)
  696. {
  697. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  698. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  699. int reg;
  700. enable_ipu_clock();
  701. imx_setup_hdmi();
  702. /* Turn on LDB0,IPU,IPU DI0 clocks */
  703. reg = __raw_readl(&mxc_ccm->CCGR3);
  704. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  705. writel(reg, &mxc_ccm->CCGR3);
  706. /* set LDB0, LDB1 clk select to 011/011 */
  707. reg = readl(&mxc_ccm->cs2cdr);
  708. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  709. |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  710. reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  711. |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  712. writel(reg, &mxc_ccm->cs2cdr);
  713. reg = readl(&mxc_ccm->cscmr2);
  714. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  715. writel(reg, &mxc_ccm->cscmr2);
  716. reg = readl(&mxc_ccm->chsccdr);
  717. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  718. <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  719. writel(reg, &mxc_ccm->chsccdr);
  720. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  721. |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  722. |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  723. |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  724. |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  725. |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  726. |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  727. |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  728. |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  729. writel(reg, &iomux->gpr[2]);
  730. reg = readl(&iomux->gpr[3]);
  731. reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
  732. |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
  733. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  734. <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  735. writel(reg, &iomux->gpr[3]);
  736. /* backlights off until needed */
  737. imx_iomux_v3_setup_multiple_pads(backlight_pads,
  738. ARRAY_SIZE(backlight_pads));
  739. gpio_direction_input(LVDS_BACKLIGHT_GP);
  740. gpio_direction_input(RGB_BACKLIGHT_GP);
  741. }
  742. #endif
  743. static iomux_v3_cfg_t const init_pads[] = {
  744. /* SGTL5000 sys_mclk */
  745. NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
  746. /* J5 - Camera MCLK */
  747. NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
  748. /* wl1271 pads on nitrogen6x */
  749. /* WL12XX_WL_IRQ_GP */
  750. NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
  751. /* WL12XX_WL_ENABLE_GP */
  752. NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
  753. /* WL12XX_BT_ENABLE_GP */
  754. NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
  755. /* USB otg power */
  756. NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
  757. NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
  758. NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
  759. NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
  760. NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
  761. };
  762. #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
  763. static unsigned gpios_out_low[] = {
  764. /* Disable wl1271 */
  765. IMX_GPIO_NR(6, 15), /* disable wireless */
  766. IMX_GPIO_NR(6, 16), /* disable bluetooth */
  767. IMX_GPIO_NR(3, 22), /* disable USB otg power */
  768. IMX_GPIO_NR(2, 5), /* ov5640 mipi camera reset */
  769. IMX_GPIO_NR(1, 8), /* ov5642 reset */
  770. };
  771. static unsigned gpios_out_high[] = {
  772. IMX_GPIO_NR(1, 6), /* ov5642 powerdown */
  773. IMX_GPIO_NR(6, 9), /* ov5640 mipi camera power down */
  774. };
  775. static void set_gpios(unsigned *p, int cnt, int val)
  776. {
  777. int i;
  778. for (i = 0; i < cnt; i++)
  779. gpio_direction_output(*p++, val);
  780. }
  781. int board_early_init_f(void)
  782. {
  783. setup_iomux_uart();
  784. set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
  785. set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
  786. gpio_direction_input(WL12XX_WL_IRQ_GP);
  787. imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
  788. imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
  789. setup_buttons();
  790. #if defined(CONFIG_VIDEO_IPUV3)
  791. setup_display();
  792. #endif
  793. return 0;
  794. }
  795. /*
  796. * Do not overwrite the console
  797. * Use always serial for U-Boot console
  798. */
  799. int overwrite_console(void)
  800. {
  801. return 1;
  802. }
  803. int board_init(void)
  804. {
  805. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  806. clrsetbits_le32(&iomuxc_regs->gpr[1],
  807. IOMUXC_GPR1_OTG_ID_MASK,
  808. IOMUXC_GPR1_OTG_ID_GPIO1);
  809. imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
  810. /* address of boot parameters */
  811. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  812. #ifdef CONFIG_MXC_SPI
  813. setup_spi();
  814. #endif
  815. imx_iomux_v3_setup_multiple_pads(
  816. usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  817. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
  818. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  819. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  820. #ifdef CONFIG_SATA
  821. setup_sata();
  822. #endif
  823. return 0;
  824. }
  825. int checkboard(void)
  826. {
  827. int ret = gpio_get_value(WL12XX_WL_IRQ_GP);
  828. if (ret < 0) {
  829. /* The gpios have not been probed yet. Read it myself */
  830. struct gpio_regs *regs = (struct gpio_regs *)GPIO6_BASE_ADDR;
  831. int gpio = WL12XX_WL_IRQ_GP & 0x1f;
  832. ret = (readl(&regs->gpio_psr) >> gpio) & 0x01;
  833. }
  834. if (ret)
  835. puts("Board: Nitrogen6X\n");
  836. else
  837. puts("Board: SABRE Lite\n");
  838. return 0;
  839. }
  840. struct button_key {
  841. char const *name;
  842. unsigned gpnum;
  843. char ident;
  844. };
  845. static struct button_key const buttons[] = {
  846. {"back", IMX_GPIO_NR(2, 2), 'B'},
  847. {"home", IMX_GPIO_NR(2, 4), 'H'},
  848. {"menu", IMX_GPIO_NR(2, 1), 'M'},
  849. {"search", IMX_GPIO_NR(2, 3), 'S'},
  850. {"volup", IMX_GPIO_NR(7, 13), 'V'},
  851. {"voldown", IMX_GPIO_NR(4, 5), 'v'},
  852. };
  853. /*
  854. * generate a null-terminated string containing the buttons pressed
  855. * returns number of keys pressed
  856. */
  857. static int read_keys(char *buf)
  858. {
  859. int i, numpressed = 0;
  860. for (i = 0; i < ARRAY_SIZE(buttons); i++) {
  861. if (!gpio_get_value(buttons[i].gpnum))
  862. buf[numpressed++] = buttons[i].ident;
  863. }
  864. buf[numpressed] = '\0';
  865. return numpressed;
  866. }
  867. static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  868. {
  869. char envvalue[ARRAY_SIZE(buttons)+1];
  870. int numpressed = read_keys(envvalue);
  871. env_set("keybd", envvalue);
  872. return numpressed == 0;
  873. }
  874. U_BOOT_CMD(
  875. kbd, 1, 1, do_kbd,
  876. "Tests for keypresses, sets 'keybd' environment variable",
  877. "Returns 0 (true) to shell if key is pressed."
  878. );
  879. #ifdef CONFIG_PREBOOT
  880. static char const kbd_magic_prefix[] = "key_magic";
  881. static char const kbd_command_prefix[] = "key_cmd";
  882. static void preboot_keys(void)
  883. {
  884. int numpressed;
  885. char keypress[ARRAY_SIZE(buttons)+1];
  886. numpressed = read_keys(keypress);
  887. if (numpressed) {
  888. char *kbd_magic_keys = env_get("magic_keys");
  889. char *suffix;
  890. /*
  891. * loop over all magic keys
  892. */
  893. for (suffix = kbd_magic_keys; *suffix; ++suffix) {
  894. char *keys;
  895. char magic[sizeof(kbd_magic_prefix) + 1];
  896. sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
  897. keys = env_get(magic);
  898. if (keys) {
  899. if (!strcmp(keys, keypress))
  900. break;
  901. }
  902. }
  903. if (*suffix) {
  904. char cmd_name[sizeof(kbd_command_prefix) + 1];
  905. char *cmd;
  906. sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
  907. cmd = env_get(cmd_name);
  908. if (cmd) {
  909. env_set("preboot", cmd);
  910. return;
  911. }
  912. }
  913. }
  914. }
  915. #endif
  916. #ifdef CONFIG_CMD_BMODE
  917. static const struct boot_mode board_boot_modes[] = {
  918. /* 4 bit bus width */
  919. {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  920. {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
  921. {NULL, 0},
  922. };
  923. #endif
  924. int misc_init_r(void)
  925. {
  926. gpio_request(RGB_BACKLIGHT_GP, "lvds backlight");
  927. gpio_request(LVDS_BACKLIGHT_GP, "lvds backlight");
  928. gpio_request(GP_USB_OTG_PWR, "usbotg power");
  929. gpio_request(IMX_GPIO_NR(7, 12), "usbh1 hub reset");
  930. gpio_request(IMX_GPIO_NR(2, 2), "back");
  931. gpio_request(IMX_GPIO_NR(2, 4), "home");
  932. gpio_request(IMX_GPIO_NR(2, 1), "menu");
  933. gpio_request(IMX_GPIO_NR(2, 3), "search");
  934. gpio_request(IMX_GPIO_NR(7, 13), "volup");
  935. gpio_request(IMX_GPIO_NR(4, 5), "voldown");
  936. #ifdef CONFIG_PREBOOT
  937. preboot_keys();
  938. #endif
  939. #ifdef CONFIG_CMD_BMODE
  940. add_board_boot_modes(board_boot_modes);
  941. #endif
  942. env_set_hex("reset_cause", get_imx_reset_cause());
  943. return 0;
  944. }