soc.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <asm/io.h>
  6. #include <asm/arch/clock.h>
  7. #include <asm/arch/imx-regs.h>
  8. #include <asm/arch/sys_proto.h>
  9. #include <asm/mach-imx/boot_mode.h>
  10. #include <asm/mach-imx/hab.h>
  11. static char *get_reset_cause(char *);
  12. #if defined(CONFIG_IMX_HAB)
  13. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  14. .bank = 29,
  15. .word = 6,
  16. };
  17. #endif
  18. #define ROM_VERSION_ADDR 0x80
  19. u32 get_cpu_rev(void)
  20. {
  21. /* Check the ROM version for cpu revision */
  22. u32 rom_version = readl((void __iomem *)ROM_VERSION_ADDR);
  23. return (MXC_CPU_MX7ULP << 12) | (rom_version & 0xFF);
  24. }
  25. #ifdef CONFIG_REVISION_TAG
  26. u32 __weak get_board_rev(void)
  27. {
  28. return get_cpu_rev();
  29. }
  30. #endif
  31. enum bt_mode get_boot_mode(void)
  32. {
  33. u32 bt0_cfg = 0;
  34. bt0_cfg = readl(CMC0_RBASE + 0x40);
  35. bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
  36. if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
  37. /* No low power boot */
  38. if (bt0_cfg & BT0CFG_DUALBOOT_MASK)
  39. return DUAL_BOOT;
  40. else
  41. return SINGLE_BOOT;
  42. }
  43. return LOW_POWER_BOOT;
  44. }
  45. int arch_cpu_init(void)
  46. {
  47. return 0;
  48. }
  49. #ifdef CONFIG_BOARD_POSTCLK_INIT
  50. int board_postclk_init(void)
  51. {
  52. return 0;
  53. }
  54. #endif
  55. #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
  56. #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
  57. #define REFRESH_WORD0 0xA602 /* 1st refresh word */
  58. #define REFRESH_WORD1 0xB480 /* 2nd refresh word */
  59. static void disable_wdog(u32 wdog_base)
  60. {
  61. writel(UNLOCK_WORD0, (wdog_base + 0x04));
  62. writel(UNLOCK_WORD1, (wdog_base + 0x04));
  63. writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
  64. writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
  65. writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
  66. writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
  67. writel(REFRESH_WORD1, (wdog_base + 0x04));
  68. }
  69. void init_wdog(void)
  70. {
  71. /*
  72. * ROM will configure WDOG1, disable it or enable it
  73. * depending on FUSE. The update bit is set for reconfigurable.
  74. * We have to use unlock sequence to reconfigure it.
  75. * WDOG2 is not touched by ROM, so it will have default value
  76. * which is enabled. We can directly configure it.
  77. * To simplify the codes, we still use same reconfigure
  78. * process as WDOG1. Because the update bit is not set for
  79. * WDOG2, the unlock sequence won't take effect really.
  80. * It actually directly configure the wdog.
  81. * In this function, we will disable both WDOG1 and WDOG2,
  82. * and set update bit for both. So that kernel can reconfigure them.
  83. */
  84. disable_wdog(WDG1_RBASE);
  85. disable_wdog(WDG2_RBASE);
  86. }
  87. void s_init(void)
  88. {
  89. /* Disable wdog */
  90. init_wdog();
  91. /* clock configuration. */
  92. clock_init();
  93. if (soc_rev() < CHIP_REV_2_0) {
  94. /* enable dumb pmic */
  95. writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR);
  96. }
  97. return;
  98. }
  99. #ifndef CONFIG_ULP_WATCHDOG
  100. void reset_cpu(ulong addr)
  101. {
  102. setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET);
  103. while (1)
  104. ;
  105. }
  106. #endif
  107. #if defined(CONFIG_DISPLAY_CPUINFO)
  108. const char *get_imx_type(u32 imxtype)
  109. {
  110. return "7ULP";
  111. }
  112. int print_cpuinfo(void)
  113. {
  114. u32 cpurev;
  115. char cause[18];
  116. cpurev = get_cpu_rev();
  117. printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
  118. get_imx_type((cpurev & 0xFF000) >> 12),
  119. (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
  120. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  121. printf("Reset cause: %s\n", get_reset_cause(cause));
  122. printf("Boot mode: ");
  123. switch (get_boot_mode()) {
  124. case LOW_POWER_BOOT:
  125. printf("Low power boot\n");
  126. break;
  127. case DUAL_BOOT:
  128. printf("Dual boot\n");
  129. break;
  130. case SINGLE_BOOT:
  131. default:
  132. printf("Single boot\n");
  133. break;
  134. }
  135. return 0;
  136. }
  137. #endif
  138. #define CMC_SRS_TAMPER (1 << 31)
  139. #define CMC_SRS_SECURITY (1 << 30)
  140. #define CMC_SRS_TZWDG (1 << 29)
  141. #define CMC_SRS_JTAG_RST (1 << 28)
  142. #define CMC_SRS_CORE1 (1 << 16)
  143. #define CMC_SRS_LOCKUP (1 << 15)
  144. #define CMC_SRS_SW (1 << 14)
  145. #define CMC_SRS_WDG (1 << 13)
  146. #define CMC_SRS_PIN_RESET (1 << 8)
  147. #define CMC_SRS_WARM (1 << 4)
  148. #define CMC_SRS_HVD (1 << 3)
  149. #define CMC_SRS_LVD (1 << 2)
  150. #define CMC_SRS_POR (1 << 1)
  151. #define CMC_SRS_WUP (1 << 0)
  152. static u32 reset_cause = -1;
  153. static char *get_reset_cause(char *ret)
  154. {
  155. u32 cause1, cause = 0, srs = 0;
  156. u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28);
  157. u32 *reg_srs = (u32 *)(SRC_BASE_ADDR + 0x20);
  158. if (!ret)
  159. return "null";
  160. srs = readl(reg_srs);
  161. cause1 = readl(reg_ssrs);
  162. writel(cause1, reg_ssrs);
  163. reset_cause = cause1;
  164. cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
  165. switch (cause) {
  166. case CMC_SRS_POR:
  167. sprintf(ret, "%s", "POR");
  168. break;
  169. case CMC_SRS_WUP:
  170. sprintf(ret, "%s", "WUP");
  171. break;
  172. case CMC_SRS_WARM:
  173. cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW |
  174. CMC_SRS_JTAG_RST);
  175. switch (cause) {
  176. case CMC_SRS_WDG:
  177. sprintf(ret, "%s", "WARM-WDG");
  178. break;
  179. case CMC_SRS_SW:
  180. sprintf(ret, "%s", "WARM-SW");
  181. break;
  182. case CMC_SRS_JTAG_RST:
  183. sprintf(ret, "%s", "WARM-JTAG");
  184. break;
  185. default:
  186. sprintf(ret, "%s", "WARM-UNKN");
  187. break;
  188. }
  189. break;
  190. default:
  191. sprintf(ret, "%s-%X", "UNKN", cause1);
  192. break;
  193. }
  194. debug("[%X] SRS[%X] %X - ", cause1, srs, srs^cause1);
  195. return ret;
  196. }
  197. #ifdef CONFIG_ENV_IS_IN_MMC
  198. __weak int board_mmc_get_env_dev(int devno)
  199. {
  200. return CONFIG_SYS_MMC_ENV_DEV;
  201. }
  202. int mmc_get_env_dev(void)
  203. {
  204. int devno = 0;
  205. u32 bt1_cfg = 0;
  206. /* If not boot from sd/mmc, use default value */
  207. if (get_boot_mode() == LOW_POWER_BOOT)
  208. return CONFIG_SYS_MMC_ENV_DEV;
  209. bt1_cfg = readl(CMC1_RBASE + 0x40);
  210. devno = (bt1_cfg >> 9) & 0x7;
  211. return board_mmc_get_env_dev(devno);
  212. }
  213. #endif
  214. enum boot_device get_boot_device(void)
  215. {
  216. struct bootrom_sw_info **p =
  217. (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
  218. enum boot_device boot_dev = SD1_BOOT;
  219. u8 boot_type = (*p)->boot_dev_type;
  220. u8 boot_instance = (*p)->boot_dev_instance;
  221. switch (boot_type) {
  222. case BOOT_TYPE_SD:
  223. boot_dev = boot_instance + SD1_BOOT;
  224. break;
  225. case BOOT_TYPE_MMC:
  226. boot_dev = boot_instance + MMC1_BOOT;
  227. break;
  228. case BOOT_TYPE_USB:
  229. boot_dev = USB_BOOT;
  230. break;
  231. default:
  232. break;
  233. }
  234. return boot_dev;
  235. }