scg.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <div64.h>
  7. #include <asm/io.h>
  8. #include <errno.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/pcc.h>
  11. #include <asm/arch/sys_proto.h>
  12. scg_p scg1_regs = (scg_p)SCG1_RBASE;
  13. static u32 scg_src_get_rate(enum scg_clk clksrc)
  14. {
  15. u32 reg;
  16. switch (clksrc) {
  17. case SCG_SOSC_CLK:
  18. reg = readl(&scg1_regs->sosccsr);
  19. if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK))
  20. return 0;
  21. return 24000000;
  22. case SCG_FIRC_CLK:
  23. reg = readl(&scg1_regs->firccsr);
  24. if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK))
  25. return 0;
  26. return 48000000;
  27. case SCG_SIRC_CLK:
  28. reg = readl(&scg1_regs->sirccsr);
  29. if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK))
  30. return 0;
  31. return 16000000;
  32. case SCG_ROSC_CLK:
  33. reg = readl(&scg1_regs->rtccsr);
  34. if (!(reg & SCG_ROSC_CSR_ROSCVLD_MASK))
  35. return 0;
  36. return 32768;
  37. default:
  38. break;
  39. }
  40. return 0;
  41. }
  42. static u32 scg_sircdiv_get_rate(enum scg_clk clk)
  43. {
  44. u32 reg, val, rate;
  45. u32 shift, mask;
  46. switch (clk) {
  47. case SCG_SIRC_DIV1_CLK:
  48. mask = SCG_SIRCDIV_DIV1_MASK;
  49. shift = SCG_SIRCDIV_DIV1_SHIFT;
  50. break;
  51. case SCG_SIRC_DIV2_CLK:
  52. mask = SCG_SIRCDIV_DIV2_MASK;
  53. shift = SCG_SIRCDIV_DIV2_SHIFT;
  54. break;
  55. case SCG_SIRC_DIV3_CLK:
  56. mask = SCG_SIRCDIV_DIV3_MASK;
  57. shift = SCG_SIRCDIV_DIV3_SHIFT;
  58. break;
  59. default:
  60. return 0;
  61. }
  62. reg = readl(&scg1_regs->sirccsr);
  63. if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK))
  64. return 0;
  65. reg = readl(&scg1_regs->sircdiv);
  66. val = (reg & mask) >> shift;
  67. if (!val) /*clock disabled*/
  68. return 0;
  69. rate = scg_src_get_rate(SCG_SIRC_CLK);
  70. rate = rate / (1 << (val - 1));
  71. return rate;
  72. }
  73. static u32 scg_fircdiv_get_rate(enum scg_clk clk)
  74. {
  75. u32 reg, val, rate;
  76. u32 shift, mask;
  77. switch (clk) {
  78. case SCG_FIRC_DIV1_CLK:
  79. mask = SCG_FIRCDIV_DIV1_MASK;
  80. shift = SCG_FIRCDIV_DIV1_SHIFT;
  81. break;
  82. case SCG_FIRC_DIV2_CLK:
  83. mask = SCG_FIRCDIV_DIV2_MASK;
  84. shift = SCG_FIRCDIV_DIV2_SHIFT;
  85. break;
  86. case SCG_FIRC_DIV3_CLK:
  87. mask = SCG_FIRCDIV_DIV3_MASK;
  88. shift = SCG_FIRCDIV_DIV3_SHIFT;
  89. break;
  90. default:
  91. return 0;
  92. }
  93. reg = readl(&scg1_regs->firccsr);
  94. if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK))
  95. return 0;
  96. reg = readl(&scg1_regs->fircdiv);
  97. val = (reg & mask) >> shift;
  98. if (!val) /*clock disabled*/
  99. return 0;
  100. rate = scg_src_get_rate(SCG_FIRC_CLK);
  101. rate = rate / (1 << (val - 1));
  102. return rate;
  103. }
  104. static u32 scg_soscdiv_get_rate(enum scg_clk clk)
  105. {
  106. u32 reg, val, rate;
  107. u32 shift, mask;
  108. switch (clk) {
  109. case SCG_SOSC_DIV1_CLK:
  110. mask = SCG_SOSCDIV_DIV1_MASK;
  111. shift = SCG_SOSCDIV_DIV1_SHIFT;
  112. break;
  113. case SCG_SOSC_DIV2_CLK:
  114. mask = SCG_SOSCDIV_DIV2_MASK;
  115. shift = SCG_SOSCDIV_DIV2_SHIFT;
  116. break;
  117. case SCG_SOSC_DIV3_CLK:
  118. mask = SCG_SOSCDIV_DIV3_MASK;
  119. shift = SCG_SOSCDIV_DIV3_SHIFT;
  120. break;
  121. default:
  122. return 0;
  123. }
  124. reg = readl(&scg1_regs->sosccsr);
  125. if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK))
  126. return 0;
  127. reg = readl(&scg1_regs->soscdiv);
  128. val = (reg & mask) >> shift;
  129. if (!val) /*clock disabled*/
  130. return 0;
  131. rate = scg_src_get_rate(SCG_SOSC_CLK);
  132. rate = rate / (1 << (val - 1));
  133. return rate;
  134. }
  135. static u32 scg_apll_pfd_get_rate(enum scg_clk clk)
  136. {
  137. u32 reg, val, rate;
  138. u32 shift, mask, gate, valid;
  139. switch (clk) {
  140. case SCG_APLL_PFD0_CLK:
  141. gate = SCG_PLL_PFD0_GATE_MASK;
  142. valid = SCG_PLL_PFD0_VALID_MASK;
  143. mask = SCG_PLL_PFD0_FRAC_MASK;
  144. shift = SCG_PLL_PFD0_FRAC_SHIFT;
  145. break;
  146. case SCG_APLL_PFD1_CLK:
  147. gate = SCG_PLL_PFD1_GATE_MASK;
  148. valid = SCG_PLL_PFD1_VALID_MASK;
  149. mask = SCG_PLL_PFD1_FRAC_MASK;
  150. shift = SCG_PLL_PFD1_FRAC_SHIFT;
  151. break;
  152. case SCG_APLL_PFD2_CLK:
  153. gate = SCG_PLL_PFD2_GATE_MASK;
  154. valid = SCG_PLL_PFD2_VALID_MASK;
  155. mask = SCG_PLL_PFD2_FRAC_MASK;
  156. shift = SCG_PLL_PFD2_FRAC_SHIFT;
  157. break;
  158. case SCG_APLL_PFD3_CLK:
  159. gate = SCG_PLL_PFD3_GATE_MASK;
  160. valid = SCG_PLL_PFD3_VALID_MASK;
  161. mask = SCG_PLL_PFD3_FRAC_MASK;
  162. shift = SCG_PLL_PFD3_FRAC_SHIFT;
  163. break;
  164. default:
  165. return 0;
  166. }
  167. reg = readl(&scg1_regs->apllpfd);
  168. if (reg & gate || !(reg & valid))
  169. return 0;
  170. clk_debug("scg_apll_pfd_get_rate reg 0x%x\n", reg);
  171. val = (reg & mask) >> shift;
  172. rate = decode_pll(PLL_A7_APLL);
  173. rate = rate / val * 18;
  174. clk_debug("scg_apll_pfd_get_rate rate %u\n", rate);
  175. return rate;
  176. }
  177. static u32 scg_spll_pfd_get_rate(enum scg_clk clk)
  178. {
  179. u32 reg, val, rate;
  180. u32 shift, mask, gate, valid;
  181. switch (clk) {
  182. case SCG_SPLL_PFD0_CLK:
  183. gate = SCG_PLL_PFD0_GATE_MASK;
  184. valid = SCG_PLL_PFD0_VALID_MASK;
  185. mask = SCG_PLL_PFD0_FRAC_MASK;
  186. shift = SCG_PLL_PFD0_FRAC_SHIFT;
  187. break;
  188. case SCG_SPLL_PFD1_CLK:
  189. gate = SCG_PLL_PFD1_GATE_MASK;
  190. valid = SCG_PLL_PFD1_VALID_MASK;
  191. mask = SCG_PLL_PFD1_FRAC_MASK;
  192. shift = SCG_PLL_PFD1_FRAC_SHIFT;
  193. break;
  194. case SCG_SPLL_PFD2_CLK:
  195. gate = SCG_PLL_PFD2_GATE_MASK;
  196. valid = SCG_PLL_PFD2_VALID_MASK;
  197. mask = SCG_PLL_PFD2_FRAC_MASK;
  198. shift = SCG_PLL_PFD2_FRAC_SHIFT;
  199. break;
  200. case SCG_SPLL_PFD3_CLK:
  201. gate = SCG_PLL_PFD3_GATE_MASK;
  202. valid = SCG_PLL_PFD3_VALID_MASK;
  203. mask = SCG_PLL_PFD3_FRAC_MASK;
  204. shift = SCG_PLL_PFD3_FRAC_SHIFT;
  205. break;
  206. default:
  207. return 0;
  208. }
  209. reg = readl(&scg1_regs->spllpfd);
  210. if (reg & gate || !(reg & valid))
  211. return 0;
  212. clk_debug("scg_spll_pfd_get_rate reg 0x%x\n", reg);
  213. val = (reg & mask) >> shift;
  214. rate = decode_pll(PLL_A7_SPLL);
  215. rate = rate / val * 18;
  216. clk_debug("scg_spll_pfd_get_rate rate %u\n", rate);
  217. return rate;
  218. }
  219. static u32 scg_apll_get_rate(void)
  220. {
  221. u32 reg, val, rate;
  222. reg = readl(&scg1_regs->apllcfg);
  223. val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT;
  224. if (!val) {
  225. /* APLL clock after two dividers */
  226. rate = decode_pll(PLL_A7_APLL);
  227. val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >>
  228. SCG_PLL_CFG_POSTDIV1_SHIFT;
  229. rate = rate / (val + 1);
  230. val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >>
  231. SCG_PLL_CFG_POSTDIV2_SHIFT;
  232. rate = rate / (val + 1);
  233. } else {
  234. /* APLL PFD clock */
  235. val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
  236. SCG_PLL_CFG_PFDSEL_SHIFT;
  237. rate = scg_apll_pfd_get_rate(SCG_APLL_PFD0_CLK + val);
  238. }
  239. return rate;
  240. }
  241. static u32 scg_spll_get_rate(void)
  242. {
  243. u32 reg, val, rate;
  244. reg = readl(&scg1_regs->spllcfg);
  245. val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT;
  246. clk_debug("scg_spll_get_rate reg 0x%x\n", reg);
  247. if (!val) {
  248. /* APLL clock after two dividers */
  249. rate = decode_pll(PLL_A7_SPLL);
  250. val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >>
  251. SCG_PLL_CFG_POSTDIV1_SHIFT;
  252. rate = rate / (val + 1);
  253. val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >>
  254. SCG_PLL_CFG_POSTDIV2_SHIFT;
  255. rate = rate / (val + 1);
  256. clk_debug("scg_spll_get_rate SPLL %u\n", rate);
  257. } else {
  258. /* APLL PFD clock */
  259. val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
  260. SCG_PLL_CFG_PFDSEL_SHIFT;
  261. rate = scg_spll_pfd_get_rate(SCG_SPLL_PFD0_CLK + val);
  262. clk_debug("scg_spll_get_rate PFD %u\n", rate);
  263. }
  264. return rate;
  265. }
  266. static u32 scg_ddr_get_rate(void)
  267. {
  268. u32 reg, val, rate, div;
  269. reg = readl(&scg1_regs->ddrccr);
  270. val = (reg & SCG_DDRCCR_DDRCS_MASK) >> SCG_DDRCCR_DDRCS_SHIFT;
  271. div = (reg & SCG_DDRCCR_DDRDIV_MASK) >> SCG_DDRCCR_DDRDIV_SHIFT;
  272. if (!div)
  273. return 0;
  274. if (!val) {
  275. reg = readl(&scg1_regs->apllcfg);
  276. val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
  277. SCG_PLL_CFG_PFDSEL_SHIFT;
  278. rate = scg_apll_pfd_get_rate(SCG_APLL_PFD0_CLK + val);
  279. } else {
  280. rate = decode_pll(PLL_USB);
  281. }
  282. rate = rate / (1 << (div - 1));
  283. return rate;
  284. }
  285. static u32 scg_nic_get_rate(enum scg_clk clk)
  286. {
  287. u32 reg, val, rate, nic0_rate;
  288. u32 shift, mask;
  289. reg = readl(&scg1_regs->niccsr);
  290. val = (reg & SCG_NICCSR_NICCS_MASK) >> SCG_NICCSR_NICCS_SHIFT;
  291. clk_debug("scg_nic_get_rate niccsr 0x%x\n", reg);
  292. if (!val)
  293. rate = scg_src_get_rate(SCG_FIRC_CLK);
  294. else
  295. rate = scg_ddr_get_rate();
  296. clk_debug("scg_nic_get_rate parent rate %u\n", rate);
  297. val = (reg & SCG_NICCSR_NIC0DIV_MASK) >> SCG_NICCSR_NIC0DIV_SHIFT;
  298. rate = rate / (val + 1);
  299. nic0_rate = rate;
  300. clk_debug("scg_nic_get_rate NIC0 rate %u\n", rate);
  301. switch (clk) {
  302. case SCG_NIC0_CLK:
  303. return rate;
  304. case SCG_GPU_CLK:
  305. mask = SCG_NICCSR_GPUDIV_MASK;
  306. shift = SCG_NICCSR_GPUDIV_SHIFT;
  307. break;
  308. case SCG_NIC1_EXT_CLK:
  309. case SCG_NIC1_BUS_CLK:
  310. case SCG_NIC1_CLK:
  311. mask = SCG_NICCSR_NIC1DIV_MASK;
  312. shift = SCG_NICCSR_NIC1DIV_SHIFT;
  313. break;
  314. default:
  315. return 0;
  316. }
  317. val = (reg & mask) >> shift;
  318. rate = rate / (val + 1);
  319. clk_debug("scg_nic_get_rate NIC1 rate %u\n", rate);
  320. switch (clk) {
  321. case SCG_GPU_CLK:
  322. case SCG_NIC1_CLK:
  323. return rate;
  324. case SCG_NIC1_EXT_CLK:
  325. mask = SCG_NICCSR_NIC1EXTDIV_MASK;
  326. shift = SCG_NICCSR_NIC1EXTDIV_SHIFT;
  327. break;
  328. case SCG_NIC1_BUS_CLK:
  329. mask = SCG_NICCSR_NIC1BUSDIV_MASK;
  330. shift = SCG_NICCSR_NIC1BUSDIV_SHIFT;
  331. break;
  332. default:
  333. return 0;
  334. }
  335. /*
  336. * On RevB, the nic_bus and nic_ext dividers are parallel
  337. * not chained with nic div
  338. */
  339. if (soc_rev() >= CHIP_REV_2_0)
  340. rate = nic0_rate;
  341. val = (reg & mask) >> shift;
  342. rate = rate / (val + 1);
  343. clk_debug("scg_nic_get_rate NIC1 bus rate %u\n", rate);
  344. return rate;
  345. }
  346. static enum scg_clk scg_scs_array[4] = {
  347. SCG_SOSC_CLK, SCG_SIRC_CLK, SCG_FIRC_CLK, SCG_ROSC_CLK,
  348. };
  349. static u32 scg_sys_get_rate(enum scg_clk clk)
  350. {
  351. u32 reg, val, rate;
  352. if (clk != SCG_CORE_CLK && clk != SCG_BUS_CLK)
  353. return 0;
  354. reg = readl(&scg1_regs->csr);
  355. val = (reg & SCG_CCR_SCS_MASK) >> SCG_CCR_SCS_SHIFT;
  356. clk_debug("scg_sys_get_rate reg 0x%x\n", reg);
  357. switch (val) {
  358. case SCG_SCS_SYS_OSC:
  359. case SCG_SCS_SLOW_IRC:
  360. case SCG_SCS_FAST_IRC:
  361. case SCG_SCS_RTC_OSC:
  362. rate = scg_src_get_rate(scg_scs_array[val - 1]);
  363. break;
  364. case 5:
  365. rate = scg_apll_get_rate();
  366. break;
  367. case 6:
  368. rate = scg_spll_get_rate();
  369. break;
  370. default:
  371. return 0;
  372. }
  373. clk_debug("scg_sys_get_rate parent rate %u\n", rate);
  374. val = (reg & SCG_CCR_DIVCORE_MASK) >> SCG_CCR_DIVCORE_SHIFT;
  375. rate = rate / (val + 1);
  376. if (clk == SCG_BUS_CLK) {
  377. val = (reg & SCG_CCR_DIVBUS_MASK) >> SCG_CCR_DIVBUS_SHIFT;
  378. rate = rate / (val + 1);
  379. }
  380. return rate;
  381. }
  382. u32 decode_pll(enum pll_clocks pll)
  383. {
  384. u32 reg, pre_div, infreq, mult;
  385. u32 num, denom;
  386. /*
  387. * Alought there are four choices for the bypass src,
  388. * we choose OSC_24M which is the default set in ROM.
  389. */
  390. switch (pll) {
  391. case PLL_A7_SPLL:
  392. reg = readl(&scg1_regs->spllcsr);
  393. if (!(reg & SCG_SPLL_CSR_SPLLVLD_MASK))
  394. return 0;
  395. reg = readl(&scg1_regs->spllcfg);
  396. pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >>
  397. SCG_PLL_CFG_PREDIV_SHIFT;
  398. pre_div += 1;
  399. mult = (reg & SCG1_SPLL_CFG_MULT_MASK) >>
  400. SCG_PLL_CFG_MULT_SHIFT;
  401. infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >>
  402. SCG_PLL_CFG_CLKSRC_SHIFT;
  403. if (!infreq)
  404. infreq = scg_src_get_rate(SCG_SOSC_CLK);
  405. else
  406. infreq = scg_src_get_rate(SCG_FIRC_CLK);
  407. num = readl(&scg1_regs->spllnum);
  408. denom = readl(&scg1_regs->splldenom);
  409. infreq = infreq / pre_div;
  410. if (denom)
  411. return infreq * mult + infreq * num / denom;
  412. else
  413. return infreq * mult;
  414. case PLL_A7_APLL:
  415. reg = readl(&scg1_regs->apllcsr);
  416. if (!(reg & SCG_APLL_CSR_APLLVLD_MASK))
  417. return 0;
  418. reg = readl(&scg1_regs->apllcfg);
  419. pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >>
  420. SCG_PLL_CFG_PREDIV_SHIFT;
  421. pre_div += 1;
  422. mult = (reg & SCG_APLL_CFG_MULT_MASK) >>
  423. SCG_PLL_CFG_MULT_SHIFT;
  424. infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >>
  425. SCG_PLL_CFG_CLKSRC_SHIFT;
  426. if (!infreq)
  427. infreq = scg_src_get_rate(SCG_SOSC_CLK);
  428. else
  429. infreq = scg_src_get_rate(SCG_FIRC_CLK);
  430. num = readl(&scg1_regs->apllnum);
  431. denom = readl(&scg1_regs->aplldenom);
  432. infreq = infreq / pre_div;
  433. if (denom)
  434. return infreq * mult + infreq * num / denom;
  435. else
  436. return infreq * mult;
  437. case PLL_USB:
  438. reg = readl(&scg1_regs->upllcsr);
  439. if (!(reg & SCG_UPLL_CSR_UPLLVLD_MASK))
  440. return 0;
  441. return 480000000u;
  442. case PLL_MIPI:
  443. return 480000000u;
  444. default:
  445. printf("Unsupported pll clocks %d\n", pll);
  446. break;
  447. }
  448. return 0;
  449. }
  450. u32 scg_clk_get_rate(enum scg_clk clk)
  451. {
  452. switch (clk) {
  453. case SCG_SIRC_DIV1_CLK:
  454. case SCG_SIRC_DIV2_CLK:
  455. case SCG_SIRC_DIV3_CLK:
  456. return scg_sircdiv_get_rate(clk);
  457. case SCG_FIRC_DIV1_CLK:
  458. case SCG_FIRC_DIV2_CLK:
  459. case SCG_FIRC_DIV3_CLK:
  460. return scg_fircdiv_get_rate(clk);
  461. case SCG_SOSC_DIV1_CLK:
  462. case SCG_SOSC_DIV2_CLK:
  463. case SCG_SOSC_DIV3_CLK:
  464. return scg_soscdiv_get_rate(clk);
  465. case SCG_CORE_CLK:
  466. case SCG_BUS_CLK:
  467. return scg_sys_get_rate(clk);
  468. case SCG_SPLL_PFD0_CLK:
  469. case SCG_SPLL_PFD1_CLK:
  470. case SCG_SPLL_PFD2_CLK:
  471. case SCG_SPLL_PFD3_CLK:
  472. return scg_spll_pfd_get_rate(clk);
  473. case SCG_APLL_PFD0_CLK:
  474. case SCG_APLL_PFD1_CLK:
  475. case SCG_APLL_PFD2_CLK:
  476. case SCG_APLL_PFD3_CLK:
  477. return scg_apll_pfd_get_rate(clk);
  478. case SCG_DDR_CLK:
  479. return scg_ddr_get_rate();
  480. case SCG_NIC0_CLK:
  481. case SCG_GPU_CLK:
  482. case SCG_NIC1_CLK:
  483. case SCG_NIC1_BUS_CLK:
  484. case SCG_NIC1_EXT_CLK:
  485. return scg_nic_get_rate(clk);
  486. case USB_PLL_OUT:
  487. return decode_pll(PLL_USB);
  488. case MIPI_PLL_OUT:
  489. return decode_pll(PLL_MIPI);
  490. case SCG_SOSC_CLK:
  491. case SCG_FIRC_CLK:
  492. case SCG_SIRC_CLK:
  493. case SCG_ROSC_CLK:
  494. return scg_src_get_rate(clk);
  495. default:
  496. return 0;
  497. }
  498. }
  499. int scg_enable_pll_pfd(enum scg_clk clk, u32 frac)
  500. {
  501. u32 reg;
  502. u32 shift, mask, gate, valid;
  503. u32 addr;
  504. if (frac < 12 || frac > 35)
  505. return -EINVAL;
  506. switch (clk) {
  507. case SCG_SPLL_PFD0_CLK:
  508. case SCG_APLL_PFD0_CLK:
  509. gate = SCG_PLL_PFD0_GATE_MASK;
  510. valid = SCG_PLL_PFD0_VALID_MASK;
  511. mask = SCG_PLL_PFD0_FRAC_MASK;
  512. shift = SCG_PLL_PFD0_FRAC_SHIFT;
  513. if (clk == SCG_SPLL_PFD0_CLK)
  514. addr = (u32)(&scg1_regs->spllpfd);
  515. else
  516. addr = (u32)(&scg1_regs->apllpfd);
  517. break;
  518. case SCG_SPLL_PFD1_CLK:
  519. case SCG_APLL_PFD1_CLK:
  520. gate = SCG_PLL_PFD1_GATE_MASK;
  521. valid = SCG_PLL_PFD1_VALID_MASK;
  522. mask = SCG_PLL_PFD1_FRAC_MASK;
  523. shift = SCG_PLL_PFD1_FRAC_SHIFT;
  524. if (clk == SCG_SPLL_PFD1_CLK)
  525. addr = (u32)(&scg1_regs->spllpfd);
  526. else
  527. addr = (u32)(&scg1_regs->apllpfd);
  528. break;
  529. case SCG_SPLL_PFD2_CLK:
  530. case SCG_APLL_PFD2_CLK:
  531. gate = SCG_PLL_PFD2_GATE_MASK;
  532. valid = SCG_PLL_PFD2_VALID_MASK;
  533. mask = SCG_PLL_PFD2_FRAC_MASK;
  534. shift = SCG_PLL_PFD2_FRAC_SHIFT;
  535. if (clk == SCG_SPLL_PFD2_CLK)
  536. addr = (u32)(&scg1_regs->spllpfd);
  537. else
  538. addr = (u32)(&scg1_regs->apllpfd);
  539. break;
  540. case SCG_SPLL_PFD3_CLK:
  541. case SCG_APLL_PFD3_CLK:
  542. gate = SCG_PLL_PFD3_GATE_MASK;
  543. valid = SCG_PLL_PFD3_VALID_MASK;
  544. mask = SCG_PLL_PFD3_FRAC_MASK;
  545. shift = SCG_PLL_PFD3_FRAC_SHIFT;
  546. if (clk == SCG_SPLL_PFD3_CLK)
  547. addr = (u32)(&scg1_regs->spllpfd);
  548. else
  549. addr = (u32)(&scg1_regs->apllpfd);
  550. break;
  551. default:
  552. return -EINVAL;
  553. }
  554. /* Gate the PFD */
  555. reg = readl(addr);
  556. reg |= gate;
  557. writel(reg, addr);
  558. /* Write Frac divider */
  559. reg &= ~mask;
  560. reg |= (frac << shift) & mask;
  561. writel(reg, addr);
  562. /*
  563. * Un-gate the PFD
  564. * (Need un-gate before checking valid, not align with RM)
  565. */
  566. reg &= ~gate;
  567. writel(reg, addr);
  568. /* Wait for PFD clock being valid */
  569. do {
  570. reg = readl(addr);
  571. } while (!(reg & valid));
  572. return 0;
  573. }
  574. #define SIM_MISC_CTRL0_USB_PLL_EN_MASK (0x1 << 2)
  575. int scg_enable_usb_pll(bool usb_control)
  576. {
  577. u32 sosc_rate;
  578. s32 timeout = 1000000;
  579. u32 reg;
  580. struct usbphy_regs *usbphy =
  581. (struct usbphy_regs *)USBPHY_RBASE;
  582. sosc_rate = scg_src_get_rate(SCG_SOSC_CLK);
  583. if (!sosc_rate)
  584. return -EPERM;
  585. reg = readl(SIM0_RBASE + 0x3C);
  586. if (usb_control)
  587. reg &= ~SIM_MISC_CTRL0_USB_PLL_EN_MASK;
  588. else
  589. reg |= SIM_MISC_CTRL0_USB_PLL_EN_MASK;
  590. writel(reg, SIM0_RBASE + 0x3C);
  591. if (!(readl(&usbphy->usb1_pll_480_ctrl) & PLL_USB_LOCK_MASK)) {
  592. writel(0x1c00000, &usbphy->usb1_pll_480_ctrl_clr);
  593. switch (sosc_rate) {
  594. case 24000000:
  595. writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set);
  596. break;
  597. case 30000000:
  598. writel(0x800000, &usbphy->usb1_pll_480_ctrl_set);
  599. break;
  600. case 19200000:
  601. writel(0x1400000, &usbphy->usb1_pll_480_ctrl_set);
  602. break;
  603. default:
  604. writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set);
  605. break;
  606. }
  607. /* Enable the regulator first */
  608. writel(PLL_USB_REG_ENABLE_MASK,
  609. &usbphy->usb1_pll_480_ctrl_set);
  610. /* Wait at least 15us */
  611. udelay(15);
  612. /* Enable the power */
  613. writel(PLL_USB_PWR_MASK, &usbphy->usb1_pll_480_ctrl_set);
  614. /* Wait lock */
  615. while (timeout--) {
  616. if (readl(&usbphy->usb1_pll_480_ctrl) &
  617. PLL_USB_LOCK_MASK)
  618. break;
  619. }
  620. if (timeout <= 0) {
  621. /* If timeout, we power down the pll */
  622. writel(PLL_USB_PWR_MASK,
  623. &usbphy->usb1_pll_480_ctrl_clr);
  624. return -ETIME;
  625. }
  626. }
  627. /* Clear the bypass */
  628. writel(PLL_USB_BYPASS_MASK, &usbphy->usb1_pll_480_ctrl_clr);
  629. /* Enable the PLL clock out to USB */
  630. writel((PLL_USB_EN_USB_CLKS_MASK | PLL_USB_ENABLE_MASK),
  631. &usbphy->usb1_pll_480_ctrl_set);
  632. if (!usb_control) {
  633. while (timeout--) {
  634. if (readl(&scg1_regs->upllcsr) &
  635. SCG_UPLL_CSR_UPLLVLD_MASK)
  636. break;
  637. }
  638. if (timeout <= 0) {
  639. reg = readl(SIM0_RBASE + 0x3C);
  640. reg &= ~SIM_MISC_CTRL0_USB_PLL_EN_MASK;
  641. writel(reg, SIM0_RBASE + 0x3C);
  642. return -ETIME;
  643. }
  644. }
  645. return 0;
  646. }
  647. /* A7 domain system clock source is SPLL */
  648. #define SCG1_RCCR_SCS_NUM ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT)
  649. /* A7 Core clck = SPLL PFD0 / 1 = 500MHz / 1 = 500MHz */
  650. #define SCG1_RCCR_DIVCORE_NUM ((0x0) << SCG_CCR_DIVCORE_SHIFT)
  651. #define SCG1_RCCR_CFG_MASK (SCG_CCR_SCS_MASK | SCG_CCR_DIVBUS_MASK)
  652. /* A7 Plat clck = A7 Core Clock / 2 = 250MHz / 1 = 250MHz */
  653. #define SCG1_RCCR_DIVBUS_NUM ((0x1) << SCG_CCR_DIVBUS_SHIFT)
  654. #define SCG1_RCCR_CFG_NUM (SCG1_RCCR_SCS_NUM | SCG1_RCCR_DIVBUS_NUM)
  655. void scg_a7_rccr_init(void)
  656. {
  657. u32 rccr_reg_val = 0;
  658. rccr_reg_val = readl(&scg1_regs->rccr);
  659. rccr_reg_val &= (~SCG1_RCCR_CFG_MASK);
  660. rccr_reg_val |= (SCG1_RCCR_CFG_NUM);
  661. writel(rccr_reg_val, &scg1_regs->rccr);
  662. }
  663. /* POSTDIV2 = 1 */
  664. #define SCG1_SPLL_CFG_POSTDIV2_NUM ((0x0) << SCG_PLL_CFG_POSTDIV2_SHIFT)
  665. /* POSTDIV1 = 1 */
  666. #define SCG1_SPLL_CFG_POSTDIV1_NUM ((0x0) << SCG_PLL_CFG_POSTDIV1_SHIFT)
  667. /* MULT = 22 */
  668. #define SCG1_SPLL_CFG_MULT_NUM ((22) << SCG_PLL_CFG_MULT_SHIFT)
  669. /* PFD0 output clock selected */
  670. #define SCG1_SPLL_CFG_PFDSEL_NUM ((0) << SCG_PLL_CFG_PFDSEL_SHIFT)
  671. /* PREDIV = 1 */
  672. #define SCG1_SPLL_CFG_PREDIV_NUM ((0x0) << SCG_PLL_CFG_PREDIV_SHIFT)
  673. /* SPLL output clocks (including PFD outputs) selected */
  674. #define SCG1_SPLL_CFG_BYPASS_NUM ((0x0) << SCG_PLL_CFG_BYPASS_SHIFT)
  675. /* SPLL PFD output clock selected */
  676. #define SCG1_SPLL_CFG_PLLSEL_NUM ((0x1) << SCG_PLL_CFG_PLLSEL_SHIFT)
  677. /* Clock source is System OSC */
  678. #define SCG1_SPLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT)
  679. #define SCG1_SPLL_CFG_NUM_24M_OSC (SCG1_SPLL_CFG_POSTDIV2_NUM | \
  680. SCG1_SPLL_CFG_POSTDIV1_NUM | \
  681. (22 << SCG_PLL_CFG_MULT_SHIFT) | \
  682. SCG1_SPLL_CFG_PFDSEL_NUM | \
  683. SCG1_SPLL_CFG_PREDIV_NUM | \
  684. SCG1_SPLL_CFG_BYPASS_NUM | \
  685. SCG1_SPLL_CFG_PLLSEL_NUM | \
  686. SCG1_SPLL_CFG_CLKSRC_NUM)
  687. /*413Mhz = A7 SPLL(528MHz) * 18/23 */
  688. #define SCG1_SPLL_PFD0_FRAC_NUM ((23) << SCG_PLL_PFD0_FRAC_SHIFT)
  689. void scg_a7_spll_init(void)
  690. {
  691. u32 val = 0;
  692. /* Disable A7 System PLL */
  693. val = readl(&scg1_regs->spllcsr);
  694. val &= ~SCG_SPLL_CSR_SPLLEN_MASK;
  695. writel(val, &scg1_regs->spllcsr);
  696. /*
  697. * Per block guide,
  698. * "When changing PFD values, it is recommneded PFDx clock
  699. * gets gated first by writing a value of 1 to PFDx_CLKGATE register,
  700. * then program the new PFD value, then poll the PFDx_VALID
  701. * flag to set before writing a value of 0 to PFDx_CLKGATE
  702. * to ungate the PFDx clock and allow PFDx clock to run"
  703. */
  704. /* Gate off A7 SPLL PFD0 ~ PDF4 */
  705. val = readl(&scg1_regs->spllpfd);
  706. val |= (SCG_PLL_PFD3_GATE_MASK |
  707. SCG_PLL_PFD2_GATE_MASK |
  708. SCG_PLL_PFD1_GATE_MASK |
  709. SCG_PLL_PFD0_GATE_MASK);
  710. writel(val, &scg1_regs->spllpfd);
  711. /* ================ A7 SPLL Configuration Start ============== */
  712. /* Configure A7 System PLL */
  713. writel(SCG1_SPLL_CFG_NUM_24M_OSC, &scg1_regs->spllcfg);
  714. /* Enable A7 System PLL */
  715. val = readl(&scg1_regs->spllcsr);
  716. val |= SCG_SPLL_CSR_SPLLEN_MASK;
  717. writel(val, &scg1_regs->spllcsr);
  718. /* Wait for A7 SPLL clock ready */
  719. while (!(readl(&scg1_regs->spllcsr) & SCG_SPLL_CSR_SPLLVLD_MASK))
  720. ;
  721. /* Configure A7 SPLL PFD0 */
  722. val = readl(&scg1_regs->spllpfd);
  723. val &= ~SCG_PLL_PFD0_FRAC_MASK;
  724. val |= SCG1_SPLL_PFD0_FRAC_NUM;
  725. writel(val, &scg1_regs->spllpfd);
  726. /* Un-gate A7 SPLL PFD0 */
  727. val = readl(&scg1_regs->spllpfd);
  728. val &= ~SCG_PLL_PFD0_GATE_MASK;
  729. writel(val, &scg1_regs->spllpfd);
  730. /* Wait for A7 SPLL PFD0 clock being valid */
  731. while (!(readl(&scg1_regs->spllpfd) & SCG_PLL_PFD0_VALID_MASK))
  732. ;
  733. /* ================ A7 SPLL Configuration End ============== */
  734. }
  735. /* DDR clock source is APLL PFD0 (396MHz) */
  736. #define SCG1_DDRCCR_DDRCS_NUM ((0x0) << SCG_DDRCCR_DDRCS_SHIFT)
  737. /* DDR clock = APLL PFD0 / 1 = 396MHz / 1 = 396MHz */
  738. #define SCG1_DDRCCR_DDRDIV_NUM ((0x1) << SCG_DDRCCR_DDRDIV_SHIFT)
  739. /* DDR clock = APLL PFD0 / 2 = 396MHz / 2 = 198MHz */
  740. #define SCG1_DDRCCR_DDRDIV_LF_NUM ((0x2) << SCG_DDRCCR_DDRDIV_SHIFT)
  741. #define SCG1_DDRCCR_CFG_NUM (SCG1_DDRCCR_DDRCS_NUM | \
  742. SCG1_DDRCCR_DDRDIV_NUM)
  743. #define SCG1_DDRCCR_CFG_LF_NUM (SCG1_DDRCCR_DDRCS_NUM | \
  744. SCG1_DDRCCR_DDRDIV_LF_NUM)
  745. void scg_a7_ddrclk_init(void)
  746. {
  747. writel(SCG1_DDRCCR_CFG_NUM, &scg1_regs->ddrccr);
  748. }
  749. /* SCG1(A7) APLLCFG configurations */
  750. /* divide by 1 <<28 */
  751. #define SCG1_APLL_CFG_POSTDIV2_NUM ((0x0) << SCG_PLL_CFG_POSTDIV2_SHIFT)
  752. /* divide by 1 <<24 */
  753. #define SCG1_APLL_CFG_POSTDIV1_NUM ((0x0) << SCG_PLL_CFG_POSTDIV1_SHIFT)
  754. /* MULT is 22 <<16 */
  755. #define SCG1_APLL_CFG_MULT_NUM ((22) << SCG_PLL_CFG_MULT_SHIFT)
  756. /* PFD0 output clock selected <<14 */
  757. #define SCG1_APLL_CFG_PFDSEL_NUM ((0) << SCG_PLL_CFG_PFDSEL_SHIFT)
  758. /* PREDIV = 1 <<8 */
  759. #define SCG1_APLL_CFG_PREDIV_NUM ((0x0) << SCG_PLL_CFG_PREDIV_SHIFT)
  760. /* APLL output clocks (including PFD outputs) selected <<2 */
  761. #define SCG1_APLL_CFG_BYPASS_NUM ((0x0) << SCG_PLL_CFG_BYPASS_SHIFT)
  762. /* APLL PFD output clock selected <<1 */
  763. #define SCG1_APLL_CFG_PLLSEL_NUM ((0x0) << SCG_PLL_CFG_PLLSEL_SHIFT)
  764. /* Clock source is System OSC <<0 */
  765. #define SCG1_APLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT)
  766. /*
  767. * A7 APLL = 24MHz / 1 * 22 / 1 / 1 = 528MHz,
  768. * system PLL is sourced from APLL,
  769. * APLL clock source is system OSC (24MHz)
  770. */
  771. #define SCG1_APLL_CFG_NUM_24M_OSC (SCG1_APLL_CFG_POSTDIV2_NUM | \
  772. SCG1_APLL_CFG_POSTDIV1_NUM | \
  773. (22 << SCG_PLL_CFG_MULT_SHIFT) | \
  774. SCG1_APLL_CFG_PFDSEL_NUM | \
  775. SCG1_APLL_CFG_PREDIV_NUM | \
  776. SCG1_APLL_CFG_BYPASS_NUM | \
  777. SCG1_APLL_CFG_PLLSEL_NUM | \
  778. SCG1_APLL_CFG_CLKSRC_NUM)
  779. /* PFD0 Freq = A7 APLL(528MHz) * 18 / 27 = 352MHz */
  780. #define SCG1_APLL_PFD0_FRAC_NUM (27)
  781. void scg_a7_apll_init(void)
  782. {
  783. u32 val = 0;
  784. /* Disable A7 Auxiliary PLL */
  785. val = readl(&scg1_regs->apllcsr);
  786. val &= ~SCG_APLL_CSR_APLLEN_MASK;
  787. writel(val, &scg1_regs->apllcsr);
  788. /* Gate off A7 APLL PFD0 ~ PDF4 */
  789. val = readl(&scg1_regs->apllpfd);
  790. val |= 0x80808080;
  791. writel(val, &scg1_regs->apllpfd);
  792. /* ================ A7 APLL Configuration Start ============== */
  793. /* Configure A7 Auxiliary PLL */
  794. writel(SCG1_APLL_CFG_NUM_24M_OSC, &scg1_regs->apllcfg);
  795. /* Enable A7 Auxiliary PLL */
  796. val = readl(&scg1_regs->apllcsr);
  797. val |= SCG_APLL_CSR_APLLEN_MASK;
  798. writel(val, &scg1_regs->apllcsr);
  799. /* Wait for A7 APLL clock ready */
  800. while (!(readl(&scg1_regs->apllcsr) & SCG_APLL_CSR_APLLVLD_MASK))
  801. ;
  802. /* Configure A7 APLL PFD0 */
  803. val = readl(&scg1_regs->apllpfd);
  804. val &= ~SCG_PLL_PFD0_FRAC_MASK;
  805. val |= SCG1_APLL_PFD0_FRAC_NUM;
  806. writel(val, &scg1_regs->apllpfd);
  807. /* Un-gate A7 APLL PFD0 */
  808. val = readl(&scg1_regs->apllpfd);
  809. val &= ~SCG_PLL_PFD0_GATE_MASK;
  810. writel(val, &scg1_regs->apllpfd);
  811. /* Wait for A7 APLL PFD0 clock being valid */
  812. while (!(readl(&scg1_regs->apllpfd) & SCG_PLL_PFD0_VALID_MASK))
  813. ;
  814. }
  815. /* SCG1(A7) FIRC DIV configurations */
  816. /* Disable FIRC DIV3 */
  817. #define SCG1_FIRCDIV_DIV3_NUM ((0x0) << SCG_FIRCDIV_DIV3_SHIFT)
  818. /* FIRC DIV2 = 48MHz / 1 = 48MHz */
  819. #define SCG1_FIRCDIV_DIV2_NUM ((0x1) << SCG_FIRCDIV_DIV2_SHIFT)
  820. /* Disable FIRC DIV1 */
  821. #define SCG1_FIRCDIV_DIV1_NUM ((0x0) << SCG_FIRCDIV_DIV1_SHIFT)
  822. void scg_a7_firc_init(void)
  823. {
  824. /* Wait for FIRC clock ready */
  825. while (!(readl(&scg1_regs->firccsr) & SCG_FIRC_CSR_FIRCVLD_MASK))
  826. ;
  827. /* Configure A7 FIRC DIV1 ~ DIV3 */
  828. writel((SCG1_FIRCDIV_DIV3_NUM |
  829. SCG1_FIRCDIV_DIV2_NUM |
  830. SCG1_FIRCDIV_DIV1_NUM), &scg1_regs->fircdiv);
  831. }
  832. /* SCG1(A7) NICCCR configurations */
  833. /* NIC clock source is DDR clock (396/198MHz) */
  834. #define SCG1_NICCCR_NICCS_NUM ((0x1) << SCG_NICCCR_NICCS_SHIFT)
  835. /* NIC0 clock = DDR Clock / 2 = 396MHz / 2 = 198MHz */
  836. #define SCG1_NICCCR_NIC0_DIV_NUM ((0x1) << SCG_NICCCR_NIC0_DIV_SHIFT)
  837. /* NIC0 clock = DDR Clock / 1 = 198MHz / 1 = 198MHz */
  838. #define SCG1_NICCCR_NIC0_DIV_LF_NUM ((0x0) << SCG_NICCCR_NIC0_DIV_SHIFT)
  839. /* NIC1 clock = NIC0 Clock / 1 = 198MHz / 2 = 198MHz */
  840. #define SCG1_NICCCR_NIC1_DIV_NUM ((0x0) << SCG_NICCCR_NIC1_DIV_SHIFT)
  841. /* NIC1 bus clock = NIC1 Clock / 3 = 198MHz / 3 = 66MHz */
  842. #define SCG1_NICCCR_NIC1_DIVBUS_NUM ((0x2) << SCG_NICCCR_NIC1_DIVBUS_SHIFT)
  843. #define SCG1_NICCCR_CFG_NUM (SCG1_NICCCR_NICCS_NUM | \
  844. SCG1_NICCCR_NIC0_DIV_NUM | \
  845. SCG1_NICCCR_NIC1_DIV_NUM | \
  846. SCG1_NICCCR_NIC1_DIVBUS_NUM)
  847. void scg_a7_nicclk_init(void)
  848. {
  849. writel(SCG1_NICCCR_CFG_NUM, &scg1_regs->nicccr);
  850. }
  851. /* SCG1(A7) FIRC DIV configurations */
  852. /* Enable FIRC DIV3 */
  853. #define SCG1_SOSCDIV_DIV3_NUM ((0x1) << SCG_SOSCDIV_DIV3_SHIFT)
  854. /* FIRC DIV2 = 48MHz / 1 = 48MHz */
  855. #define SCG1_SOSCDIV_DIV2_NUM ((0x1) << SCG_SOSCDIV_DIV2_SHIFT)
  856. /* Enable FIRC DIV1 */
  857. #define SCG1_SOSCDIV_DIV1_NUM ((0x1) << SCG_SOSCDIV_DIV1_SHIFT)
  858. void scg_a7_soscdiv_init(void)
  859. {
  860. /* Wait for FIRC clock ready */
  861. while (!(readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK))
  862. ;
  863. /* Configure A7 FIRC DIV1 ~ DIV3 */
  864. writel((SCG1_SOSCDIV_DIV3_NUM | SCG1_SOSCDIV_DIV2_NUM |
  865. SCG1_SOSCDIV_DIV1_NUM), &scg1_regs->soscdiv);
  866. }
  867. void scg_a7_sys_clk_sel(enum scg_sys_src clk)
  868. {
  869. u32 rccr_reg_val = 0;
  870. clk_debug("%s: system clock selected as %s\n", "[SCG]",
  871. clk == SCG_SCS_SYS_OSC ? "SYS_OSC" :
  872. clk == SCG_SCS_SLOW_IRC ? "SLOW_IRC" :
  873. clk == SCG_SCS_FAST_IRC ? "FAST_IRC" :
  874. clk == SCG_SCS_RTC_OSC ? "RTC_OSC" :
  875. clk == SCG_SCS_AUX_PLL ? "AUX_PLL" :
  876. clk == SCG_SCS_SYS_PLL ? "SYS_PLL" :
  877. clk == SCG_SCS_USBPHY_PLL ? "USBPHY_PLL" :
  878. "Invalid source"
  879. );
  880. rccr_reg_val = readl(&scg1_regs->rccr);
  881. rccr_reg_val &= ~SCG_CCR_SCS_MASK;
  882. rccr_reg_val |= (clk << SCG_CCR_SCS_SHIFT);
  883. writel(rccr_reg_val, &scg1_regs->rccr);
  884. }
  885. void scg_a7_info(void)
  886. {
  887. debug("SCG Version: 0x%x\n", readl(&scg1_regs->verid));
  888. debug("SCG Parameter: 0x%x\n", readl(&scg1_regs->param));
  889. debug("SCG RCCR Value: 0x%x\n", readl(&scg1_regs->rccr));
  890. debug("SCG Clock Status: 0x%x\n", readl(&scg1_regs->csr));
  891. }
  892. void scg_a7_init_core_clk(void)
  893. {
  894. u32 val = 0;
  895. /*
  896. * The normal target frequency for ULP B0 is 500Mhz,
  897. * but ROM set it to 413Mhz, need to change SPLL PFD0 FRAC
  898. */
  899. if (soc_rev() >= CHIP_REV_2_0) {
  900. /* Switch RCCR SCG to SOSC, firstly check the SOSC is valid */
  901. if ((readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK)) {
  902. val = readl(&scg1_regs->rccr);
  903. val &= (~SCG_CCR_SCS_MASK);
  904. val |= ((SCG_SCS_SYS_OSC) << SCG_CCR_SCS_SHIFT);
  905. writel(val, &scg1_regs->rccr);
  906. /* Switch the PLLS to SPLL clk */
  907. val = readl(&scg1_regs->spllcfg);
  908. val &= ~SCG_PLL_CFG_PLLSEL_MASK;
  909. writel(val, &scg1_regs->spllcfg);
  910. /*
  911. * Re-configure PFD0 to 19,
  912. * A7 SPLL(528MHz) * 18 / 19 = 500MHz
  913. */
  914. scg_enable_pll_pfd(SCG_SPLL_PFD0_CLK, 19);
  915. /* Switch the PLLS to SPLL PFD0 */
  916. val = readl(&scg1_regs->spllcfg);
  917. val |= SCG_PLL_CFG_PLLSEL_MASK;
  918. writel(val, &scg1_regs->spllcfg);
  919. /* Set RCCR SCG to SPLL clk out */
  920. val = readl(&scg1_regs->rccr);
  921. val &= (~SCG_CCR_SCS_MASK);
  922. val |= ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT);
  923. writel(val, &scg1_regs->rccr);
  924. }
  925. }
  926. }