clock.c 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <div64.h>
  7. #include <asm/io.h>
  8. #include <errno.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/sys_proto.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. int get_clocks(void)
  13. {
  14. #ifdef CONFIG_FSL_ESDHC_IMX
  15. #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
  16. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  17. #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
  18. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  19. #endif
  20. #endif
  21. return 0;
  22. }
  23. static u32 get_fast_plat_clk(void)
  24. {
  25. return scg_clk_get_rate(SCG_NIC0_CLK);
  26. }
  27. static u32 get_slow_plat_clk(void)
  28. {
  29. return scg_clk_get_rate(SCG_NIC1_CLK);
  30. }
  31. static u32 get_ipg_clk(void)
  32. {
  33. return scg_clk_get_rate(SCG_NIC1_BUS_CLK);
  34. }
  35. u32 get_lpuart_clk(void)
  36. {
  37. int index = 0;
  38. const u32 lpuart_array[] = {
  39. LPUART0_RBASE,
  40. LPUART1_RBASE,
  41. LPUART2_RBASE,
  42. LPUART3_RBASE,
  43. LPUART4_RBASE,
  44. LPUART5_RBASE,
  45. LPUART6_RBASE,
  46. LPUART7_RBASE,
  47. };
  48. const enum pcc_clk lpuart_pcc_clks[] = {
  49. PER_CLK_LPUART4,
  50. PER_CLK_LPUART5,
  51. PER_CLK_LPUART6,
  52. PER_CLK_LPUART7,
  53. };
  54. for (index = 0; index < 8; index++) {
  55. if (lpuart_array[index] == LPUART_BASE)
  56. break;
  57. }
  58. if (index < 4 || index > 7)
  59. return 0;
  60. return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]);
  61. }
  62. #ifdef CONFIG_SYS_I2C_IMX_LPI2C
  63. int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
  64. {
  65. /* Set parent to FIRC DIV2 clock */
  66. const enum pcc_clk lpi2c_pcc_clks[] = {
  67. PER_CLK_LPI2C4,
  68. PER_CLK_LPI2C5,
  69. PER_CLK_LPI2C6,
  70. PER_CLK_LPI2C7,
  71. };
  72. if (i2c_num < 4 || i2c_num > 7)
  73. return -EINVAL;
  74. if (enable) {
  75. pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
  76. pcc_clock_sel(lpi2c_pcc_clks[i2c_num - 4], SCG_FIRC_DIV2_CLK);
  77. pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], true);
  78. } else {
  79. pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
  80. }
  81. return 0;
  82. }
  83. u32 imx_get_i2cclk(unsigned i2c_num)
  84. {
  85. const enum pcc_clk lpi2c_pcc_clks[] = {
  86. PER_CLK_LPI2C4,
  87. PER_CLK_LPI2C5,
  88. PER_CLK_LPI2C6,
  89. PER_CLK_LPI2C7,
  90. };
  91. if (i2c_num < 4 || i2c_num > 7)
  92. return 0;
  93. return pcc_clock_get_rate(lpi2c_pcc_clks[i2c_num - 4]);
  94. }
  95. #endif
  96. unsigned int mxc_get_clock(enum mxc_clock clk)
  97. {
  98. switch (clk) {
  99. case MXC_ARM_CLK:
  100. return scg_clk_get_rate(SCG_CORE_CLK);
  101. case MXC_AXI_CLK:
  102. return get_fast_plat_clk();
  103. case MXC_AHB_CLK:
  104. return get_slow_plat_clk();
  105. case MXC_IPG_CLK:
  106. return get_ipg_clk();
  107. case MXC_I2C_CLK:
  108. return pcc_clock_get_rate(PER_CLK_LPI2C4);
  109. case MXC_UART_CLK:
  110. return get_lpuart_clk();
  111. case MXC_ESDHC_CLK:
  112. return pcc_clock_get_rate(PER_CLK_USDHC0);
  113. case MXC_ESDHC2_CLK:
  114. return pcc_clock_get_rate(PER_CLK_USDHC1);
  115. case MXC_DDR_CLK:
  116. return scg_clk_get_rate(SCG_DDR_CLK);
  117. default:
  118. printf("Unsupported mxc_clock %d\n", clk);
  119. break;
  120. }
  121. return 0;
  122. }
  123. void init_clk_usdhc(u32 index)
  124. {
  125. switch (index) {
  126. case 0:
  127. /*Disable the clock before configure it */
  128. pcc_clock_enable(PER_CLK_USDHC0, false);
  129. /* 158MHz / 1 = 158MHz */
  130. pcc_clock_sel(PER_CLK_USDHC0, SCG_NIC1_CLK);
  131. pcc_clock_div_config(PER_CLK_USDHC0, false, 1);
  132. pcc_clock_enable(PER_CLK_USDHC0, true);
  133. break;
  134. case 1:
  135. /*Disable the clock before configure it */
  136. pcc_clock_enable(PER_CLK_USDHC1, false);
  137. /* 158MHz / 1 = 158MHz */
  138. pcc_clock_sel(PER_CLK_USDHC1, SCG_NIC1_CLK);
  139. pcc_clock_div_config(PER_CLK_USDHC1, false, 1);
  140. pcc_clock_enable(PER_CLK_USDHC1, true);
  141. break;
  142. default:
  143. printf("Invalid index for USDHC %d\n", index);
  144. break;
  145. }
  146. }
  147. #ifdef CONFIG_MXC_OCOTP
  148. #define OCOTP_CTRL_PCC1_SLOT (38)
  149. #define OCOTP_CTRL_HIGH4K_PCC1_SLOT (39)
  150. void enable_ocotp_clk(unsigned char enable)
  151. {
  152. u32 val;
  153. /*
  154. * Seems the OCOTP CLOCKs have been enabled at default,
  155. * check its inuse flag
  156. */
  157. val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT);
  158. if (!(val & PCC_INUSE_MASK))
  159. writel(PCC_CGC_MASK, (PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT));
  160. val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT);
  161. if (!(val & PCC_INUSE_MASK))
  162. writel(PCC_CGC_MASK,
  163. (PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT));
  164. }
  165. #endif
  166. void enable_usboh3_clk(unsigned char enable)
  167. {
  168. if (enable) {
  169. pcc_clock_enable(PER_CLK_USB0, false);
  170. pcc_clock_sel(PER_CLK_USB0, SCG_NIC1_BUS_CLK);
  171. pcc_clock_enable(PER_CLK_USB0, true);
  172. #ifdef CONFIG_USB_MAX_CONTROLLER_COUNT
  173. if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) {
  174. pcc_clock_enable(PER_CLK_USB1, false);
  175. pcc_clock_sel(PER_CLK_USB1, SCG_NIC1_BUS_CLK);
  176. pcc_clock_enable(PER_CLK_USB1, true);
  177. }
  178. #endif
  179. pcc_clock_enable(PER_CLK_USB_PHY, true);
  180. pcc_clock_enable(PER_CLK_USB_PL301, true);
  181. } else {
  182. pcc_clock_enable(PER_CLK_USB0, false);
  183. pcc_clock_enable(PER_CLK_USB1, false);
  184. pcc_clock_enable(PER_CLK_USB_PHY, false);
  185. pcc_clock_enable(PER_CLK_USB_PL301, false);
  186. }
  187. }
  188. static void lpuart_set_clk(uint32_t index, enum scg_clk clk)
  189. {
  190. const enum pcc_clk lpuart_pcc_clks[] = {
  191. PER_CLK_LPUART4,
  192. PER_CLK_LPUART5,
  193. PER_CLK_LPUART6,
  194. PER_CLK_LPUART7,
  195. };
  196. if (index < 4 || index > 7)
  197. return;
  198. #ifndef CONFIG_CLK_DEBUG
  199. pcc_clock_enable(lpuart_pcc_clks[index - 4], false);
  200. #endif
  201. pcc_clock_sel(lpuart_pcc_clks[index - 4], clk);
  202. pcc_clock_enable(lpuart_pcc_clks[index - 4], true);
  203. }
  204. static void init_clk_lpuart(void)
  205. {
  206. u32 index = 0, i;
  207. const u32 lpuart_array[] = {
  208. LPUART0_RBASE,
  209. LPUART1_RBASE,
  210. LPUART2_RBASE,
  211. LPUART3_RBASE,
  212. LPUART4_RBASE,
  213. LPUART5_RBASE,
  214. LPUART6_RBASE,
  215. LPUART7_RBASE,
  216. };
  217. for (i = 0; i < 8; i++) {
  218. if (lpuart_array[i] == LPUART_BASE) {
  219. index = i;
  220. break;
  221. }
  222. }
  223. lpuart_set_clk(index, SCG_SOSC_DIV2_CLK);
  224. }
  225. static void init_clk_rgpio2p(void)
  226. {
  227. /*Enable RGPIO2P1 clock */
  228. pcc_clock_enable(PER_CLK_RGPIO2P1, true);
  229. /*
  230. * Hard code to enable RGPIO2P0 clock since it is not
  231. * in clock frame for A7 domain
  232. */
  233. writel(PCC_CGC_MASK, (PCC0_RBASE + 0x3C));
  234. }
  235. /* Configure PLL/PFD freq */
  236. void clock_init(void)
  237. {
  238. /*
  239. * ROM has enabled clocks:
  240. * A4 side: SIRC 16Mhz (DIV1-3 off), FIRC 48Mhz (DIV1-2 on),
  241. * Non-LP-boot: SOSC, SPLL PFD0 (scs selected)
  242. * A7 side: SPLL PFD0 (scs selected, 413Mhz),
  243. * APLL PFD0 (352Mhz), DDRCLK, all NIC clocks
  244. * A7 Plat0 (NIC0) = 176Mhz, Plat1 (NIC1) = 176Mhz,
  245. * IP BUS (NIC1_BUS) = 58.6Mhz
  246. *
  247. * In u-boot:
  248. * 1. Enable PFD1-3 of APLL for A7 side. Enable FIRC and DIVs.
  249. * 2. Enable USB PLL
  250. * 3. Init the clocks of peripherals used in u-boot bu
  251. * without set rate interface.The clocks for these
  252. * peripherals are enabled in this intialization.
  253. * 4.Other peripherals with set clock rate interface
  254. * does not be set in this function.
  255. */
  256. scg_a7_firc_init();
  257. scg_a7_soscdiv_init();
  258. scg_a7_init_core_clk();
  259. /* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */
  260. scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35);
  261. scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28);
  262. scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12);
  263. init_clk_lpuart();
  264. init_clk_rgpio2p();
  265. enable_usboh3_clk(1);
  266. }
  267. #ifdef CONFIG_IMX_HAB
  268. void hab_caam_clock_enable(unsigned char enable)
  269. {
  270. if (enable)
  271. pcc_clock_enable(PER_CLK_CAAM, true);
  272. else
  273. pcc_clock_enable(PER_CLK_CAAM, false);
  274. }
  275. #endif
  276. #ifndef CONFIG_SPL_BUILD
  277. /*
  278. * Dump some core clockes.
  279. */
  280. int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  281. {
  282. u32 addr = 0;
  283. u32 freq;
  284. freq = decode_pll(PLL_A7_SPLL);
  285. printf("PLL_A7_SPLL %8d MHz\n", freq / 1000000);
  286. freq = decode_pll(PLL_A7_APLL);
  287. printf("PLL_A7_APLL %8d MHz\n", freq / 1000000);
  288. freq = decode_pll(PLL_USB);
  289. printf("PLL_USB %8d MHz\n", freq / 1000000);
  290. printf("\n");
  291. printf("CORE %8d kHz\n", scg_clk_get_rate(SCG_CORE_CLK) / 1000);
  292. printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
  293. printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
  294. printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
  295. printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
  296. printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
  297. printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
  298. printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
  299. printf("I2C4 %8d kHz\n", mxc_get_clock(MXC_I2C_CLK) / 1000);
  300. addr = (u32) clock_init;
  301. printf("[%s] addr = 0x%08X\r\n", __func__, addr);
  302. scg_a7_info();
  303. return 0;
  304. }
  305. U_BOOT_CMD(
  306. clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,
  307. "display clocks",
  308. ""
  309. );
  310. #endif