soc.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/io.h>
  7. #include <asm/arch/imx-regs.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <asm/mach-imx/dma.h>
  11. #include <asm/mach-imx/hab.h>
  12. #include <asm/mach-imx/rdc-sema.h>
  13. #include <asm/arch/imx-rdc.h>
  14. #include <asm/arch/crm_regs.h>
  15. #include <dm.h>
  16. #include <env.h>
  17. #include <imx_thermal.h>
  18. #include <fsl_sec.h>
  19. #include <asm/setup.h>
  20. #define IOMUXC_GPR1 0x4
  21. #define BM_IOMUXC_GPR1_IRQ 0x1000
  22. #define GPC_LPCR_A7_BSC 0x0
  23. #define GPC_LPCR_M4 0x8
  24. #define GPC_SLPCR 0x14
  25. #define GPC_PGC_ACK_SEL_A7 0x24
  26. #define GPC_IMR1_CORE0 0x30
  27. #define GPC_IMR1_CORE1 0x40
  28. #define GPC_IMR1_M4 0x50
  29. #define GPC_PGC_CPU_MAPPING 0xec
  30. #define GPC_PGC_C0_PUPSCR 0x804
  31. #define GPC_PGC_SCU_TIMING 0x890
  32. #define GPC_PGC_C1_PUPSCR 0x844
  33. #define BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP 0x70000000
  34. #define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000
  35. #define BM_LPCR_M4_MASK_DSM_TRIGGER 0x80000000
  36. #define BM_SLPCR_EN_DSM 0x80000000
  37. #define BM_SLPCR_RBC_EN 0x40000000
  38. #define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000
  39. #define BM_SLPCR_VSTBY 0x4
  40. #define BM_SLPCR_SBYOS 0x2
  41. #define BM_SLPCR_BYPASS_PMIC_READY 0x1
  42. #define BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE 0x10000
  43. #define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK 0x80000000
  44. #define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK 0x8000
  45. #define BM_GPC_PGC_CORE_PUPSCR 0x7fff80
  46. #if defined(CONFIG_IMX_THERMAL)
  47. static const struct imx_thermal_plat imx7_thermal_plat = {
  48. .regs = (void *)ANATOP_BASE_ADDR,
  49. .fuse_bank = 3,
  50. .fuse_word = 3,
  51. };
  52. U_BOOT_DEVICE(imx7_thermal) = {
  53. .name = "imx_thermal",
  54. .platdata = &imx7_thermal_plat,
  55. };
  56. #endif
  57. #if CONFIG_IS_ENABLED(IMX_RDC)
  58. /*
  59. * In current design, if any peripheral was assigned to both A7 and M4,
  60. * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
  61. * low power mode. So M4 sleep will cause some peripherals fail to work
  62. * at A7 core side. At default, all resources are in domain 0 - 3.
  63. *
  64. * There are 26 peripherals impacted by this IC issue:
  65. * SIM2(sim2/emvsim2)
  66. * SIM1(sim1/emvsim1)
  67. * UART1/UART2/UART3/UART4/UART5/UART6/UART7
  68. * SAI1/SAI2/SAI3
  69. * WDOG1/WDOG2/WDOG3/WDOG4
  70. * GPT1/GPT2/GPT3/GPT4
  71. * PWM1/PWM2/PWM3/PWM4
  72. * ENET1/ENET2
  73. * Software Workaround:
  74. * Here we setup some resources to domain 0 where M4 codes will move
  75. * the M4 out of this domain. Then M4 is not able to access them any longer.
  76. * This is a workaround for ic issue. So the peripherals are not shared
  77. * by them. This way requires the uboot implemented the RDC driver and
  78. * set the 26 IPs above to domain 0 only. M4 code will assign resource
  79. * to its own domain, if it want to use the resource.
  80. */
  81. static rdc_peri_cfg_t const resources[] = {
  82. (RDC_PER_SIM1 | RDC_DOMAIN(0)),
  83. (RDC_PER_SIM2 | RDC_DOMAIN(0)),
  84. (RDC_PER_UART1 | RDC_DOMAIN(0)),
  85. (RDC_PER_UART2 | RDC_DOMAIN(0)),
  86. (RDC_PER_UART3 | RDC_DOMAIN(0)),
  87. (RDC_PER_UART4 | RDC_DOMAIN(0)),
  88. (RDC_PER_UART5 | RDC_DOMAIN(0)),
  89. (RDC_PER_UART6 | RDC_DOMAIN(0)),
  90. (RDC_PER_UART7 | RDC_DOMAIN(0)),
  91. (RDC_PER_SAI1 | RDC_DOMAIN(0)),
  92. (RDC_PER_SAI2 | RDC_DOMAIN(0)),
  93. (RDC_PER_SAI3 | RDC_DOMAIN(0)),
  94. (RDC_PER_WDOG1 | RDC_DOMAIN(0)),
  95. (RDC_PER_WDOG2 | RDC_DOMAIN(0)),
  96. (RDC_PER_WDOG3 | RDC_DOMAIN(0)),
  97. (RDC_PER_WDOG4 | RDC_DOMAIN(0)),
  98. (RDC_PER_GPT1 | RDC_DOMAIN(0)),
  99. (RDC_PER_GPT2 | RDC_DOMAIN(0)),
  100. (RDC_PER_GPT3 | RDC_DOMAIN(0)),
  101. (RDC_PER_GPT4 | RDC_DOMAIN(0)),
  102. (RDC_PER_PWM1 | RDC_DOMAIN(0)),
  103. (RDC_PER_PWM2 | RDC_DOMAIN(0)),
  104. (RDC_PER_PWM3 | RDC_DOMAIN(0)),
  105. (RDC_PER_PWM4 | RDC_DOMAIN(0)),
  106. (RDC_PER_ENET1 | RDC_DOMAIN(0)),
  107. (RDC_PER_ENET2 | RDC_DOMAIN(0)),
  108. };
  109. static void isolate_resource(void)
  110. {
  111. imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
  112. }
  113. #endif
  114. #if defined(CONFIG_IMX_HAB)
  115. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  116. .bank = 1,
  117. .word = 3,
  118. };
  119. #endif
  120. static bool is_mx7d(void)
  121. {
  122. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  123. struct fuse_bank *bank = &ocotp->bank[1];
  124. struct fuse_bank1_regs *fuse =
  125. (struct fuse_bank1_regs *)bank->fuse_regs;
  126. int val;
  127. val = readl(&fuse->tester4);
  128. if (val & 1)
  129. return false;
  130. else
  131. return true;
  132. }
  133. u32 get_cpu_rev(void)
  134. {
  135. struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
  136. ANATOP_BASE_ADDR;
  137. u32 reg = readl(&ccm_anatop->digprog);
  138. u32 type = (reg >> 16) & 0xff;
  139. if (!is_mx7d())
  140. type = MXC_CPU_MX7S;
  141. reg &= 0xff;
  142. return (type << 12) | reg;
  143. }
  144. #ifdef CONFIG_REVISION_TAG
  145. u32 __weak get_board_rev(void)
  146. {
  147. return get_cpu_rev();
  148. }
  149. #endif
  150. static void imx_enet_mdio_fixup(void)
  151. {
  152. struct iomuxc_gpr_base_regs *gpr_regs =
  153. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  154. /*
  155. * The management data input/output (MDIO) requires open-drain,
  156. * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
  157. * this feature. So to TO1.1, need to enable open drain by setting
  158. * bits GPR0[8:7].
  159. */
  160. if (soc_rev() >= CHIP_REV_1_1) {
  161. setbits_le32(&gpr_regs->gpr[0],
  162. IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
  163. }
  164. }
  165. static void init_cpu_basic(void)
  166. {
  167. imx_enet_mdio_fixup();
  168. #ifdef CONFIG_APBH_DMA
  169. /* Start APBH DMA */
  170. mxs_dma_init();
  171. #endif
  172. }
  173. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  174. /* enable all periherial can be accessed in nosec mode */
  175. static void init_csu(void)
  176. {
  177. int i = 0;
  178. for (i = 0; i < CSU_NUM_REGS; i++)
  179. writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
  180. }
  181. static void imx_gpcv2_init(void)
  182. {
  183. u32 val, i;
  184. /*
  185. * Force IOMUXC irq pending, so that the interrupt to GPC can be
  186. * used to deassert dsm_request signal when the signal gets
  187. * asserted unexpectedly.
  188. */
  189. val = readl(IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
  190. val |= BM_IOMUXC_GPR1_IRQ;
  191. writel(val, IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
  192. /* Initially mask all interrupts */
  193. for (i = 0; i < 4; i++) {
  194. writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
  195. writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE1 + i * 4);
  196. writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_M4 + i * 4);
  197. }
  198. /* set SCU timing */
  199. writel((0x59 << 10) | 0x5B | (0x2 << 20),
  200. GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING);
  201. /* only external IRQs to wake up LPM and core 0/1 */
  202. val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
  203. val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP;
  204. writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
  205. /* set C0 power up timming per design requirement */
  206. val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
  207. val &= ~BM_GPC_PGC_CORE_PUPSCR;
  208. val |= (0x1A << 7);
  209. writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
  210. /* set C1 power up timming per design requirement */
  211. val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
  212. val &= ~BM_GPC_PGC_CORE_PUPSCR;
  213. val |= (0x1A << 7);
  214. writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
  215. /* dummy ack for time slot by default */
  216. writel(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK |
  217. BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK,
  218. GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);
  219. /* mask M4 DSM trigger */
  220. writel(readl(GPC_IPS_BASE_ADDR + GPC_LPCR_M4) |
  221. BM_LPCR_M4_MASK_DSM_TRIGGER,
  222. GPC_IPS_BASE_ADDR + GPC_LPCR_M4);
  223. /* set mega/fast mix in A7 domain */
  224. writel(0x1, GPC_IPS_BASE_ADDR + GPC_PGC_CPU_MAPPING);
  225. /* DSM related settings */
  226. val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
  227. val &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN |
  228. BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY |
  229. BM_SLPCR_REG_BYPASS_COUNT);
  230. val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE;
  231. writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
  232. /*
  233. * disabling RBC need to delay at least 2 cycles of CKIL(32K)
  234. * due to hardware design requirement, which is
  235. * ~61us, here we use 65us for safe
  236. */
  237. udelay(65);
  238. }
  239. int arch_cpu_init(void)
  240. {
  241. init_aips();
  242. init_csu();
  243. /* Disable PDE bit of WMCR register */
  244. imx_wdog_disable_powerdown();
  245. init_cpu_basic();
  246. #if CONFIG_IS_ENABLED(IMX_RDC)
  247. isolate_resource();
  248. #endif
  249. init_snvs();
  250. imx_gpcv2_init();
  251. return 0;
  252. }
  253. #else
  254. int arch_cpu_init(void)
  255. {
  256. init_cpu_basic();
  257. return 0;
  258. }
  259. #endif
  260. #ifdef CONFIG_ARCH_MISC_INIT
  261. int arch_misc_init(void)
  262. {
  263. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  264. if (is_mx7d())
  265. env_set("soc", "imx7d");
  266. else
  267. env_set("soc", "imx7s");
  268. #endif
  269. #ifdef CONFIG_FSL_CAAM
  270. sec_init();
  271. #endif
  272. return 0;
  273. }
  274. #endif
  275. #ifdef CONFIG_SERIAL_TAG
  276. /*
  277. * OCOTP_TESTER
  278. * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
  279. * OCOTP_TESTER describes a unique ID based on silicon wafer
  280. * and die X/Y position
  281. *
  282. * OCOTOP_TESTER offset 0x410
  283. * 31:0 fuse 0
  284. * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
  285. *
  286. * OCOTP_TESTER1 offset 0x420
  287. * 31:24 fuse 1
  288. * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
  289. * 23:16 fuse 1
  290. * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
  291. * 15:11 fuse 1
  292. * The wafer number of the wafer on which the device was fabricated/SJC
  293. * CHALLENGE/ Unique ID
  294. * 10:0 fuse 1
  295. * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
  296. */
  297. void get_board_serial(struct tag_serialnr *serialnr)
  298. {
  299. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  300. struct fuse_bank *bank = &ocotp->bank[0];
  301. struct fuse_bank0_regs *fuse =
  302. (struct fuse_bank0_regs *)bank->fuse_regs;
  303. serialnr->low = fuse->tester0;
  304. serialnr->high = fuse->tester1;
  305. }
  306. #endif
  307. void set_wdog_reset(struct wdog_regs *wdog)
  308. {
  309. u32 reg = readw(&wdog->wcr);
  310. /*
  311. * Output WDOG_B signal to reset external pmic or POR_B decided by
  312. * the board desgin. Without external reset, the peripherals/DDR/
  313. * PMIC are not reset, that may cause system working abnormal.
  314. */
  315. reg = readw(&wdog->wcr);
  316. reg |= 1 << 3;
  317. /*
  318. * WDZST bit is write-once only bit. Align this bit in kernel,
  319. * otherwise kernel code will have no chance to set this bit.
  320. */
  321. reg |= 1 << 0;
  322. writew(reg, &wdog->wcr);
  323. }
  324. void s_init(void)
  325. {
  326. /* clock configuration. */
  327. clock_init();
  328. return;
  329. }
  330. void reset_misc(void)
  331. {
  332. #ifndef CONFIG_SPL_BUILD
  333. #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
  334. lcdif_power_down();
  335. #endif
  336. #endif
  337. }