clock.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor, Inc.
  4. *
  5. * Author:
  6. * Peng Fan <Peng.Fan@freescale.com>
  7. */
  8. #include <common.h>
  9. #include <div64.h>
  10. #include <asm/io.h>
  11. #include <linux/errno.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/crm_regs.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/sys_proto.h>
  16. struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
  17. ANATOP_BASE_ADDR;
  18. struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  19. #ifdef CONFIG_FSL_ESDHC_IMX
  20. DECLARE_GLOBAL_DATA_PTR;
  21. #endif
  22. int get_clocks(void)
  23. {
  24. #ifdef CONFIG_FSL_ESDHC_IMX
  25. #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
  26. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  27. #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
  28. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  29. #else
  30. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  31. #endif
  32. #endif
  33. return 0;
  34. }
  35. u32 get_ahb_clk(void)
  36. {
  37. return get_root_clk(AHB_CLK_ROOT);
  38. }
  39. static u32 get_ipg_clk(void)
  40. {
  41. /*
  42. * The AHB and IPG are fixed at 2:1 ratio, and synchronized to
  43. * each other.
  44. */
  45. return get_ahb_clk() / 2;
  46. }
  47. u32 imx_get_uartclk(void)
  48. {
  49. return get_root_clk(UART_CLK_ROOT);
  50. }
  51. u32 imx_get_fecclk(void)
  52. {
  53. return get_root_clk(ENET_AXI_CLK_ROOT);
  54. }
  55. #ifdef CONFIG_MXC_OCOTP
  56. void enable_ocotp_clk(unsigned char enable)
  57. {
  58. clock_enable(CCGR_OCOTP, enable);
  59. }
  60. void enable_thermal_clk(void)
  61. {
  62. enable_ocotp_clk(1);
  63. }
  64. #endif
  65. void enable_usboh3_clk(unsigned char enable)
  66. {
  67. u32 target;
  68. if (enable) {
  69. /* disable the clock gate first */
  70. clock_enable(CCGR_USB_HSIC, 0);
  71. /* 120Mhz */
  72. target = CLK_ROOT_ON |
  73. USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
  74. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  75. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  76. clock_set_target_val(USB_HSIC_CLK_ROOT, target);
  77. /* enable the clock gate */
  78. clock_enable(CCGR_USB_CTRL, 1);
  79. clock_enable(CCGR_USB_HSIC, 1);
  80. clock_enable(CCGR_USB_PHY1, 1);
  81. clock_enable(CCGR_USB_PHY2, 1);
  82. } else {
  83. clock_enable(CCGR_USB_CTRL, 0);
  84. clock_enable(CCGR_USB_HSIC, 0);
  85. clock_enable(CCGR_USB_PHY1, 0);
  86. clock_enable(CCGR_USB_PHY2, 0);
  87. }
  88. }
  89. static u32 decode_pll(enum pll_clocks pll, u32 infreq)
  90. {
  91. u32 reg, div_sel;
  92. u32 num, denom;
  93. /*
  94. * Alought there are four choices for the bypass src,
  95. * we choose OSC_24M which is the default set in ROM.
  96. */
  97. switch (pll) {
  98. case PLL_CORE:
  99. reg = readl(&ccm_anatop->pll_arm);
  100. if (reg & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
  101. return 0;
  102. if (reg & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
  103. return MXC_HCLK;
  104. div_sel = (reg & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
  105. CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT;
  106. return (infreq * div_sel) / 2;
  107. case PLL_SYS:
  108. reg = readl(&ccm_anatop->pll_480);
  109. if (reg & CCM_ANALOG_PLL_480_POWERDOWN_MASK)
  110. return 0;
  111. if (reg & CCM_ANALOG_PLL_480_BYPASS_MASK)
  112. return MXC_HCLK;
  113. if (((reg & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) >>
  114. CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT) == 0)
  115. return 480000000u;
  116. else
  117. return 528000000u;
  118. case PLL_ENET:
  119. reg = readl(&ccm_anatop->pll_enet);
  120. if (reg & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
  121. return 0;
  122. if (reg & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
  123. return MXC_HCLK;
  124. return 1000000000u;
  125. case PLL_DDR:
  126. reg = readl(&ccm_anatop->pll_ddr);
  127. if (reg & CCM_ANALOG_PLL_DDR_POWERDOWN_MASK)
  128. return 0;
  129. num = ccm_anatop->pll_ddr_num;
  130. denom = ccm_anatop->pll_ddr_denom;
  131. if (reg & CCM_ANALOG_PLL_DDR_BYPASS_MASK)
  132. return MXC_HCLK;
  133. div_sel = (reg & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK) >>
  134. CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT;
  135. return infreq * (div_sel + num / denom);
  136. case PLL_USB:
  137. return 480000000u;
  138. default:
  139. printf("Unsupported pll clocks %d\n", pll);
  140. break;
  141. }
  142. return 0;
  143. }
  144. static u32 mxc_get_pll_sys_derive(int derive)
  145. {
  146. u32 freq, div, frac;
  147. u32 reg;
  148. div = 1;
  149. reg = readl(&ccm_anatop->pll_480);
  150. freq = decode_pll(PLL_SYS, MXC_HCLK);
  151. switch (derive) {
  152. case PLL_SYS_MAIN_480M_CLK:
  153. if (reg & CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK)
  154. return 0;
  155. else
  156. return freq;
  157. case PLL_SYS_MAIN_240M_CLK:
  158. if (reg & CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK)
  159. return 0;
  160. else
  161. return freq / 2;
  162. case PLL_SYS_MAIN_120M_CLK:
  163. if (reg & CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK)
  164. return 0;
  165. else
  166. return freq / 4;
  167. case PLL_SYS_PFD0_392M_CLK:
  168. reg = readl(&ccm_anatop->pfd_480a);
  169. if (reg & CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK)
  170. return 0;
  171. frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
  172. CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
  173. break;
  174. case PLL_SYS_PFD0_196M_CLK:
  175. if (reg & CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK)
  176. return 0;
  177. reg = readl(&ccm_anatop->pfd_480a);
  178. frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
  179. CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
  180. div = 2;
  181. break;
  182. case PLL_SYS_PFD1_332M_CLK:
  183. reg = readl(&ccm_anatop->pfd_480a);
  184. if (reg & CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK)
  185. return 0;
  186. frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
  187. CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
  188. break;
  189. case PLL_SYS_PFD1_166M_CLK:
  190. if (reg & CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK)
  191. return 0;
  192. reg = readl(&ccm_anatop->pfd_480a);
  193. frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
  194. CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
  195. div = 2;
  196. break;
  197. case PLL_SYS_PFD2_270M_CLK:
  198. reg = readl(&ccm_anatop->pfd_480a);
  199. if (reg & CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK)
  200. return 0;
  201. frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
  202. CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
  203. break;
  204. case PLL_SYS_PFD2_135M_CLK:
  205. if (reg & CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK)
  206. return 0;
  207. reg = readl(&ccm_anatop->pfd_480a);
  208. frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
  209. CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
  210. div = 2;
  211. break;
  212. case PLL_SYS_PFD3_CLK:
  213. reg = readl(&ccm_anatop->pfd_480a);
  214. if (reg & CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK)
  215. return 0;
  216. frac = (reg & CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) >>
  217. CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT;
  218. break;
  219. case PLL_SYS_PFD4_CLK:
  220. reg = readl(&ccm_anatop->pfd_480b);
  221. if (reg & CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK)
  222. return 0;
  223. frac = (reg & CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) >>
  224. CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT;
  225. break;
  226. case PLL_SYS_PFD5_CLK:
  227. reg = readl(&ccm_anatop->pfd_480b);
  228. if (reg & CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK)
  229. return 0;
  230. frac = (reg & CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK) >>
  231. CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT;
  232. break;
  233. case PLL_SYS_PFD6_CLK:
  234. reg = readl(&ccm_anatop->pfd_480b);
  235. if (reg & CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK)
  236. return 0;
  237. frac = (reg & CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK) >>
  238. CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT;
  239. break;
  240. case PLL_SYS_PFD7_CLK:
  241. reg = readl(&ccm_anatop->pfd_480b);
  242. if (reg & CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK)
  243. return 0;
  244. frac = (reg & CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK) >>
  245. CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT;
  246. break;
  247. default:
  248. printf("Error derived pll_sys clock %d\n", derive);
  249. return 0;
  250. }
  251. return ((freq / frac) * 18) / div;
  252. }
  253. static u32 mxc_get_pll_enet_derive(int derive)
  254. {
  255. u32 freq, reg;
  256. freq = decode_pll(PLL_ENET, MXC_HCLK);
  257. reg = readl(&ccm_anatop->pll_enet);
  258. switch (derive) {
  259. case PLL_ENET_MAIN_500M_CLK:
  260. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK)
  261. return freq / 2;
  262. break;
  263. case PLL_ENET_MAIN_250M_CLK:
  264. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK)
  265. return freq / 4;
  266. break;
  267. case PLL_ENET_MAIN_125M_CLK:
  268. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK)
  269. return freq / 8;
  270. break;
  271. case PLL_ENET_MAIN_100M_CLK:
  272. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK)
  273. return freq / 10;
  274. break;
  275. case PLL_ENET_MAIN_50M_CLK:
  276. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK)
  277. return freq / 20;
  278. break;
  279. case PLL_ENET_MAIN_40M_CLK:
  280. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK)
  281. return freq / 25;
  282. break;
  283. case PLL_ENET_MAIN_25M_CLK:
  284. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK)
  285. return freq / 40;
  286. break;
  287. default:
  288. printf("Error derived pll_enet clock %d\n", derive);
  289. break;
  290. }
  291. return 0;
  292. }
  293. static u32 mxc_get_pll_ddr_derive(int derive)
  294. {
  295. u32 freq, reg;
  296. freq = decode_pll(PLL_DDR, MXC_HCLK);
  297. reg = readl(&ccm_anatop->pll_ddr);
  298. switch (derive) {
  299. case PLL_DRAM_MAIN_1066M_CLK:
  300. return freq;
  301. case PLL_DRAM_MAIN_533M_CLK:
  302. if (reg & CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK)
  303. return freq / 2;
  304. break;
  305. default:
  306. printf("Error derived pll_ddr clock %d\n", derive);
  307. break;
  308. }
  309. return 0;
  310. }
  311. static u32 mxc_get_pll_derive(enum pll_clocks pll, int derive)
  312. {
  313. switch (pll) {
  314. case PLL_SYS:
  315. return mxc_get_pll_sys_derive(derive);
  316. case PLL_ENET:
  317. return mxc_get_pll_enet_derive(derive);
  318. case PLL_DDR:
  319. return mxc_get_pll_ddr_derive(derive);
  320. default:
  321. printf("Error pll.\n");
  322. return 0;
  323. }
  324. }
  325. static u32 get_root_src_clk(enum clk_root_src root_src)
  326. {
  327. switch (root_src) {
  328. case OSC_24M_CLK:
  329. return 24000000u;
  330. case PLL_ARM_MAIN_800M_CLK:
  331. return decode_pll(PLL_CORE, MXC_HCLK);
  332. case PLL_SYS_MAIN_480M_CLK:
  333. case PLL_SYS_MAIN_240M_CLK:
  334. case PLL_SYS_MAIN_120M_CLK:
  335. case PLL_SYS_PFD0_392M_CLK:
  336. case PLL_SYS_PFD0_196M_CLK:
  337. case PLL_SYS_PFD1_332M_CLK:
  338. case PLL_SYS_PFD1_166M_CLK:
  339. case PLL_SYS_PFD2_270M_CLK:
  340. case PLL_SYS_PFD2_135M_CLK:
  341. case PLL_SYS_PFD3_CLK:
  342. case PLL_SYS_PFD4_CLK:
  343. case PLL_SYS_PFD5_CLK:
  344. case PLL_SYS_PFD6_CLK:
  345. case PLL_SYS_PFD7_CLK:
  346. return mxc_get_pll_derive(PLL_SYS, root_src);
  347. case PLL_ENET_MAIN_500M_CLK:
  348. case PLL_ENET_MAIN_250M_CLK:
  349. case PLL_ENET_MAIN_125M_CLK:
  350. case PLL_ENET_MAIN_100M_CLK:
  351. case PLL_ENET_MAIN_50M_CLK:
  352. case PLL_ENET_MAIN_40M_CLK:
  353. case PLL_ENET_MAIN_25M_CLK:
  354. return mxc_get_pll_derive(PLL_ENET, root_src);
  355. case PLL_DRAM_MAIN_1066M_CLK:
  356. case PLL_DRAM_MAIN_533M_CLK:
  357. return mxc_get_pll_derive(PLL_DDR, root_src);
  358. case PLL_AUDIO_MAIN_CLK:
  359. return decode_pll(PLL_AUDIO, MXC_HCLK);
  360. case PLL_VIDEO_MAIN_CLK:
  361. return decode_pll(PLL_VIDEO, MXC_HCLK);
  362. case PLL_USB_MAIN_480M_CLK:
  363. return decode_pll(PLL_USB, MXC_HCLK);
  364. case REF_1M_CLK:
  365. return 1000000;
  366. case OSC_32K_CLK:
  367. return MXC_CLK32;
  368. case EXT_CLK_1:
  369. case EXT_CLK_2:
  370. case EXT_CLK_3:
  371. case EXT_CLK_4:
  372. printf("No EXT CLK supported??\n");
  373. break;
  374. };
  375. return 0;
  376. }
  377. u32 get_root_clk(enum clk_root_index clock_id)
  378. {
  379. enum clk_root_src root_src;
  380. u32 post_podf, pre_podf, auto_podf, root_src_clk;
  381. int auto_en;
  382. if (clock_root_enabled(clock_id) <= 0)
  383. return 0;
  384. if (clock_get_prediv(clock_id, &pre_podf) < 0)
  385. return 0;
  386. if (clock_get_postdiv(clock_id, &post_podf) < 0)
  387. return 0;
  388. if (clock_get_autopostdiv(clock_id, &auto_podf, &auto_en) < 0)
  389. return 0;
  390. if (auto_en == 0)
  391. auto_podf = 0;
  392. if (clock_get_src(clock_id, &root_src) < 0)
  393. return 0;
  394. root_src_clk = get_root_src_clk(root_src);
  395. /*
  396. * bypass clk is ignored.
  397. */
  398. return root_src_clk / (post_podf + 1) / (pre_podf + 1) /
  399. (auto_podf + 1);
  400. }
  401. static u32 get_ddrc_clk(void)
  402. {
  403. u32 reg, freq;
  404. enum root_post_div post_div;
  405. reg = readl(&ccm_reg->root[DRAM_CLK_ROOT].target_root);
  406. if (reg & CLK_ROOT_MUX_MASK)
  407. /* DRAM_ALT_CLK_ROOT */
  408. freq = get_root_clk(DRAM_ALT_CLK_ROOT);
  409. else
  410. /* PLL_DRAM_MAIN_1066M_CLK */
  411. freq = mxc_get_pll_derive(PLL_DDR, PLL_DRAM_MAIN_1066M_CLK);
  412. post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK;
  413. return freq / (post_div + 1) / 2;
  414. }
  415. unsigned int mxc_get_clock(enum mxc_clock clk)
  416. {
  417. switch (clk) {
  418. case MXC_ARM_CLK:
  419. return get_root_clk(ARM_A7_CLK_ROOT);
  420. case MXC_AXI_CLK:
  421. return get_root_clk(MAIN_AXI_CLK_ROOT);
  422. case MXC_AHB_CLK:
  423. return get_root_clk(AHB_CLK_ROOT);
  424. case MXC_IPG_CLK:
  425. return get_ipg_clk();
  426. case MXC_I2C_CLK:
  427. return get_root_clk(I2C1_CLK_ROOT);
  428. case MXC_UART_CLK:
  429. return get_root_clk(UART1_CLK_ROOT);
  430. case MXC_CSPI_CLK:
  431. return get_root_clk(ECSPI1_CLK_ROOT);
  432. case MXC_DDR_CLK:
  433. return get_ddrc_clk();
  434. case MXC_ESDHC_CLK:
  435. return get_root_clk(USDHC1_CLK_ROOT);
  436. case MXC_ESDHC2_CLK:
  437. return get_root_clk(USDHC2_CLK_ROOT);
  438. case MXC_ESDHC3_CLK:
  439. return get_root_clk(USDHC3_CLK_ROOT);
  440. default:
  441. printf("Unsupported mxc_clock %d\n", clk);
  442. break;
  443. }
  444. return 0;
  445. }
  446. #ifdef CONFIG_SYS_I2C_MXC
  447. /* i2c_num can be 0 - 3 */
  448. int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
  449. {
  450. u32 target;
  451. if (i2c_num >= 4)
  452. return -EINVAL;
  453. if (enable) {
  454. clock_enable(CCGR_I2C1 + i2c_num, 0);
  455. /* Set i2c root clock to PLL_SYS_MAIN_120M_CLK */
  456. target = CLK_ROOT_ON |
  457. I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
  458. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  459. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  460. clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target);
  461. clock_enable(CCGR_I2C1 + i2c_num, 1);
  462. } else {
  463. clock_enable(CCGR_I2C1 + i2c_num, 0);
  464. }
  465. return 0;
  466. }
  467. #endif
  468. static void init_clk_esdhc(void)
  469. {
  470. u32 target;
  471. /* disable the clock gate first */
  472. clock_enable(CCGR_USDHC1, 0);
  473. clock_enable(CCGR_USDHC2, 0);
  474. clock_enable(CCGR_USDHC3, 0);
  475. /* 196: 392/2 */
  476. target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
  477. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  478. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  479. clock_set_target_val(USDHC1_CLK_ROOT, target);
  480. target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
  481. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  482. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  483. clock_set_target_val(USDHC2_CLK_ROOT, target);
  484. target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
  485. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  486. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  487. clock_set_target_val(USDHC3_CLK_ROOT, target);
  488. /* enable the clock gate */
  489. clock_enable(CCGR_USDHC1, 1);
  490. clock_enable(CCGR_USDHC2, 1);
  491. clock_enable(CCGR_USDHC3, 1);
  492. }
  493. static void init_clk_uart(void)
  494. {
  495. u32 target;
  496. /* disable the clock gate first */
  497. clock_enable(CCGR_UART1, 0);
  498. clock_enable(CCGR_UART2, 0);
  499. clock_enable(CCGR_UART3, 0);
  500. clock_enable(CCGR_UART4, 0);
  501. clock_enable(CCGR_UART5, 0);
  502. clock_enable(CCGR_UART6, 0);
  503. clock_enable(CCGR_UART7, 0);
  504. /* 24Mhz */
  505. target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK |
  506. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  507. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  508. clock_set_target_val(UART1_CLK_ROOT, target);
  509. target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK |
  510. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  511. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  512. clock_set_target_val(UART2_CLK_ROOT, target);
  513. target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK |
  514. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  515. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  516. clock_set_target_val(UART3_CLK_ROOT, target);
  517. target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK |
  518. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  519. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  520. clock_set_target_val(UART4_CLK_ROOT, target);
  521. target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK |
  522. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  523. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  524. clock_set_target_val(UART5_CLK_ROOT, target);
  525. target = CLK_ROOT_ON | UART6_CLK_ROOT_FROM_OSC_24M_CLK |
  526. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  527. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  528. clock_set_target_val(UART6_CLK_ROOT, target);
  529. target = CLK_ROOT_ON | UART7_CLK_ROOT_FROM_OSC_24M_CLK |
  530. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  531. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  532. clock_set_target_val(UART7_CLK_ROOT, target);
  533. /* enable the clock gate */
  534. clock_enable(CCGR_UART1, 1);
  535. clock_enable(CCGR_UART2, 1);
  536. clock_enable(CCGR_UART3, 1);
  537. clock_enable(CCGR_UART4, 1);
  538. clock_enable(CCGR_UART5, 1);
  539. clock_enable(CCGR_UART6, 1);
  540. clock_enable(CCGR_UART7, 1);
  541. }
  542. static void init_clk_weim(void)
  543. {
  544. u32 target;
  545. /* disable the clock gate first */
  546. clock_enable(CCGR_WEIM, 0);
  547. /* 120Mhz */
  548. target = CLK_ROOT_ON | EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
  549. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  550. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  551. clock_set_target_val(EIM_CLK_ROOT, target);
  552. /* enable the clock gate */
  553. clock_enable(CCGR_WEIM, 1);
  554. }
  555. static void init_clk_ecspi(void)
  556. {
  557. u32 target;
  558. /* disable the clock gate first */
  559. clock_enable(CCGR_ECSPI1, 0);
  560. clock_enable(CCGR_ECSPI2, 0);
  561. clock_enable(CCGR_ECSPI3, 0);
  562. clock_enable(CCGR_ECSPI4, 0);
  563. /* 60Mhz: 240/4 */
  564. target = CLK_ROOT_ON | ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
  565. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  566. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  567. clock_set_target_val(ECSPI1_CLK_ROOT, target);
  568. target = CLK_ROOT_ON | ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
  569. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  570. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  571. clock_set_target_val(ECSPI2_CLK_ROOT, target);
  572. target = CLK_ROOT_ON | ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
  573. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  574. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  575. clock_set_target_val(ECSPI3_CLK_ROOT, target);
  576. target = CLK_ROOT_ON | ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
  577. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  578. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  579. clock_set_target_val(ECSPI4_CLK_ROOT, target);
  580. /* enable the clock gate */
  581. clock_enable(CCGR_ECSPI1, 1);
  582. clock_enable(CCGR_ECSPI2, 1);
  583. clock_enable(CCGR_ECSPI3, 1);
  584. clock_enable(CCGR_ECSPI4, 1);
  585. }
  586. static void init_clk_wdog(void)
  587. {
  588. u32 target;
  589. /* disable the clock gate first */
  590. clock_enable(CCGR_WDOG1, 0);
  591. clock_enable(CCGR_WDOG2, 0);
  592. clock_enable(CCGR_WDOG3, 0);
  593. clock_enable(CCGR_WDOG4, 0);
  594. /* 24Mhz */
  595. target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK |
  596. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  597. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  598. clock_set_target_val(WDOG_CLK_ROOT, target);
  599. /* enable the clock gate */
  600. clock_enable(CCGR_WDOG1, 1);
  601. clock_enable(CCGR_WDOG2, 1);
  602. clock_enable(CCGR_WDOG3, 1);
  603. clock_enable(CCGR_WDOG4, 1);
  604. }
  605. #ifdef CONFIG_MXC_EPDC
  606. static void init_clk_epdc(void)
  607. {
  608. u32 target;
  609. /* disable the clock gate first */
  610. clock_enable(CCGR_EPDC, 0);
  611. /* 24Mhz */
  612. target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
  613. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  614. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV12);
  615. clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target);
  616. /* enable the clock gate */
  617. clock_enable(CCGR_EPDC, 1);
  618. }
  619. #endif
  620. static int enable_pll_enet(void)
  621. {
  622. u32 reg;
  623. s32 timeout = 100000;
  624. reg = readl(&ccm_anatop->pll_enet);
  625. /* If pll_enet powered up, no need to set it again */
  626. if (reg & ANADIG_PLL_ENET_PWDN_MASK) {
  627. reg &= ~ANADIG_PLL_ENET_PWDN_MASK;
  628. writel(reg, &ccm_anatop->pll_enet);
  629. while (timeout--) {
  630. if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK)
  631. break;
  632. }
  633. if (timeout <= 0) {
  634. /* If timeout, we set pwdn for pll_enet. */
  635. reg |= ANADIG_PLL_ENET_PWDN_MASK;
  636. return -ETIME;
  637. }
  638. }
  639. /* Clear bypass */
  640. writel(CCM_ANALOG_PLL_ENET_BYPASS_MASK, &ccm_anatop->pll_enet_clr);
  641. writel((CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK
  642. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK
  643. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK
  644. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK
  645. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK
  646. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK
  647. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK),
  648. &ccm_anatop->pll_enet_set);
  649. return 0;
  650. }
  651. static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
  652. u32 post_div)
  653. {
  654. u32 reg = 0;
  655. ulong start;
  656. debug("pll5 div = %d, num = %d, denom = %d\n",
  657. pll_div, pll_num, pll_denom);
  658. /* Power up PLL5 video and disable its output */
  659. writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK |
  660. CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK |
  661. CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK |
  662. CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK |
  663. CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK |
  664. CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK,
  665. &ccm_anatop->pll_video_clr);
  666. /* Set div, num and denom */
  667. switch (post_div) {
  668. case 1:
  669. writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
  670. CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x1) |
  671. CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
  672. &ccm_anatop->pll_video_set);
  673. break;
  674. case 2:
  675. writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
  676. CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
  677. CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
  678. &ccm_anatop->pll_video_set);
  679. break;
  680. case 3:
  681. writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
  682. CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
  683. CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x1),
  684. &ccm_anatop->pll_video_set);
  685. break;
  686. case 4:
  687. writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
  688. CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
  689. CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x3),
  690. &ccm_anatop->pll_video_set);
  691. break;
  692. case 0:
  693. default:
  694. writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
  695. CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x2) |
  696. CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
  697. &ccm_anatop->pll_video_set);
  698. break;
  699. }
  700. writel(CCM_ANALOG_PLL_VIDEO_NUM_A(pll_num),
  701. &ccm_anatop->pll_video_num);
  702. writel(CCM_ANALOG_PLL_VIDEO_DENOM_B(pll_denom),
  703. &ccm_anatop->pll_video_denom);
  704. /* Wait PLL5 lock */
  705. start = get_timer(0); /* Get current timestamp */
  706. do {
  707. reg = readl(&ccm_anatop->pll_video);
  708. if (reg & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) {
  709. /* Enable PLL out */
  710. writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK,
  711. &ccm_anatop->pll_video_set);
  712. return 0;
  713. }
  714. } while (get_timer(0) < (start + 10)); /* Wait 10ms */
  715. printf("Lock PLL5 timeout\n");
  716. return 1;
  717. }
  718. int set_clk_qspi(void)
  719. {
  720. u32 target;
  721. /* disable the clock gate first */
  722. clock_enable(CCGR_QSPI, 0);
  723. /* 49M: 392/2/4 */
  724. target = CLK_ROOT_ON | QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
  725. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  726. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  727. clock_set_target_val(QSPI_CLK_ROOT, target);
  728. /* enable the clock gate */
  729. clock_enable(CCGR_QSPI, 1);
  730. return 0;
  731. }
  732. int set_clk_nand(void)
  733. {
  734. u32 target;
  735. /* disable the clock gate first */
  736. clock_enable(CCGR_RAWNAND, 0);
  737. enable_pll_enet();
  738. /* 100: 500/5 */
  739. target = CLK_ROOT_ON | NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK |
  740. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  741. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV5);
  742. clock_set_target_val(NAND_CLK_ROOT, target);
  743. /* enable the clock gate */
  744. clock_enable(CCGR_RAWNAND, 1);
  745. return 0;
  746. }
  747. void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
  748. {
  749. u32 hck = MXC_HCLK/1000;
  750. u32 min = hck * 27;
  751. u32 max = hck * 54;
  752. u32 temp, best = 0;
  753. u32 i, j, pred = 1, postd = 1;
  754. u32 pll_div, pll_num, pll_denom, post_div = 0;
  755. u32 target;
  756. debug("mxs_set_lcdclk, freq = %d\n", freq);
  757. clock_enable(CCGR_LCDIF, 0);
  758. temp = (freq * 8 * 8);
  759. if (temp < min) {
  760. for (i = 1; i <= 4; i++) {
  761. if ((temp * (1 << i)) > min) {
  762. post_div = i;
  763. freq = (freq * (1 << i));
  764. break;
  765. }
  766. }
  767. if (5 == i) {
  768. printf("Fail to set rate to %dkhz", freq);
  769. return;
  770. }
  771. }
  772. for (i = 1; i <= 8; i++) {
  773. for (j = 1; j <= 8; j++) {
  774. temp = freq * i * j;
  775. if (temp > max || temp < min)
  776. continue;
  777. if (best == 0 || temp < best) {
  778. best = temp;
  779. pred = i;
  780. postd = j;
  781. }
  782. }
  783. }
  784. if (best == 0) {
  785. printf("Fail to set rate to %dkhz", freq);
  786. return;
  787. }
  788. debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
  789. pll_div = best / hck;
  790. pll_denom = 1000000;
  791. pll_num = (best - hck * pll_div) * pll_denom / hck;
  792. if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
  793. return;
  794. target = CLK_ROOT_ON | LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK |
  795. CLK_ROOT_PRE_DIV((pred - 1)) | CLK_ROOT_POST_DIV((postd - 1));
  796. clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, target);
  797. clock_enable(CCGR_LCDIF, 1);
  798. }
  799. #ifdef CONFIG_FEC_MXC
  800. int set_clk_enet(enum enet_freq type)
  801. {
  802. u32 target;
  803. int ret;
  804. u32 enet1_ref, enet2_ref;
  805. /* disable the clock first */
  806. clock_enable(CCGR_ENET1, 0);
  807. clock_enable(CCGR_ENET2, 0);
  808. switch (type) {
  809. case ENET_125MHZ:
  810. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
  811. enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
  812. break;
  813. case ENET_50MHZ:
  814. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
  815. enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
  816. break;
  817. case ENET_25MHZ:
  818. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
  819. enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
  820. break;
  821. default:
  822. return -EINVAL;
  823. }
  824. ret = enable_pll_enet();
  825. if (ret != 0)
  826. return ret;
  827. /* set enet axi clock 196M: 392/2 */
  828. target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
  829. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  830. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  831. clock_set_target_val(ENET_AXI_CLK_ROOT, target);
  832. target = CLK_ROOT_ON | enet1_ref |
  833. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  834. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  835. clock_set_target_val(ENET1_REF_CLK_ROOT, target);
  836. target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
  837. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  838. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  839. clock_set_target_val(ENET1_TIME_CLK_ROOT, target);
  840. target = CLK_ROOT_ON | enet2_ref |
  841. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  842. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  843. clock_set_target_val(ENET2_REF_CLK_ROOT, target);
  844. target = CLK_ROOT_ON | ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
  845. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  846. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  847. clock_set_target_val(ENET2_TIME_CLK_ROOT, target);
  848. #ifdef CONFIG_FEC_MXC_25M_REF_CLK
  849. target = CLK_ROOT_ON |
  850. ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
  851. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  852. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  853. clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
  854. #endif
  855. /* enable clock */
  856. clock_enable(CCGR_ENET1, 1);
  857. clock_enable(CCGR_ENET2, 1);
  858. return 0;
  859. }
  860. #endif
  861. /* Configure PLL/PFD freq */
  862. void clock_init(void)
  863. {
  864. /* Rom has enabled PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET
  865. * In u-boot, we have to:
  866. * 1. Configure PFD3- PFD7 for freq we needed in u-boot
  867. * 2. Set clock root for peripherals (ip channel) used in u-boot but without set rate
  868. * interface. The clocks for these peripherals are enabled after this intialization.
  869. * 3. Other peripherals with set clock rate interface does not be set in this function.
  870. */
  871. u32 reg;
  872. /*
  873. * Configure PFD4 to 392M
  874. * 480M * 18 / 0x16 = 392M
  875. */
  876. reg = readl(&ccm_anatop->pfd_480b);
  877. reg &= ~(ANATOP_PFD480B_PFD4_FRAC_MASK |
  878. CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK);
  879. reg |= ANATOP_PFD480B_PFD4_FRAC_392M_VAL;
  880. writel(reg, &ccm_anatop->pfd_480b);
  881. init_clk_esdhc();
  882. init_clk_uart();
  883. init_clk_weim();
  884. init_clk_ecspi();
  885. init_clk_wdog();
  886. #ifdef CONFIG_MXC_EPDC
  887. init_clk_epdc();
  888. #endif
  889. enable_usboh3_clk(1);
  890. clock_enable(CCGR_SNVS, 1);
  891. #ifdef CONFIG_NAND_MXS
  892. clock_enable(CCGR_RAWNAND, 1);
  893. #endif
  894. if (IS_ENABLED(CONFIG_IMX_RDC)) {
  895. clock_enable(CCGR_RDC, 1);
  896. clock_enable(CCGR_SEMA1, 1);
  897. clock_enable(CCGR_SEMA2, 1);
  898. }
  899. }
  900. #ifdef CONFIG_IMX_HAB
  901. void hab_caam_clock_enable(unsigned char enable)
  902. {
  903. if (enable)
  904. clock_enable(CCGR_CAAM, 1);
  905. else
  906. clock_enable(CCGR_CAAM, 0);
  907. }
  908. #endif
  909. #ifdef CONFIG_MXC_EPDC
  910. void epdc_clock_enable(void)
  911. {
  912. clock_enable(CCGR_EPDC, 1);
  913. }
  914. void epdc_clock_disable(void)
  915. {
  916. clock_enable(CCGR_EPDC, 0);
  917. }
  918. #endif
  919. #ifndef CONFIG_SPL_BUILD
  920. /*
  921. * Dump some core clockes.
  922. */
  923. int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  924. {
  925. u32 freq;
  926. freq = decode_pll(PLL_CORE, MXC_HCLK);
  927. printf("PLL_CORE %8d MHz\n", freq / 1000000);
  928. freq = decode_pll(PLL_SYS, MXC_HCLK);
  929. printf("PLL_SYS %8d MHz\n", freq / 1000000);
  930. freq = decode_pll(PLL_ENET, MXC_HCLK);
  931. printf("PLL_NET %8d MHz\n", freq / 1000000);
  932. printf("\n");
  933. printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
  934. printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
  935. #ifdef CONFIG_MXC_SPI
  936. printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
  937. #endif
  938. printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
  939. printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
  940. printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
  941. printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
  942. printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
  943. printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
  944. return 0;
  945. }
  946. U_BOOT_CMD(
  947. clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,
  948. "display clocks",
  949. ""
  950. );
  951. #endif