clock.c 37 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <div64.h>
  7. #include <asm/io.h>
  8. #include <linux/errno.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/crm_regs.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/sys_proto.h>
  13. enum pll_clocks {
  14. PLL_SYS, /* System PLL */
  15. PLL_BUS, /* System Bus PLL*/
  16. PLL_USBOTG, /* OTG USB PLL */
  17. PLL_ENET, /* ENET PLL */
  18. PLL_AUDIO, /* AUDIO PLL */
  19. PLL_VIDEO, /* VIDEO PLL */
  20. };
  21. struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  22. #ifdef CONFIG_MXC_OCOTP
  23. void enable_ocotp_clk(unsigned char enable)
  24. {
  25. u32 reg;
  26. reg = __raw_readl(&imx_ccm->CCGR2);
  27. if (enable)
  28. reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  29. else
  30. reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  31. __raw_writel(reg, &imx_ccm->CCGR2);
  32. }
  33. #endif
  34. #ifdef CONFIG_NAND_MXS
  35. void setup_gpmi_io_clk(u32 cfg)
  36. {
  37. /* Disable clocks per ERR007177 from MX6 errata */
  38. clrbits_le32(&imx_ccm->CCGR4,
  39. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  40. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  41. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  42. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  43. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  44. #if defined(CONFIG_MX6SX)
  45. clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
  46. clrsetbits_le32(&imx_ccm->cs2cdr,
  47. MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
  48. MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
  49. MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
  50. cfg);
  51. setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
  52. #else
  53. clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  54. clrsetbits_le32(&imx_ccm->cs2cdr,
  55. MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  56. MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  57. MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  58. cfg);
  59. setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  60. #endif
  61. setbits_le32(&imx_ccm->CCGR4,
  62. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  63. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  64. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  65. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  66. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  67. }
  68. #endif
  69. void enable_usboh3_clk(unsigned char enable)
  70. {
  71. u32 reg;
  72. reg = __raw_readl(&imx_ccm->CCGR6);
  73. if (enable)
  74. reg |= MXC_CCM_CCGR6_USBOH3_MASK;
  75. else
  76. reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
  77. __raw_writel(reg, &imx_ccm->CCGR6);
  78. }
  79. #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
  80. void enable_enet_clk(unsigned char enable)
  81. {
  82. u32 mask, *addr;
  83. if (is_mx6ull()) {
  84. mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK;
  85. addr = &imx_ccm->CCGR0;
  86. } else if (is_mx6ul()) {
  87. mask = MXC_CCM_CCGR3_ENET_MASK;
  88. addr = &imx_ccm->CCGR3;
  89. } else {
  90. mask = MXC_CCM_CCGR1_ENET_MASK;
  91. addr = &imx_ccm->CCGR1;
  92. }
  93. if (enable)
  94. setbits_le32(addr, mask);
  95. else
  96. clrbits_le32(addr, mask);
  97. }
  98. #endif
  99. #ifdef CONFIG_MXC_UART
  100. void enable_uart_clk(unsigned char enable)
  101. {
  102. u32 mask;
  103. if (is_mx6ul() || is_mx6ull())
  104. mask = MXC_CCM_CCGR5_UART_MASK;
  105. else
  106. mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
  107. if (enable)
  108. setbits_le32(&imx_ccm->CCGR5, mask);
  109. else
  110. clrbits_le32(&imx_ccm->CCGR5, mask);
  111. }
  112. #endif
  113. #ifdef CONFIG_MMC
  114. int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
  115. {
  116. u32 mask;
  117. if (bus_num > 3)
  118. return -EINVAL;
  119. mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
  120. if (enable)
  121. setbits_le32(&imx_ccm->CCGR6, mask);
  122. else
  123. clrbits_le32(&imx_ccm->CCGR6, mask);
  124. return 0;
  125. }
  126. #endif
  127. #ifdef CONFIG_SYS_I2C_MXC
  128. /* i2c_num can be from 0 - 3 */
  129. int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
  130. {
  131. u32 reg;
  132. u32 mask;
  133. u32 *addr;
  134. if (i2c_num > 3)
  135. return -EINVAL;
  136. if (i2c_num < 3) {
  137. mask = MXC_CCM_CCGR_CG_MASK
  138. << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
  139. + (i2c_num << 1));
  140. reg = __raw_readl(&imx_ccm->CCGR2);
  141. if (enable)
  142. reg |= mask;
  143. else
  144. reg &= ~mask;
  145. __raw_writel(reg, &imx_ccm->CCGR2);
  146. } else {
  147. if (is_mx6sll())
  148. return -EINVAL;
  149. if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
  150. mask = MXC_CCM_CCGR6_I2C4_MASK;
  151. addr = &imx_ccm->CCGR6;
  152. } else {
  153. mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
  154. addr = &imx_ccm->CCGR1;
  155. }
  156. reg = __raw_readl(addr);
  157. if (enable)
  158. reg |= mask;
  159. else
  160. reg &= ~mask;
  161. __raw_writel(reg, addr);
  162. }
  163. return 0;
  164. }
  165. #endif
  166. /* spi_num can be from 0 - SPI_MAX_NUM */
  167. int enable_spi_clk(unsigned char enable, unsigned spi_num)
  168. {
  169. u32 reg;
  170. u32 mask;
  171. if (spi_num > SPI_MAX_NUM)
  172. return -EINVAL;
  173. mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
  174. reg = __raw_readl(&imx_ccm->CCGR1);
  175. if (enable)
  176. reg |= mask;
  177. else
  178. reg &= ~mask;
  179. __raw_writel(reg, &imx_ccm->CCGR1);
  180. return 0;
  181. }
  182. static u32 decode_pll(enum pll_clocks pll, u32 infreq)
  183. {
  184. u32 div, test_div, pll_num, pll_denom;
  185. switch (pll) {
  186. case PLL_SYS:
  187. div = __raw_readl(&imx_ccm->analog_pll_sys);
  188. div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
  189. return (infreq * div) >> 1;
  190. case PLL_BUS:
  191. div = __raw_readl(&imx_ccm->analog_pll_528);
  192. div &= BM_ANADIG_PLL_528_DIV_SELECT;
  193. return infreq * (20 + (div << 1));
  194. case PLL_USBOTG:
  195. div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
  196. div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
  197. return infreq * (20 + (div << 1));
  198. case PLL_ENET:
  199. div = __raw_readl(&imx_ccm->analog_pll_enet);
  200. div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
  201. return 25000000 * (div + (div >> 1) + 1);
  202. case PLL_AUDIO:
  203. div = __raw_readl(&imx_ccm->analog_pll_audio);
  204. if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE))
  205. return 0;
  206. /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
  207. if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
  208. return MXC_HCLK;
  209. pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);
  210. pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);
  211. test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >>
  212. BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT;
  213. div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
  214. if (test_div == 3) {
  215. debug("Error test_div\n");
  216. return 0;
  217. }
  218. test_div = 1 << (2 - test_div);
  219. return infreq * (div + pll_num / pll_denom) / test_div;
  220. case PLL_VIDEO:
  221. div = __raw_readl(&imx_ccm->analog_pll_video);
  222. if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE))
  223. return 0;
  224. /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
  225. if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
  226. return MXC_HCLK;
  227. pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);
  228. pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);
  229. test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
  230. BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
  231. div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
  232. if (test_div == 3) {
  233. debug("Error test_div\n");
  234. return 0;
  235. }
  236. test_div = 1 << (2 - test_div);
  237. return infreq * (div + pll_num / pll_denom) / test_div;
  238. default:
  239. return 0;
  240. }
  241. /* NOTREACHED */
  242. }
  243. static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
  244. {
  245. u32 div;
  246. u64 freq;
  247. switch (pll) {
  248. case PLL_BUS:
  249. if (!is_mx6ul() && !is_mx6ull()) {
  250. if (pfd_num == 3) {
  251. /* No PFD3 on PLL2 */
  252. return 0;
  253. }
  254. }
  255. div = __raw_readl(&imx_ccm->analog_pfd_528);
  256. freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
  257. break;
  258. case PLL_USBOTG:
  259. div = __raw_readl(&imx_ccm->analog_pfd_480);
  260. freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
  261. break;
  262. default:
  263. /* No PFD on other PLL */
  264. return 0;
  265. }
  266. return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
  267. ANATOP_PFD_FRAC_SHIFT(pfd_num));
  268. }
  269. static u32 get_mcu_main_clk(void)
  270. {
  271. u32 reg, freq;
  272. reg = __raw_readl(&imx_ccm->cacrr);
  273. reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
  274. reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
  275. freq = decode_pll(PLL_SYS, MXC_HCLK);
  276. return freq / (reg + 1);
  277. }
  278. u32 get_periph_clk(void)
  279. {
  280. u32 reg, div = 0, freq = 0;
  281. reg = __raw_readl(&imx_ccm->cbcdr);
  282. if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
  283. div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
  284. MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
  285. reg = __raw_readl(&imx_ccm->cbcmr);
  286. reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
  287. reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
  288. switch (reg) {
  289. case 0:
  290. freq = decode_pll(PLL_USBOTG, MXC_HCLK);
  291. break;
  292. case 1:
  293. case 2:
  294. freq = MXC_HCLK;
  295. break;
  296. default:
  297. break;
  298. }
  299. } else {
  300. reg = __raw_readl(&imx_ccm->cbcmr);
  301. reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
  302. reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
  303. switch (reg) {
  304. case 0:
  305. freq = decode_pll(PLL_BUS, MXC_HCLK);
  306. break;
  307. case 1:
  308. freq = mxc_get_pll_pfd(PLL_BUS, 2);
  309. break;
  310. case 2:
  311. freq = mxc_get_pll_pfd(PLL_BUS, 0);
  312. break;
  313. case 3:
  314. /* static / 2 divider */
  315. freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
  316. break;
  317. default:
  318. break;
  319. }
  320. }
  321. return freq / (div + 1);
  322. }
  323. static u32 get_ipg_clk(void)
  324. {
  325. u32 reg, ipg_podf;
  326. reg = __raw_readl(&imx_ccm->cbcdr);
  327. reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
  328. ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
  329. return get_ahb_clk() / (ipg_podf + 1);
  330. }
  331. static u32 get_ipg_per_clk(void)
  332. {
  333. u32 reg, perclk_podf;
  334. reg = __raw_readl(&imx_ccm->cscmr1);
  335. if (is_mx6sll() || is_mx6sl() || is_mx6sx() ||
  336. is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
  337. if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
  338. return MXC_HCLK; /* OSC 24Mhz */
  339. }
  340. perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
  341. return get_ipg_clk() / (perclk_podf + 1);
  342. }
  343. static u32 get_uart_clk(void)
  344. {
  345. u32 reg, uart_podf;
  346. u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
  347. reg = __raw_readl(&imx_ccm->cscdr1);
  348. if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
  349. is_mx6sll() || is_mx6ull()) {
  350. if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
  351. freq = MXC_HCLK;
  352. }
  353. reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
  354. uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
  355. return freq / (uart_podf + 1);
  356. }
  357. static u32 get_cspi_clk(void)
  358. {
  359. u32 reg, cspi_podf;
  360. reg = __raw_readl(&imx_ccm->cscdr2);
  361. cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
  362. MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
  363. if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
  364. is_mx6sll() || is_mx6ull()) {
  365. if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
  366. return MXC_HCLK / (cspi_podf + 1);
  367. }
  368. return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
  369. }
  370. static u32 get_axi_clk(void)
  371. {
  372. u32 root_freq, axi_podf;
  373. u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
  374. axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
  375. axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
  376. if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
  377. if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
  378. root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
  379. else
  380. root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
  381. } else
  382. root_freq = get_periph_clk();
  383. return root_freq / (axi_podf + 1);
  384. }
  385. static u32 get_emi_slow_clk(void)
  386. {
  387. u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
  388. cscmr1 = __raw_readl(&imx_ccm->cscmr1);
  389. emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
  390. emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
  391. emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
  392. emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
  393. switch (emi_clk_sel) {
  394. case 0:
  395. root_freq = get_axi_clk();
  396. break;
  397. case 1:
  398. root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
  399. break;
  400. case 2:
  401. root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
  402. break;
  403. case 3:
  404. root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
  405. break;
  406. }
  407. return root_freq / (emi_slow_podf + 1);
  408. }
  409. static u32 get_mmdc_ch0_clk(void)
  410. {
  411. u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
  412. u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
  413. u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
  414. if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() ||
  415. is_mx6sll()) {
  416. podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
  417. MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
  418. if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
  419. per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
  420. MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
  421. if (is_mx6sl()) {
  422. if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
  423. freq = MXC_HCLK;
  424. else
  425. freq = decode_pll(PLL_USBOTG, MXC_HCLK);
  426. } else {
  427. if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
  428. freq = decode_pll(PLL_BUS, MXC_HCLK);
  429. else
  430. freq = decode_pll(PLL_USBOTG, MXC_HCLK);
  431. }
  432. } else {
  433. per2_clk2_podf = 0;
  434. switch ((cbcmr &
  435. MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
  436. MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
  437. case 0:
  438. freq = decode_pll(PLL_BUS, MXC_HCLK);
  439. break;
  440. case 1:
  441. freq = mxc_get_pll_pfd(PLL_BUS, 2);
  442. break;
  443. case 2:
  444. freq = mxc_get_pll_pfd(PLL_BUS, 0);
  445. break;
  446. case 3:
  447. if (is_mx6sl()) {
  448. freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1;
  449. break;
  450. }
  451. pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
  452. switch (pmu_misc2_audio_div) {
  453. case 0:
  454. case 2:
  455. pmu_misc2_audio_div = 1;
  456. break;
  457. case 1:
  458. pmu_misc2_audio_div = 2;
  459. break;
  460. case 3:
  461. pmu_misc2_audio_div = 4;
  462. break;
  463. }
  464. freq = decode_pll(PLL_AUDIO, MXC_HCLK) /
  465. pmu_misc2_audio_div;
  466. break;
  467. }
  468. }
  469. return freq / (podf + 1) / (per2_clk2_podf + 1);
  470. } else {
  471. podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
  472. MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
  473. return get_periph_clk() / (podf + 1);
  474. }
  475. }
  476. #if defined(CONFIG_VIDEO_MXS)
  477. static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
  478. u32 post_div)
  479. {
  480. u32 reg = 0;
  481. ulong start;
  482. debug("pll5 div = %d, num = %d, denom = %d\n",
  483. pll_div, pll_num, pll_denom);
  484. /* Power up PLL5 video */
  485. writel(BM_ANADIG_PLL_VIDEO_POWERDOWN |
  486. BM_ANADIG_PLL_VIDEO_BYPASS |
  487. BM_ANADIG_PLL_VIDEO_DIV_SELECT |
  488. BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
  489. &imx_ccm->analog_pll_video_clr);
  490. /* Set div, num and denom */
  491. switch (post_div) {
  492. case 1:
  493. writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
  494. BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
  495. &imx_ccm->analog_pll_video_set);
  496. break;
  497. case 2:
  498. writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
  499. BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
  500. &imx_ccm->analog_pll_video_set);
  501. break;
  502. case 4:
  503. writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
  504. BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
  505. &imx_ccm->analog_pll_video_set);
  506. break;
  507. default:
  508. puts("Wrong test_div!\n");
  509. return -EINVAL;
  510. }
  511. writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num),
  512. &imx_ccm->analog_pll_video_num);
  513. writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom),
  514. &imx_ccm->analog_pll_video_denom);
  515. /* Wait PLL5 lock */
  516. start = get_timer(0); /* Get current timestamp */
  517. do {
  518. reg = readl(&imx_ccm->analog_pll_video);
  519. if (reg & BM_ANADIG_PLL_VIDEO_LOCK) {
  520. /* Enable PLL out */
  521. writel(BM_ANADIG_PLL_VIDEO_ENABLE,
  522. &imx_ccm->analog_pll_video_set);
  523. return 0;
  524. }
  525. } while (get_timer(0) < (start + 10)); /* Wait 10ms */
  526. puts("Lock PLL5 timeout\n");
  527. return -ETIME;
  528. }
  529. /*
  530. * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
  531. *
  532. * 'freq' using KHz as unit, see driver/video/mxsfb.c.
  533. */
  534. void mxs_set_lcdclk(u32 base_addr, u32 freq)
  535. {
  536. u32 reg = 0;
  537. u32 hck = MXC_HCLK / 1000;
  538. /* DIV_SELECT ranges from 27 to 54 */
  539. u32 min = hck * 27;
  540. u32 max = hck * 54;
  541. u32 temp, best = 0;
  542. u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1;
  543. u32 pll_div, pll_num, pll_denom, post_div = 1;
  544. debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
  545. if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() &&
  546. !is_mx6sll()) {
  547. debug("This chip not support lcd!\n");
  548. return;
  549. }
  550. if (!is_mx6sl()) {
  551. if (base_addr == LCDIF1_BASE_ADDR) {
  552. reg = readl(&imx_ccm->cscdr2);
  553. /* Can't change clocks when clock not from pre-mux */
  554. if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
  555. return;
  556. }
  557. }
  558. if (is_mx6sx()) {
  559. reg = readl(&imx_ccm->cscdr2);
  560. /* Can't change clocks when clock not from pre-mux */
  561. if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
  562. return;
  563. }
  564. temp = freq * max_pred * max_postd;
  565. if (temp < min) {
  566. /*
  567. * Register: PLL_VIDEO
  568. * Bit Field: POST_DIV_SELECT
  569. * 00 — Divide by 4.
  570. * 01 — Divide by 2.
  571. * 10 — Divide by 1.
  572. * 11 — Reserved
  573. * No need to check post_div(1)
  574. */
  575. for (post_div = 2; post_div <= 4; post_div <<= 1) {
  576. if ((temp * post_div) > min) {
  577. freq *= post_div;
  578. break;
  579. }
  580. }
  581. if (post_div > 4) {
  582. printf("Fail to set rate to %dkhz", freq);
  583. return;
  584. }
  585. }
  586. /* Choose the best pred and postd to match freq for lcd */
  587. for (i = 1; i <= max_pred; i++) {
  588. for (j = 1; j <= max_postd; j++) {
  589. temp = freq * i * j;
  590. if (temp > max || temp < min)
  591. continue;
  592. if (best == 0 || temp < best) {
  593. best = temp;
  594. pred = i;
  595. postd = j;
  596. }
  597. }
  598. }
  599. if (best == 0) {
  600. printf("Fail to set rate to %dKHz", freq);
  601. return;
  602. }
  603. debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
  604. pll_div = best / hck;
  605. pll_denom = 1000000;
  606. pll_num = (best - hck * pll_div) * pll_denom / hck;
  607. /*
  608. * pll_num
  609. * (24MHz * (pll_div + --------- ))
  610. * pll_denom
  611. *freq KHz = --------------------------------
  612. * post_div * pred * postd * 1000
  613. */
  614. if (base_addr == LCDIF1_BASE_ADDR) {
  615. if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
  616. return;
  617. enable_lcdif_clock(base_addr, 0);
  618. if (!is_mx6sl()) {
  619. /* Select pre-lcd clock to PLL5 and set pre divider */
  620. clrsetbits_le32(&imx_ccm->cscdr2,
  621. MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
  622. MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
  623. (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
  624. ((pred - 1) <<
  625. MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
  626. /* Set the post divider */
  627. clrsetbits_le32(&imx_ccm->cbcmr,
  628. MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
  629. ((postd - 1) <<
  630. MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
  631. } else {
  632. /* Select pre-lcd clock to PLL5 and set pre divider */
  633. clrsetbits_le32(&imx_ccm->cscdr2,
  634. MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK |
  635. MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK,
  636. (0x2 << MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET) |
  637. ((pred - 1) <<
  638. MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET));
  639. /* Set the post divider */
  640. clrsetbits_le32(&imx_ccm->cscmr1,
  641. MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK,
  642. (((postd - 1)^0x6) <<
  643. MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET));
  644. }
  645. enable_lcdif_clock(base_addr, 1);
  646. } else if (is_mx6sx()) {
  647. /* Setting LCDIF2 for i.MX6SX */
  648. if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
  649. return;
  650. enable_lcdif_clock(base_addr, 0);
  651. /* Select pre-lcd clock to PLL5 and set pre divider */
  652. clrsetbits_le32(&imx_ccm->cscdr2,
  653. MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
  654. MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK,
  655. (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) |
  656. ((pred - 1) <<
  657. MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET));
  658. /* Set the post divider */
  659. clrsetbits_le32(&imx_ccm->cscmr1,
  660. MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
  661. ((postd - 1) <<
  662. MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
  663. enable_lcdif_clock(base_addr, 1);
  664. }
  665. }
  666. int enable_lcdif_clock(u32 base_addr, bool enable)
  667. {
  668. u32 reg = 0;
  669. u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
  670. if (is_mx6sx()) {
  671. if ((base_addr != LCDIF1_BASE_ADDR) &&
  672. (base_addr != LCDIF2_BASE_ADDR)) {
  673. puts("Wrong LCD interface!\n");
  674. return -EINVAL;
  675. }
  676. /* Set to pre-mux clock at default */
  677. lcdif_clk_sel_mask = (base_addr == LCDIF2_BASE_ADDR) ?
  678. MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK :
  679. MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
  680. lcdif_ccgr3_mask = (base_addr == LCDIF2_BASE_ADDR) ?
  681. (MXC_CCM_CCGR3_LCDIF2_PIX_MASK |
  682. MXC_CCM_CCGR3_DISP_AXI_MASK) :
  683. (MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
  684. MXC_CCM_CCGR3_DISP_AXI_MASK);
  685. } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
  686. if (base_addr != LCDIF1_BASE_ADDR) {
  687. puts("Wrong LCD interface!\n");
  688. return -EINVAL;
  689. }
  690. /* Set to pre-mux clock at default */
  691. lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
  692. lcdif_ccgr3_mask = MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
  693. } else if (is_mx6sl()) {
  694. if (base_addr != LCDIF1_BASE_ADDR) {
  695. puts("Wrong LCD interface!\n");
  696. return -EINVAL;
  697. }
  698. reg = readl(&imx_ccm->CCGR3);
  699. reg &= ~(MXC_CCM_CCGR3_LCDIF_AXI_MASK |
  700. MXC_CCM_CCGR3_LCDIF_PIX_MASK);
  701. writel(reg, &imx_ccm->CCGR3);
  702. if (enable) {
  703. reg = readl(&imx_ccm->cscdr3);
  704. reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK;
  705. reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET;
  706. writel(reg, &imx_ccm->cscdr3);
  707. reg = readl(&imx_ccm->CCGR3);
  708. reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK |
  709. MXC_CCM_CCGR3_LCDIF_PIX_MASK;
  710. writel(reg, &imx_ccm->CCGR3);
  711. }
  712. return 0;
  713. } else {
  714. return 0;
  715. }
  716. /* Gate LCDIF clock first */
  717. reg = readl(&imx_ccm->CCGR3);
  718. reg &= ~lcdif_ccgr3_mask;
  719. writel(reg, &imx_ccm->CCGR3);
  720. reg = readl(&imx_ccm->CCGR2);
  721. reg &= ~MXC_CCM_CCGR2_LCD_MASK;
  722. writel(reg, &imx_ccm->CCGR2);
  723. if (enable) {
  724. /* Select pre-mux */
  725. reg = readl(&imx_ccm->cscdr2);
  726. reg &= ~lcdif_clk_sel_mask;
  727. writel(reg, &imx_ccm->cscdr2);
  728. /* Enable the LCDIF pix clock */
  729. reg = readl(&imx_ccm->CCGR3);
  730. reg |= lcdif_ccgr3_mask;
  731. writel(reg, &imx_ccm->CCGR3);
  732. reg = readl(&imx_ccm->CCGR2);
  733. reg |= MXC_CCM_CCGR2_LCD_MASK;
  734. writel(reg, &imx_ccm->CCGR2);
  735. }
  736. return 0;
  737. }
  738. #endif
  739. #ifdef CONFIG_FSL_QSPI
  740. /* qspi_num can be from 0 - 1 */
  741. void enable_qspi_clk(int qspi_num)
  742. {
  743. u32 reg = 0;
  744. /* Enable QuadSPI clock */
  745. switch (qspi_num) {
  746. case 0:
  747. /* disable the clock gate */
  748. clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
  749. /* set 50M : (50 = 396 / 2 / 4) */
  750. reg = readl(&imx_ccm->cscmr1);
  751. reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
  752. MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
  753. reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
  754. (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
  755. writel(reg, &imx_ccm->cscmr1);
  756. /* enable the clock gate */
  757. setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
  758. break;
  759. case 1:
  760. /*
  761. * disable the clock gate
  762. * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
  763. * disable both of them.
  764. */
  765. clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
  766. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
  767. /* set 50M : (50 = 396 / 2 / 4) */
  768. reg = readl(&imx_ccm->cs2cdr);
  769. reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
  770. MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
  771. MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
  772. reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
  773. MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
  774. writel(reg, &imx_ccm->cs2cdr);
  775. /*enable the clock gate*/
  776. setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
  777. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
  778. break;
  779. default:
  780. break;
  781. }
  782. }
  783. #endif
  784. #ifdef CONFIG_FEC_MXC
  785. int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
  786. {
  787. u32 reg = 0;
  788. s32 timeout = 100000;
  789. struct anatop_regs __iomem *anatop =
  790. (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
  791. if (freq < ENET_25MHZ || freq > ENET_125MHZ)
  792. return -EINVAL;
  793. reg = readl(&anatop->pll_enet);
  794. if (fec_id == 0) {
  795. reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
  796. reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
  797. } else if (fec_id == 1) {
  798. /* Only i.MX6SX/UL support ENET2 */
  799. if (!(is_mx6sx() || is_mx6ul() || is_mx6ull()))
  800. return -EINVAL;
  801. reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
  802. reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
  803. } else {
  804. return -EINVAL;
  805. }
  806. if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
  807. (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
  808. reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
  809. writel(reg, &anatop->pll_enet);
  810. while (timeout--) {
  811. if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
  812. break;
  813. }
  814. if (timeout < 0)
  815. return -ETIMEDOUT;
  816. }
  817. /* Enable FEC clock */
  818. if (fec_id == 0)
  819. reg |= BM_ANADIG_PLL_ENET_ENABLE;
  820. else
  821. reg |= BM_ANADIG_PLL_ENET2_ENABLE;
  822. reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
  823. writel(reg, &anatop->pll_enet);
  824. #ifdef CONFIG_MX6SX
  825. /* Disable enet system clcok before switching clock parent */
  826. reg = readl(&imx_ccm->CCGR3);
  827. reg &= ~MXC_CCM_CCGR3_ENET_MASK;
  828. writel(reg, &imx_ccm->CCGR3);
  829. /*
  830. * Set enet ahb clock to 200MHz
  831. * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
  832. */
  833. reg = readl(&imx_ccm->chsccdr);
  834. reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
  835. | MXC_CCM_CHSCCDR_ENET_PODF_MASK
  836. | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
  837. /* PLL2 PFD2 */
  838. reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
  839. /* Div = 2*/
  840. reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
  841. reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
  842. writel(reg, &imx_ccm->chsccdr);
  843. /* Enable enet system clock */
  844. reg = readl(&imx_ccm->CCGR3);
  845. reg |= MXC_CCM_CCGR3_ENET_MASK;
  846. writel(reg, &imx_ccm->CCGR3);
  847. #endif
  848. return 0;
  849. }
  850. #endif
  851. static u32 get_usdhc_clk(u32 port)
  852. {
  853. u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
  854. u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
  855. u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
  856. if (is_mx6ul() || is_mx6ull()) {
  857. if (port > 1)
  858. return 0;
  859. }
  860. if (is_mx6sll()) {
  861. if (port > 2)
  862. return 0;
  863. }
  864. switch (port) {
  865. case 0:
  866. usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
  867. MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
  868. clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
  869. break;
  870. case 1:
  871. usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
  872. MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
  873. clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
  874. break;
  875. case 2:
  876. usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
  877. MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
  878. clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
  879. break;
  880. case 3:
  881. usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
  882. MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
  883. clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
  884. break;
  885. default:
  886. break;
  887. }
  888. if (clk_sel)
  889. root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
  890. else
  891. root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
  892. return root_freq / (usdhc_podf + 1);
  893. }
  894. u32 imx_get_uartclk(void)
  895. {
  896. return get_uart_clk();
  897. }
  898. u32 imx_get_fecclk(void)
  899. {
  900. return mxc_get_clock(MXC_IPG_CLK);
  901. }
  902. #if defined(CONFIG_SATA) || defined(CONFIG_PCIE_IMX)
  903. static int enable_enet_pll(uint32_t en)
  904. {
  905. struct mxc_ccm_reg *const imx_ccm
  906. = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
  907. s32 timeout = 100000;
  908. u32 reg = 0;
  909. /* Enable PLLs */
  910. reg = readl(&imx_ccm->analog_pll_enet);
  911. reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
  912. writel(reg, &imx_ccm->analog_pll_enet);
  913. reg |= BM_ANADIG_PLL_SYS_ENABLE;
  914. while (timeout--) {
  915. if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
  916. break;
  917. }
  918. if (timeout <= 0)
  919. return -EIO;
  920. reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
  921. writel(reg, &imx_ccm->analog_pll_enet);
  922. reg |= en;
  923. writel(reg, &imx_ccm->analog_pll_enet);
  924. return 0;
  925. }
  926. #endif
  927. #ifdef CONFIG_SATA
  928. static void ungate_sata_clock(void)
  929. {
  930. struct mxc_ccm_reg *const imx_ccm =
  931. (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  932. /* Enable SATA clock. */
  933. setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
  934. }
  935. int enable_sata_clock(void)
  936. {
  937. ungate_sata_clock();
  938. return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
  939. }
  940. void disable_sata_clock(void)
  941. {
  942. struct mxc_ccm_reg *const imx_ccm =
  943. (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  944. clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
  945. }
  946. #endif
  947. #ifdef CONFIG_PCIE_IMX
  948. static void ungate_pcie_clock(void)
  949. {
  950. struct mxc_ccm_reg *const imx_ccm =
  951. (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  952. /* Enable PCIe clock. */
  953. setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
  954. }
  955. int enable_pcie_clock(void)
  956. {
  957. struct anatop_regs *anatop_regs =
  958. (struct anatop_regs *)ANATOP_BASE_ADDR;
  959. struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  960. u32 lvds1_clk_sel;
  961. /*
  962. * Here be dragons!
  963. *
  964. * The register ANATOP_MISC1 is not documented in the Freescale
  965. * MX6RM. The register that is mapped in the ANATOP space and
  966. * marked as ANATOP_MISC1 is actually documented in the PMU section
  967. * of the datasheet as PMU_MISC1.
  968. *
  969. * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
  970. * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
  971. * for PCI express link that is clocked from the i.MX6.
  972. */
  973. #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
  974. #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
  975. #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
  976. #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
  977. #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
  978. if (is_mx6sx())
  979. lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
  980. else
  981. lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
  982. clrsetbits_le32(&anatop_regs->ana_misc1,
  983. ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
  984. ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
  985. ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
  986. /* PCIe reference clock sourced from AXI. */
  987. clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
  988. /* Party time! Ungate the clock to the PCIe. */
  989. #ifdef CONFIG_SATA
  990. ungate_sata_clock();
  991. #endif
  992. ungate_pcie_clock();
  993. return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
  994. BM_ANADIG_PLL_ENET_ENABLE_PCIE);
  995. }
  996. #endif
  997. #ifdef CONFIG_IMX_HAB
  998. void hab_caam_clock_enable(unsigned char enable)
  999. {
  1000. u32 reg;
  1001. if (is_mx6ull() || is_mx6sll()) {
  1002. /* CG5, DCP clock */
  1003. reg = __raw_readl(&imx_ccm->CCGR0);
  1004. if (enable)
  1005. reg |= MXC_CCM_CCGR0_DCP_CLK_MASK;
  1006. else
  1007. reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK;
  1008. __raw_writel(reg, &imx_ccm->CCGR0);
  1009. } else {
  1010. /* CG4 ~ CG6, CAAM clocks */
  1011. reg = __raw_readl(&imx_ccm->CCGR0);
  1012. if (enable)
  1013. reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
  1014. MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
  1015. MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
  1016. else
  1017. reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
  1018. MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
  1019. MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
  1020. __raw_writel(reg, &imx_ccm->CCGR0);
  1021. }
  1022. /* EMI slow clk */
  1023. reg = __raw_readl(&imx_ccm->CCGR6);
  1024. if (enable)
  1025. reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
  1026. else
  1027. reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
  1028. __raw_writel(reg, &imx_ccm->CCGR6);
  1029. }
  1030. #endif
  1031. static void enable_pll3(void)
  1032. {
  1033. struct anatop_regs __iomem *anatop =
  1034. (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
  1035. /* make sure pll3 is enabled */
  1036. if ((readl(&anatop->usb1_pll_480_ctrl) &
  1037. BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
  1038. /* enable pll's power */
  1039. writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
  1040. &anatop->usb1_pll_480_ctrl_set);
  1041. writel(0x80, &anatop->ana_misc2_clr);
  1042. /* wait for pll lock */
  1043. while ((readl(&anatop->usb1_pll_480_ctrl) &
  1044. BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
  1045. ;
  1046. /* disable bypass */
  1047. writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
  1048. &anatop->usb1_pll_480_ctrl_clr);
  1049. /* enable pll output */
  1050. writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
  1051. &anatop->usb1_pll_480_ctrl_set);
  1052. }
  1053. }
  1054. void enable_thermal_clk(void)
  1055. {
  1056. enable_pll3();
  1057. }
  1058. #ifdef CONFIG_MTD_NOR_FLASH
  1059. void enable_eim_clk(unsigned char enable)
  1060. {
  1061. u32 reg;
  1062. reg = __raw_readl(&imx_ccm->CCGR6);
  1063. if (enable)
  1064. reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
  1065. else
  1066. reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
  1067. __raw_writel(reg, &imx_ccm->CCGR6);
  1068. }
  1069. #endif
  1070. unsigned int mxc_get_clock(enum mxc_clock clk)
  1071. {
  1072. switch (clk) {
  1073. case MXC_ARM_CLK:
  1074. return get_mcu_main_clk();
  1075. case MXC_PER_CLK:
  1076. return get_periph_clk();
  1077. case MXC_AHB_CLK:
  1078. return get_ahb_clk();
  1079. case MXC_IPG_CLK:
  1080. return get_ipg_clk();
  1081. case MXC_IPG_PERCLK:
  1082. case MXC_I2C_CLK:
  1083. return get_ipg_per_clk();
  1084. case MXC_UART_CLK:
  1085. return get_uart_clk();
  1086. case MXC_CSPI_CLK:
  1087. return get_cspi_clk();
  1088. case MXC_AXI_CLK:
  1089. return get_axi_clk();
  1090. case MXC_EMI_SLOW_CLK:
  1091. return get_emi_slow_clk();
  1092. case MXC_DDR_CLK:
  1093. return get_mmdc_ch0_clk();
  1094. case MXC_ESDHC_CLK:
  1095. return get_usdhc_clk(0);
  1096. case MXC_ESDHC2_CLK:
  1097. return get_usdhc_clk(1);
  1098. case MXC_ESDHC3_CLK:
  1099. return get_usdhc_clk(2);
  1100. case MXC_ESDHC4_CLK:
  1101. return get_usdhc_clk(3);
  1102. case MXC_SATA_CLK:
  1103. return get_ahb_clk();
  1104. default:
  1105. printf("Unsupported MXC CLK: %d\n", clk);
  1106. break;
  1107. }
  1108. return 0;
  1109. }
  1110. #ifndef CONFIG_MX6SX
  1111. void enable_ipu_clock(void)
  1112. {
  1113. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  1114. int reg;
  1115. reg = readl(&mxc_ccm->CCGR3);
  1116. reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
  1117. writel(reg, &mxc_ccm->CCGR3);
  1118. if (is_mx6dqp()) {
  1119. setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
  1120. setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
  1121. }
  1122. }
  1123. #endif
  1124. #ifndef CONFIG_SPL_BUILD
  1125. /*
  1126. * Dump some core clockes.
  1127. */
  1128. int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  1129. {
  1130. u32 freq;
  1131. freq = decode_pll(PLL_SYS, MXC_HCLK);
  1132. printf("PLL_SYS %8d MHz\n", freq / 1000000);
  1133. freq = decode_pll(PLL_BUS, MXC_HCLK);
  1134. printf("PLL_BUS %8d MHz\n", freq / 1000000);
  1135. freq = decode_pll(PLL_USBOTG, MXC_HCLK);
  1136. printf("PLL_OTG %8d MHz\n", freq / 1000000);
  1137. freq = decode_pll(PLL_ENET, MXC_HCLK);
  1138. printf("PLL_NET %8d MHz\n", freq / 1000000);
  1139. printf("\n");
  1140. printf("ARM %8d kHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000);
  1141. printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
  1142. printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
  1143. #ifdef CONFIG_MXC_SPI
  1144. printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
  1145. #endif
  1146. printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
  1147. printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
  1148. printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
  1149. printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
  1150. printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
  1151. printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
  1152. printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
  1153. printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
  1154. printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
  1155. return 0;
  1156. }
  1157. #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \
  1158. defined(CONFIG_MX6S)
  1159. static void disable_ldb_di_clock_sources(void)
  1160. {
  1161. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  1162. int reg;
  1163. /* Make sure PFDs are disabled at boot. */
  1164. reg = readl(&mxc_ccm->analog_pfd_528);
  1165. /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
  1166. if (is_mx6sdl())
  1167. reg |= 0x80008080;
  1168. else
  1169. reg |= 0x80808080;
  1170. writel(reg, &mxc_ccm->analog_pfd_528);
  1171. /* Disable PLL3 PFDs */
  1172. reg = readl(&mxc_ccm->analog_pfd_480);
  1173. reg |= 0x80808080;
  1174. writel(reg, &mxc_ccm->analog_pfd_480);
  1175. /* Disable PLL5 */
  1176. reg = readl(&mxc_ccm->analog_pll_video);
  1177. reg &= ~(1 << 13);
  1178. writel(reg, &mxc_ccm->analog_pll_video);
  1179. }
  1180. static void enable_ldb_di_clock_sources(void)
  1181. {
  1182. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  1183. int reg;
  1184. reg = readl(&mxc_ccm->analog_pfd_528);
  1185. if (is_mx6sdl())
  1186. reg &= ~(0x80008080);
  1187. else
  1188. reg &= ~(0x80808080);
  1189. writel(reg, &mxc_ccm->analog_pfd_528);
  1190. reg = readl(&mxc_ccm->analog_pfd_480);
  1191. reg &= ~(0x80808080);
  1192. writel(reg, &mxc_ccm->analog_pfd_480);
  1193. }
  1194. /*
  1195. * Try call this function as early in the boot process as possible since the
  1196. * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5.
  1197. */
  1198. void select_ldb_di_clock_source(enum ldb_di_clock clk)
  1199. {
  1200. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  1201. int reg;
  1202. /*
  1203. * Need to follow a strict procedure when changing the LDB
  1204. * clock, else we can introduce a glitch. Things to keep in
  1205. * mind:
  1206. * 1. The current and new parent clocks must be disabled.
  1207. * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
  1208. * no CG bit.
  1209. * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
  1210. * the top four options are in one mux and the PLL3 option along
  1211. * with another option is in the second mux. There is third mux
  1212. * used to decide between the first and second mux.
  1213. * The code below switches the parent to the bottom mux first
  1214. * and then manipulates the top mux. This ensures that no glitch
  1215. * will enter the divider.
  1216. *
  1217. * Need to disable MMDC_CH1 clock manually as there is no CG bit
  1218. * for this clock. The only way to disable this clock is to move
  1219. * it to pll3_sw_clk and then to disable pll3_sw_clk
  1220. * Make sure periph2_clk2_sel is set to pll3_sw_clk
  1221. */
  1222. /* Disable all ldb_di clock parents */
  1223. disable_ldb_di_clock_sources();
  1224. /* Set MMDC_CH1 mask bit */
  1225. reg = readl(&mxc_ccm->ccdr);
  1226. reg |= MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
  1227. writel(reg, &mxc_ccm->ccdr);
  1228. /* Set periph2_clk2_sel to be sourced from PLL3_sw_clk */
  1229. reg = readl(&mxc_ccm->cbcmr);
  1230. reg &= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL;
  1231. writel(reg, &mxc_ccm->cbcmr);
  1232. /*
  1233. * Set the periph2_clk_sel to the top mux so that
  1234. * mmdc_ch1 is from pll3_sw_clk.
  1235. */
  1236. reg = readl(&mxc_ccm->cbcdr);
  1237. reg |= MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
  1238. writel(reg, &mxc_ccm->cbcdr);
  1239. /* Wait for the clock switch */
  1240. while (readl(&mxc_ccm->cdhipr))
  1241. ;
  1242. /* Disable pll3_sw_clk by selecting bypass clock source */
  1243. reg = readl(&mxc_ccm->ccsr);
  1244. reg |= MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
  1245. writel(reg, &mxc_ccm->ccsr);
  1246. /* Set the ldb_di0_clk and ldb_di1_clk to 111b */
  1247. reg = readl(&mxc_ccm->cs2cdr);
  1248. reg |= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
  1249. | (7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
  1250. writel(reg, &mxc_ccm->cs2cdr);
  1251. /* Set the ldb_di0_clk and ldb_di1_clk to 100b */
  1252. reg = readl(&mxc_ccm->cs2cdr);
  1253. reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
  1254. | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
  1255. reg |= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
  1256. | (4 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
  1257. writel(reg, &mxc_ccm->cs2cdr);
  1258. /* Set the ldb_di0_clk and ldb_di1_clk to desired source */
  1259. reg = readl(&mxc_ccm->cs2cdr);
  1260. reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
  1261. | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
  1262. reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
  1263. | (clk << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
  1264. writel(reg, &mxc_ccm->cs2cdr);
  1265. /* Unbypass pll3_sw_clk */
  1266. reg = readl(&mxc_ccm->ccsr);
  1267. reg &= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
  1268. writel(reg, &mxc_ccm->ccsr);
  1269. /*
  1270. * Set the periph2_clk_sel back to the bottom mux so that
  1271. * mmdc_ch1 is from its original parent.
  1272. */
  1273. reg = readl(&mxc_ccm->cbcdr);
  1274. reg &= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
  1275. writel(reg, &mxc_ccm->cbcdr);
  1276. /* Wait for the clock switch */
  1277. while (readl(&mxc_ccm->cdhipr))
  1278. ;
  1279. /* Clear MMDC_CH1 mask bit */
  1280. reg = readl(&mxc_ccm->ccdr);
  1281. reg &= ~MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
  1282. writel(reg, &mxc_ccm->ccdr);
  1283. enable_ldb_di_clock_sources();
  1284. }
  1285. #endif
  1286. /***************************************************/
  1287. U_BOOT_CMD(
  1288. clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
  1289. "display clocks",
  1290. ""
  1291. );
  1292. #endif