soc.c 7.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017 NXP
  4. *
  5. * Peng Fan <peng.fan@nxp.com>
  6. */
  7. #include <common.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/mach-imx/hab.h>
  13. #include <asm/mach-imx/boot_mode.h>
  14. #include <asm/mach-imx/syscounter.h>
  15. #include <asm/armv8/mmu.h>
  16. #include <dm/uclass.h>
  17. #include <errno.h>
  18. #include <fdt_support.h>
  19. #include <fsl_wdog.h>
  20. #include <imx_sip.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. #if defined(CONFIG_IMX_HAB)
  23. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  24. .bank = 1,
  25. .word = 3,
  26. };
  27. #endif
  28. int timer_init(void)
  29. {
  30. #ifdef CONFIG_SPL_BUILD
  31. struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
  32. unsigned long freq = readl(&sctr->cntfid0);
  33. /* Update with accurate clock frequency */
  34. asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
  35. clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
  36. SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
  37. #endif
  38. gd->arch.tbl = 0;
  39. gd->arch.tbu = 0;
  40. return 0;
  41. }
  42. void enable_tzc380(void)
  43. {
  44. struct iomuxc_gpr_base_regs *gpr =
  45. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  46. /* Enable TZASC and lock setting */
  47. setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
  48. setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
  49. if (IS_ENABLED(CONFIG_IMX8MM))
  50. setbits_le32(&gpr->gpr[10], BIT(1));
  51. /*
  52. * set Region 0 attribute to allow secure and non-secure
  53. * read/write permission. Found some masters like usb dwc3
  54. * controllers can't work with secure memory.
  55. */
  56. writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
  57. }
  58. void set_wdog_reset(struct wdog_regs *wdog)
  59. {
  60. /*
  61. * Output WDOG_B signal to reset external pmic or POR_B decided by
  62. * the board design. Without external reset, the peripherals/DDR/
  63. * PMIC are not reset, that may cause system working abnormal.
  64. * WDZST bit is write-once only bit. Align this bit in kernel,
  65. * otherwise kernel code will have no chance to set this bit.
  66. */
  67. setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
  68. }
  69. static struct mm_region imx8m_mem_map[] = {
  70. {
  71. /* ROM */
  72. .virt = 0x0UL,
  73. .phys = 0x0UL,
  74. .size = 0x100000UL,
  75. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  76. PTE_BLOCK_OUTER_SHARE
  77. }, {
  78. /* CAAM */
  79. .virt = 0x100000UL,
  80. .phys = 0x100000UL,
  81. .size = 0x8000UL,
  82. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  83. PTE_BLOCK_NON_SHARE |
  84. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  85. }, {
  86. /* TCM */
  87. .virt = 0x7C0000UL,
  88. .phys = 0x7C0000UL,
  89. .size = 0x80000UL,
  90. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  91. PTE_BLOCK_NON_SHARE |
  92. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  93. }, {
  94. /* OCRAM */
  95. .virt = 0x900000UL,
  96. .phys = 0x900000UL,
  97. .size = 0x200000UL,
  98. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  99. PTE_BLOCK_OUTER_SHARE
  100. }, {
  101. /* AIPS */
  102. .virt = 0xB00000UL,
  103. .phys = 0xB00000UL,
  104. .size = 0x3f500000UL,
  105. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  106. PTE_BLOCK_NON_SHARE |
  107. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  108. }, {
  109. /* DRAM1 */
  110. .virt = 0x40000000UL,
  111. .phys = 0x40000000UL,
  112. .size = PHYS_SDRAM_SIZE,
  113. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  114. PTE_BLOCK_OUTER_SHARE
  115. #ifdef PHYS_SDRAM_2_SIZE
  116. }, {
  117. /* DRAM2 */
  118. .virt = 0x100000000UL,
  119. .phys = 0x100000000UL,
  120. .size = PHYS_SDRAM_2_SIZE,
  121. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  122. PTE_BLOCK_OUTER_SHARE
  123. #endif
  124. }, {
  125. /* List terminator */
  126. 0,
  127. }
  128. };
  129. struct mm_region *mem_map = imx8m_mem_map;
  130. void enable_caches(void)
  131. {
  132. /*
  133. * If OPTEE runs, remove OPTEE memory from MMU table to
  134. * avoid speculative prefetch. OPTEE runs at the top of
  135. * the first memory bank
  136. */
  137. if (rom_pointer[1])
  138. imx8m_mem_map[5].size -= rom_pointer[1];
  139. icache_enable();
  140. dcache_enable();
  141. }
  142. static u32 get_cpu_variant_type(u32 type)
  143. {
  144. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  145. struct fuse_bank *bank = &ocotp->bank[1];
  146. struct fuse_bank1_regs *fuse =
  147. (struct fuse_bank1_regs *)bank->fuse_regs;
  148. u32 value = readl(&fuse->tester4);
  149. if (type == MXC_CPU_IMX8MM) {
  150. switch (value & 0x3) {
  151. case 2:
  152. if (value & 0x1c0000)
  153. return MXC_CPU_IMX8MMDL;
  154. else
  155. return MXC_CPU_IMX8MMD;
  156. case 3:
  157. if (value & 0x1c0000)
  158. return MXC_CPU_IMX8MMSL;
  159. else
  160. return MXC_CPU_IMX8MMS;
  161. default:
  162. if (value & 0x1c0000)
  163. return MXC_CPU_IMX8MML;
  164. break;
  165. }
  166. }
  167. return type;
  168. }
  169. u32 get_cpu_rev(void)
  170. {
  171. struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  172. u32 reg = readl(&ana_pll->digprog);
  173. u32 type = (reg >> 16) & 0xff;
  174. u32 major_low = (reg >> 8) & 0xff;
  175. u32 rom_version;
  176. reg &= 0xff;
  177. /* i.MX8MM */
  178. if (major_low == 0x41) {
  179. type = get_cpu_variant_type(MXC_CPU_IMX8MM);
  180. } else {
  181. if (reg == CHIP_REV_1_0) {
  182. /*
  183. * For B0 chip, the DIGPROG is not updated, still TO1.0.
  184. * we have to check ROM version further
  185. */
  186. rom_version = readl((void __iomem *)ROM_VERSION_A0);
  187. if (rom_version != CHIP_REV_1_0) {
  188. rom_version = readl((void __iomem *)ROM_VERSION_B0);
  189. if (rom_version >= CHIP_REV_2_0)
  190. reg = CHIP_REV_2_0;
  191. }
  192. }
  193. }
  194. return (type << 12) | reg;
  195. }
  196. static void imx_set_wdog_powerdown(bool enable)
  197. {
  198. struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
  199. struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
  200. struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
  201. /* Write to the PDE (Power Down Enable) bit */
  202. writew(enable, &wdog1->wmcr);
  203. writew(enable, &wdog2->wmcr);
  204. writew(enable, &wdog3->wmcr);
  205. }
  206. int arch_cpu_init_dm(void)
  207. {
  208. struct udevice *dev;
  209. int ret;
  210. ret = uclass_get_device_by_name(UCLASS_CLK,
  211. "clock-controller@30380000",
  212. &dev);
  213. if (ret < 0) {
  214. printf("Failed to find clock node. Check device tree\n");
  215. return ret;
  216. }
  217. return 0;
  218. }
  219. int arch_cpu_init(void)
  220. {
  221. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  222. /*
  223. * ROM might disable clock for SCTR,
  224. * enable the clock before timer_init.
  225. */
  226. if (IS_ENABLED(CONFIG_SPL_BUILD))
  227. clock_enable(CCGR_SCTR, 1);
  228. /*
  229. * Init timer at very early state, because sscg pll setting
  230. * will use it
  231. */
  232. timer_init();
  233. if (IS_ENABLED(CONFIG_SPL_BUILD)) {
  234. clock_init();
  235. imx_set_wdog_powerdown(false);
  236. }
  237. if (is_imx8mq()) {
  238. clock_enable(CCGR_OCOTP, 1);
  239. if (readl(&ocotp->ctrl) & 0x200)
  240. writel(0x200, &ocotp->ctrl_clr);
  241. }
  242. return 0;
  243. }
  244. bool is_usb_boot(void)
  245. {
  246. return get_boot_device() == USB_BOOT;
  247. }
  248. #ifdef CONFIG_OF_SYSTEM_SETUP
  249. int ft_system_setup(void *blob, bd_t *bd)
  250. {
  251. int i = 0;
  252. int rc;
  253. int nodeoff;
  254. /* Disable the CPU idle for A0 chip since the HW does not support it */
  255. if (is_soc_rev(CHIP_REV_1_0)) {
  256. static const char * const nodes_path[] = {
  257. "/cpus/cpu@0",
  258. "/cpus/cpu@1",
  259. "/cpus/cpu@2",
  260. "/cpus/cpu@3",
  261. };
  262. for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
  263. nodeoff = fdt_path_offset(blob, nodes_path[i]);
  264. if (nodeoff < 0)
  265. continue; /* Not found, skip it */
  266. printf("Found %s node\n", nodes_path[i]);
  267. rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
  268. if (rc) {
  269. printf("Unable to update property %s:%s, err=%s\n",
  270. nodes_path[i], "status", fdt_strerror(rc));
  271. return rc;
  272. }
  273. printf("Remove %s:%s\n", nodes_path[i],
  274. "cpu-idle-states");
  275. }
  276. }
  277. return 0;
  278. }
  279. #endif
  280. #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYSRESET)
  281. void reset_cpu(ulong addr)
  282. {
  283. struct watchdog_regs *wdog = (struct watchdog_regs *)addr;
  284. if (!addr)
  285. wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
  286. /* Clear WDA to trigger WDOG_B immediately */
  287. writew((WCR_WDE | WCR_SRS), &wdog->wcr);
  288. while (1) {
  289. /*
  290. * spin for .5 seconds before reset
  291. */
  292. }
  293. }
  294. #endif