clock.h 7.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor, Inc.
  4. *
  5. * Author:
  6. * Peng Fan <Peng.Fan@freescale.com>
  7. */
  8. #ifndef _ASM_ARCH_CLOCK_H
  9. #define _ASM_ARCH_CLOCK_H
  10. #include <common.h>
  11. #include <asm/arch/crm_regs.h>
  12. #ifdef CONFIG_SYS_MX7_HCLK
  13. #define MXC_HCLK CONFIG_SYS_MX7_HCLK
  14. #else
  15. #define MXC_HCLK 24000000
  16. #endif
  17. #ifdef CONFIG_SYS_MX7_CLK32
  18. #define MXC_CLK32 CONFIG_SYS_MX7_CLK32
  19. #else
  20. #define MXC_CLK32 32768
  21. #endif
  22. /* Mainly for compatible to imx common code. */
  23. enum mxc_clock {
  24. MXC_ARM_CLK = 0,
  25. MXC_AHB_CLK,
  26. MXC_IPG_CLK,
  27. MXC_UART_CLK,
  28. MXC_CSPI_CLK,
  29. MXC_AXI_CLK,
  30. MXC_DDR_CLK,
  31. MXC_ESDHC_CLK,
  32. MXC_ESDHC2_CLK,
  33. MXC_ESDHC3_CLK,
  34. MXC_I2C_CLK,
  35. };
  36. /* PLL supported by i.mx7d */
  37. enum pll_clocks {
  38. PLL_CORE, /* Core PLL */
  39. PLL_SYS, /* System PLL*/
  40. PLL_ENET, /* Enet PLL */
  41. PLL_AUDIO, /* Audio PLL */
  42. PLL_VIDEO, /* Video PLL*/
  43. PLL_DDR, /* Dram PLL */
  44. PLL_USB, /* USB PLL, fixed at 480MHZ */
  45. };
  46. /* clk src for clock root gen */
  47. enum clk_root_src {
  48. OSC_24M_CLK,
  49. PLL_ARM_MAIN_800M_CLK,
  50. PLL_SYS_MAIN_480M_CLK,
  51. PLL_SYS_MAIN_240M_CLK,
  52. PLL_SYS_MAIN_120M_CLK,
  53. PLL_SYS_PFD0_392M_CLK,
  54. PLL_SYS_PFD0_196M_CLK,
  55. PLL_SYS_PFD1_332M_CLK,
  56. PLL_SYS_PFD1_166M_CLK,
  57. PLL_SYS_PFD2_270M_CLK,
  58. PLL_SYS_PFD2_135M_CLK,
  59. PLL_SYS_PFD3_CLK,
  60. PLL_SYS_PFD4_CLK,
  61. PLL_SYS_PFD5_CLK,
  62. PLL_SYS_PFD6_CLK,
  63. PLL_SYS_PFD7_CLK,
  64. PLL_ENET_MAIN_500M_CLK,
  65. PLL_ENET_MAIN_250M_CLK,
  66. PLL_ENET_MAIN_125M_CLK,
  67. PLL_ENET_MAIN_100M_CLK,
  68. PLL_ENET_MAIN_50M_CLK,
  69. PLL_ENET_MAIN_40M_CLK,
  70. PLL_ENET_MAIN_25M_CLK,
  71. PLL_DRAM_MAIN_1066M_CLK,
  72. PLL_DRAM_MAIN_533M_CLK,
  73. PLL_AUDIO_MAIN_CLK,
  74. PLL_VIDEO_MAIN_CLK,
  75. PLL_USB_MAIN_480M_CLK, /* fixed at 480MHZ */
  76. EXT_CLK_1,
  77. EXT_CLK_2,
  78. EXT_CLK_3,
  79. EXT_CLK_4,
  80. REF_1M_CLK,
  81. OSC_32K_CLK,
  82. };
  83. /*
  84. * Clock root index
  85. */
  86. enum clk_root_index {
  87. ARM_A7_CLK_ROOT = 0,
  88. ARM_M4_CLK_ROOT = 1,
  89. ARM_M0_CLK_ROOT = 2,
  90. MAIN_AXI_CLK_ROOT = 16,
  91. DISP_AXI_CLK_ROOT = 17,
  92. ENET_AXI_CLK_ROOT = 18,
  93. NAND_USDHC_BUS_CLK_ROOT = 19,
  94. AHB_CLK_ROOT = 32,
  95. DRAM_PHYM_CLK_ROOT = 48,
  96. DRAM_CLK_ROOT = 49,
  97. DRAM_PHYM_ALT_CLK_ROOT = 64,
  98. DRAM_ALT_CLK_ROOT = 65,
  99. USB_HSIC_CLK_ROOT = 66,
  100. PCIE_CTRL_CLK_ROOT = 67,
  101. PCIE_PHY_CLK_ROOT = 68,
  102. EPDC_PIXEL_CLK_ROOT = 69,
  103. LCDIF_PIXEL_CLK_ROOT = 70,
  104. MIPI_DSI_EXTSER_CLK_ROOT = 71,
  105. MIPI_CSI_WARP_CLK_ROOT = 72,
  106. MIPI_DPHY_REF_CLK_ROOT = 73,
  107. SAI1_CLK_ROOT = 74,
  108. SAI2_CLK_ROOT = 75,
  109. SAI3_CLK_ROOT = 76,
  110. SPDIF_CLK_ROOT = 77,
  111. ENET1_REF_CLK_ROOT = 78,
  112. ENET1_TIME_CLK_ROOT = 79,
  113. ENET2_REF_CLK_ROOT = 80,
  114. ENET2_TIME_CLK_ROOT = 81,
  115. ENET_PHY_REF_CLK_ROOT = 82,
  116. EIM_CLK_ROOT = 83,
  117. NAND_CLK_ROOT = 84,
  118. QSPI_CLK_ROOT = 85,
  119. USDHC1_CLK_ROOT = 86,
  120. USDHC2_CLK_ROOT = 87,
  121. USDHC3_CLK_ROOT = 88,
  122. CAN1_CLK_ROOT = 89,
  123. CAN2_CLK_ROOT = 90,
  124. I2C1_CLK_ROOT = 91,
  125. I2C2_CLK_ROOT = 92,
  126. I2C3_CLK_ROOT = 93,
  127. I2C4_CLK_ROOT = 94,
  128. UART1_CLK_ROOT = 95,
  129. UART2_CLK_ROOT = 96,
  130. UART3_CLK_ROOT = 97,
  131. UART4_CLK_ROOT = 98,
  132. UART5_CLK_ROOT = 99,
  133. UART6_CLK_ROOT = 100,
  134. UART7_CLK_ROOT = 101,
  135. ECSPI1_CLK_ROOT = 102,
  136. ECSPI2_CLK_ROOT = 103,
  137. ECSPI3_CLK_ROOT = 104,
  138. ECSPI4_CLK_ROOT = 105,
  139. PWM1_CLK_ROOT = 106,
  140. PWM2_CLK_ROOT = 107,
  141. PWM3_CLK_ROOT = 108,
  142. PWM4_CLK_ROOT = 109,
  143. FLEXTIMER1_CLK_ROOT = 110,
  144. FLEXTIMER2_CLK_ROOT = 111,
  145. SIM1_CLK_ROOT = 112,
  146. SIM2_CLK_ROOT = 113,
  147. GPT1_CLK_ROOT = 114,
  148. GPT2_CLK_ROOT = 115,
  149. GPT3_CLK_ROOT = 116,
  150. GPT4_CLK_ROOT = 117,
  151. TRACE_CLK_ROOT = 118,
  152. WDOG_CLK_ROOT = 119,
  153. CSI_MCLK_CLK_ROOT = 120,
  154. AUDIO_MCLK_CLK_ROOT = 121,
  155. WRCLK_CLK_ROOT = 122,
  156. IPP_DO_CLKO1 = 123,
  157. IPP_DO_CLKO2 = 124,
  158. CLK_ROOT_MAX,
  159. };
  160. #if (CONFIG_CONS_INDEX == 0)
  161. #define UART_CLK_ROOT UART1_CLK_ROOT
  162. #elif (CONFIG_CONS_INDEX == 1)
  163. #define UART_CLK_ROOT UART2_CLK_ROOT
  164. #elif (CONFIG_CONS_INDEX == 2)
  165. #define UART_CLK_ROOT UART3_CLK_ROOT
  166. #elif (CONFIG_CONS_INDEX == 3)
  167. #define UART_CLK_ROOT UART4_CLK_ROOT
  168. #elif (CONFIG_CONS_INDEX == 4)
  169. #define UART_CLK_ROOT UART5_CLK_ROOT
  170. #elif (CONFIG_CONS_INDEX == 5)
  171. #define UART_CLK_ROOT UART6_CLK_ROOT
  172. #elif (CONFIG_CONS_INDEX == 6)
  173. #define UART_CLK_ROOT UART7_CLK_ROOT
  174. #else
  175. #error "Invalid IMX UART ID for serial console is defined"
  176. #endif
  177. struct clk_root_setting {
  178. enum clk_root_index root;
  179. u32 setting;
  180. };
  181. /*
  182. * CCGR mapping
  183. */
  184. enum clk_ccgr_index {
  185. CCGR_CPU = 0,
  186. CCGR_M4 = 1,
  187. CCGR_SIM_MAIN = 4,
  188. CCGR_SIM_DISPLAY = 5,
  189. CCGR_SIM_ENET = 6,
  190. CCGR_SIM_M = 7,
  191. CCGR_SIM_S = 8,
  192. CCGR_SIM_WAKEUP = 9,
  193. CCGR_IPMUX1 = 10,
  194. CCGR_IPMUX2 = 11,
  195. CCGR_IPMUX3 = 12,
  196. CCGR_ROM = 16,
  197. CCGR_OCRAM = 17,
  198. CCGR_OCRAM_S = 18,
  199. CCGR_DRAM = 19,
  200. CCGR_RAWNAND = 20,
  201. CCGR_QSPI = 21,
  202. CCGR_WEIM = 22,
  203. CCGR_ADC = 32,
  204. CCGR_ANATOP = 33,
  205. CCGR_SCTR = 34,
  206. CCGR_OCOTP = 35,
  207. CCGR_CAAM = 36,
  208. CCGR_SNVS = 37,
  209. CCGR_RDC = 38,
  210. CCGR_MU = 39,
  211. CCGR_HS = 40,
  212. CCGR_DVFS = 41,
  213. CCGR_QOS = 42,
  214. CCGR_QOS_DISPMIX = 43,
  215. CCGR_QOS_MEGAMIX = 44,
  216. CCGR_CSU = 45,
  217. CCGR_DBGMON = 46,
  218. CCGR_DEBUG = 47,
  219. CCGR_TRACE = 48,
  220. CCGR_SEC_DEBUG = 49,
  221. CCGR_SEMA1 = 64,
  222. CCGR_SEMA2 = 65,
  223. CCGR_PERFMON1 = 68,
  224. CCGR_PERFMON2 = 69,
  225. CCGR_SDMA = 72,
  226. CCGR_CSI = 73,
  227. CCGR_EPDC = 74,
  228. CCGR_LCDIF = 75,
  229. CCGR_PXP = 76,
  230. CCGR_PCIE = 96,
  231. CCGR_MIPI_CSI = 100,
  232. CCGR_MIPI_DSI = 101,
  233. CCGR_MIPI_MEM_PHY = 102,
  234. CCGR_USB_CTRL = 104,
  235. CCGR_USB_HSIC = 105,
  236. CCGR_USB_PHY1 = 106,
  237. CCGR_USB_PHY2 = 107,
  238. CCGR_USDHC1 = 108,
  239. CCGR_USDHC2 = 109,
  240. CCGR_USDHC3 = 110,
  241. CCGR_ENET1 = 112,
  242. CCGR_ENET2 = 113,
  243. CCGR_CAN1 = 116,
  244. CCGR_CAN2 = 117,
  245. CCGR_ECSPI1 = 120,
  246. CCGR_ECSPI2 = 121,
  247. CCGR_ECSPI3 = 122,
  248. CCGR_ECSPI4 = 123,
  249. CCGR_GPT1 = 124,
  250. CCGR_GPT2 = 125,
  251. CCGR_GPT3 = 126,
  252. CCGR_GPT4 = 127,
  253. CCGR_FTM1 = 128,
  254. CCGR_FTM2 = 129,
  255. CCGR_PWM1 = 132,
  256. CCGR_PWM2 = 133,
  257. CCGR_PWM3 = 134,
  258. CCGR_PWM4 = 135,
  259. CCGR_I2C1 = 136,
  260. CCGR_I2C2 = 137,
  261. CCGR_I2C3 = 138,
  262. CCGR_I2C4 = 139,
  263. CCGR_SAI1 = 140,
  264. CCGR_SAI2 = 141,
  265. CCGR_SAI3 = 142,
  266. CCGR_SIM1 = 144,
  267. CCGR_SIM2 = 145,
  268. CCGR_UART1 = 148,
  269. CCGR_UART2 = 149,
  270. CCGR_UART3 = 150,
  271. CCGR_UART4 = 151,
  272. CCGR_UART5 = 152,
  273. CCGR_UART6 = 153,
  274. CCGR_UART7 = 154,
  275. CCGR_WDOG1 = 156,
  276. CCGR_WDOG2 = 157,
  277. CCGR_WDOG3 = 158,
  278. CCGR_WDOG4 = 159,
  279. CCGR_GPIO1 = 160,
  280. CCGR_GPIO2 = 161,
  281. CCGR_GPIO3 = 162,
  282. CCGR_GPIO4 = 163,
  283. CCGR_GPIO5 = 164,
  284. CCGR_GPIO6 = 165,
  285. CCGR_GPIO7 = 166,
  286. CCGR_IOMUX = 168,
  287. CCGR_IOMUX_LPSR = 169,
  288. CCGR_KPP = 170,
  289. CCGR_SKIP,
  290. CCGR_MAX,
  291. };
  292. /* Clock root channel */
  293. enum clk_root_type {
  294. CCM_CORE_CHANNEL,
  295. CCM_BUS_CHANNEL,
  296. CCM_AHB_CHANNEL,
  297. CCM_DRAM_PHYM_CHANNEL,
  298. CCM_DRAM_CHANNEL,
  299. CCM_IP_CHANNEL,
  300. };
  301. #include <asm/arch/clock_slice.h>
  302. /*
  303. * entry: the clock root index
  304. * type: ccm channel
  305. * src_mux: each entry corresponding to the clock src, detailed info in CCM RM
  306. */
  307. struct clk_root_map {
  308. enum clk_root_index entry;
  309. enum clk_root_type type;
  310. uint8_t src_mux[8];
  311. };
  312. enum enet_freq {
  313. ENET_25MHZ,
  314. ENET_50MHZ,
  315. ENET_125MHZ,
  316. };
  317. u32 get_root_clk(enum clk_root_index clock_id);
  318. u32 mxc_get_clock(enum mxc_clock clk);
  319. u32 imx_get_uartclk(void);
  320. u32 imx_get_fecclk(void);
  321. void clock_init(void);
  322. #ifdef CONFIG_SYS_I2C_MXC
  323. int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
  324. #endif
  325. #ifdef CONFIG_FEC_MXC
  326. int set_clk_enet(enum enet_freq type);
  327. #endif
  328. int set_clk_qspi(void);
  329. int set_clk_nand(void);
  330. #ifdef CONFIG_MXC_OCOTP
  331. void enable_ocotp_clk(unsigned char enable);
  332. #endif
  333. void enable_usboh3_clk(unsigned char enable);
  334. #ifdef CONFIG_IMX_HAB
  335. void hab_caam_clock_enable(unsigned char enable);
  336. #endif
  337. void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq);
  338. void enable_thermal_clk(void);
  339. #endif