ahci.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006.
  4. * Author: Jason Jin<Jason.jin@freescale.com>
  5. * Zhang Wei<wei.zhang@freescale.com>
  6. *
  7. * with the reference on libata and ahci drvier in kernel
  8. *
  9. * This driver provides a SCSI interface to SATA.
  10. */
  11. #include <common.h>
  12. #include <blk.h>
  13. #include <cpu_func.h>
  14. #include <log.h>
  15. #include <linux/bitops.h>
  16. #include <linux/delay.h>
  17. #include <command.h>
  18. #include <dm.h>
  19. #include <pci.h>
  20. #include <asm/processor.h>
  21. #include <linux/errno.h>
  22. #include <asm/io.h>
  23. #include <malloc.h>
  24. #include <memalign.h>
  25. #include <pci.h>
  26. #include <scsi.h>
  27. #include <libata.h>
  28. #include <linux/ctype.h>
  29. #include <ahci.h>
  30. #include <dm/device-internal.h>
  31. #include <dm/lists.h>
  32. static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);
  33. #ifndef CONFIG_DM_SCSI
  34. struct ahci_uc_priv *probe_ent = NULL;
  35. #endif
  36. #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
  37. /*
  38. * Some controllers limit number of blocks they can read/write at once.
  39. * Contemporary SSD devices work much faster if the read/write size is aligned
  40. * to a power of 2. Let's set default to 128 and allowing to be overwritten if
  41. * needed.
  42. */
  43. #ifndef MAX_SATA_BLOCKS_READ_WRITE
  44. #define MAX_SATA_BLOCKS_READ_WRITE 0x80
  45. #endif
  46. /* Maximum timeouts for each event */
  47. #define WAIT_MS_SPINUP 20000
  48. #define WAIT_MS_DATAIO 10000
  49. #define WAIT_MS_FLUSH 5000
  50. #define WAIT_MS_LINKUP 200
  51. #define AHCI_CAP_S64A BIT(31)
  52. __weak void __iomem *ahci_port_base(void __iomem *base, u32 port)
  53. {
  54. return base + 0x100 + (port * 0x80);
  55. }
  56. #define msleep(a) udelay(a * 1000)
  57. static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
  58. {
  59. const unsigned long start = begin;
  60. const unsigned long end = start + len;
  61. debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
  62. flush_dcache_range(start, end);
  63. }
  64. /*
  65. * SATA controller DMAs to physical RAM. Ensure data from the
  66. * controller is invalidated from dcache; next access comes from
  67. * physical RAM.
  68. */
  69. static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
  70. {
  71. const unsigned long start = begin;
  72. const unsigned long end = start + len;
  73. debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
  74. invalidate_dcache_range(start, end);
  75. }
  76. /*
  77. * Ensure data for SATA controller is flushed out of dcache and
  78. * written to physical memory.
  79. */
  80. static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
  81. {
  82. ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
  83. AHCI_PORT_PRIV_DMA_SZ);
  84. }
  85. static int waiting_for_cmd_completed(void __iomem *offset,
  86. int timeout_msec,
  87. u32 sign)
  88. {
  89. int i;
  90. u32 status;
  91. for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
  92. msleep(1);
  93. return (i < timeout_msec) ? 0 : -1;
  94. }
  95. int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, int port)
  96. {
  97. u32 tmp;
  98. int j = 0;
  99. void __iomem *port_mmio = uc_priv->port[port].port_mmio;
  100. /*
  101. * Bring up SATA link.
  102. * SATA link bringup time is usually less than 1 ms; only very
  103. * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
  104. */
  105. while (j < WAIT_MS_LINKUP) {
  106. tmp = readl(port_mmio + PORT_SCR_STAT);
  107. tmp &= PORT_SCR_STAT_DET_MASK;
  108. if (tmp == PORT_SCR_STAT_DET_PHYRDY)
  109. return 0;
  110. udelay(1000);
  111. j++;
  112. }
  113. return 1;
  114. }
  115. #ifdef CONFIG_SUNXI_AHCI
  116. /* The sunxi AHCI controller requires this undocumented setup */
  117. static void sunxi_dma_init(void __iomem *port_mmio)
  118. {
  119. clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
  120. }
  121. #endif
  122. int ahci_reset(void __iomem *base)
  123. {
  124. int i = 1000;
  125. u32 __iomem *host_ctl_reg = base + HOST_CTL;
  126. u32 tmp = readl(host_ctl_reg); /* global controller reset */
  127. if ((tmp & HOST_RESET) == 0)
  128. writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
  129. /*
  130. * reset must complete within 1 second, or
  131. * the hardware should be considered fried.
  132. */
  133. do {
  134. udelay(1000);
  135. tmp = readl(host_ctl_reg);
  136. i--;
  137. } while ((i > 0) && (tmp & HOST_RESET));
  138. if (i == 0) {
  139. printf("controller reset failed (0x%x)\n", tmp);
  140. return -1;
  141. }
  142. return 0;
  143. }
  144. static int ahci_host_init(struct ahci_uc_priv *uc_priv)
  145. {
  146. #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
  147. struct udevice *dev = uc_priv->dev;
  148. struct pci_child_plat *pplat = dev_get_parent_plat(dev);
  149. u16 tmp16;
  150. #endif
  151. void __iomem *mmio = uc_priv->mmio_base;
  152. u32 tmp, cap_save, cmd;
  153. int i, j, ret;
  154. void __iomem *port_mmio;
  155. u32 port_map;
  156. debug("ahci_host_init: start\n");
  157. cap_save = readl(mmio + HOST_CAP);
  158. cap_save &= ((1 << 28) | (1 << 17));
  159. cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
  160. ret = ahci_reset(uc_priv->mmio_base);
  161. if (ret)
  162. return ret;
  163. writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
  164. writel(cap_save, mmio + HOST_CAP);
  165. writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
  166. #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
  167. if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
  168. u16 tmp16;
  169. dm_pci_read_config16(dev, 0x92, &tmp16);
  170. dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
  171. }
  172. #endif
  173. uc_priv->cap = readl(mmio + HOST_CAP);
  174. uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);
  175. port_map = uc_priv->port_map;
  176. uc_priv->n_ports = (uc_priv->cap & 0x1f) + 1;
  177. debug("cap 0x%x port_map 0x%x n_ports %d\n",
  178. uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
  179. #if !defined(CONFIG_DM_SCSI)
  180. if (uc_priv->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
  181. uc_priv->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
  182. #endif
  183. for (i = 0; i < uc_priv->n_ports; i++) {
  184. if (!(port_map & (1 << i)))
  185. continue;
  186. uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);
  187. port_mmio = (u8 *)uc_priv->port[i].port_mmio;
  188. /* make sure port is not active */
  189. tmp = readl(port_mmio + PORT_CMD);
  190. if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
  191. PORT_CMD_FIS_RX | PORT_CMD_START)) {
  192. debug("Port %d is active. Deactivating.\n", i);
  193. tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
  194. PORT_CMD_FIS_RX | PORT_CMD_START);
  195. writel_with_flush(tmp, port_mmio + PORT_CMD);
  196. /* spec says 500 msecs for each bit, so
  197. * this is slightly incorrect.
  198. */
  199. msleep(500);
  200. }
  201. #ifdef CONFIG_SUNXI_AHCI
  202. sunxi_dma_init(port_mmio);
  203. #endif
  204. /* Add the spinup command to whatever mode bits may
  205. * already be on in the command register.
  206. */
  207. cmd = readl(port_mmio + PORT_CMD);
  208. cmd |= PORT_CMD_SPIN_UP;
  209. writel_with_flush(cmd, port_mmio + PORT_CMD);
  210. /* Bring up SATA link. */
  211. ret = ahci_link_up(uc_priv, i);
  212. if (ret) {
  213. printf("SATA link %d timeout.\n", i);
  214. continue;
  215. } else {
  216. debug("SATA link ok.\n");
  217. }
  218. /* Clear error status */
  219. tmp = readl(port_mmio + PORT_SCR_ERR);
  220. if (tmp)
  221. writel(tmp, port_mmio + PORT_SCR_ERR);
  222. debug("Spinning up device on SATA port %d... ", i);
  223. j = 0;
  224. while (j < WAIT_MS_SPINUP) {
  225. tmp = readl(port_mmio + PORT_TFDATA);
  226. if (!(tmp & (ATA_BUSY | ATA_DRQ)))
  227. break;
  228. udelay(1000);
  229. tmp = readl(port_mmio + PORT_SCR_STAT);
  230. tmp &= PORT_SCR_STAT_DET_MASK;
  231. if (tmp == PORT_SCR_STAT_DET_PHYRDY)
  232. break;
  233. j++;
  234. }
  235. tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
  236. if (tmp == PORT_SCR_STAT_DET_COMINIT) {
  237. debug("SATA link %d down (COMINIT received), retrying...\n", i);
  238. i--;
  239. continue;
  240. }
  241. printf("Target spinup took %d ms.\n", j);
  242. if (j == WAIT_MS_SPINUP)
  243. debug("timeout.\n");
  244. else
  245. debug("ok.\n");
  246. tmp = readl(port_mmio + PORT_SCR_ERR);
  247. debug("PORT_SCR_ERR 0x%x\n", tmp);
  248. writel(tmp, port_mmio + PORT_SCR_ERR);
  249. /* ack any pending irq events for this port */
  250. tmp = readl(port_mmio + PORT_IRQ_STAT);
  251. debug("PORT_IRQ_STAT 0x%x\n", tmp);
  252. if (tmp)
  253. writel(tmp, port_mmio + PORT_IRQ_STAT);
  254. writel(1 << i, mmio + HOST_IRQ_STAT);
  255. /* register linkup ports */
  256. tmp = readl(port_mmio + PORT_SCR_STAT);
  257. debug("SATA port %d status: 0x%x\n", i, tmp);
  258. if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
  259. uc_priv->link_port_map |= (0x01 << i);
  260. }
  261. tmp = readl(mmio + HOST_CTL);
  262. debug("HOST_CTL 0x%x\n", tmp);
  263. writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
  264. tmp = readl(mmio + HOST_CTL);
  265. debug("HOST_CTL 0x%x\n", tmp);
  266. #if !defined(CONFIG_DM_SCSI)
  267. #ifndef CONFIG_SCSI_AHCI_PLAT
  268. dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
  269. tmp |= PCI_COMMAND_MASTER;
  270. dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
  271. #endif
  272. #endif
  273. return 0;
  274. }
  275. static void ahci_print_info(struct ahci_uc_priv *uc_priv)
  276. {
  277. #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
  278. struct udevice *dev = uc_priv->dev;
  279. u16 cc;
  280. #endif
  281. void __iomem *mmio = uc_priv->mmio_base;
  282. u32 vers, cap, cap2, impl, speed;
  283. const char *speed_s;
  284. const char *scc_s;
  285. vers = readl(mmio + HOST_VERSION);
  286. cap = uc_priv->cap;
  287. cap2 = readl(mmio + HOST_CAP2);
  288. impl = uc_priv->port_map;
  289. speed = (cap >> 20) & 0xf;
  290. if (speed == 1)
  291. speed_s = "1.5";
  292. else if (speed == 2)
  293. speed_s = "3";
  294. else if (speed == 3)
  295. speed_s = "6";
  296. else
  297. speed_s = "?";
  298. #if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
  299. scc_s = "SATA";
  300. #else
  301. dm_pci_read_config16(dev, 0x0a, &cc);
  302. if (cc == 0x0101)
  303. scc_s = "IDE";
  304. else if (cc == 0x0106)
  305. scc_s = "SATA";
  306. else if (cc == 0x0104)
  307. scc_s = "RAID";
  308. else
  309. scc_s = "unknown";
  310. #endif
  311. printf("AHCI %02x%02x.%02x%02x "
  312. "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
  313. (vers >> 24) & 0xff,
  314. (vers >> 16) & 0xff,
  315. (vers >> 8) & 0xff,
  316. vers & 0xff,
  317. ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
  318. printf("flags: "
  319. "%s%s%s%s%s%s%s"
  320. "%s%s%s%s%s%s%s"
  321. "%s%s%s%s%s%s\n",
  322. cap & (1 << 31) ? "64bit " : "",
  323. cap & (1 << 30) ? "ncq " : "",
  324. cap & (1 << 28) ? "ilck " : "",
  325. cap & (1 << 27) ? "stag " : "",
  326. cap & (1 << 26) ? "pm " : "",
  327. cap & (1 << 25) ? "led " : "",
  328. cap & (1 << 24) ? "clo " : "",
  329. cap & (1 << 19) ? "nz " : "",
  330. cap & (1 << 18) ? "only " : "",
  331. cap & (1 << 17) ? "pmp " : "",
  332. cap & (1 << 16) ? "fbss " : "",
  333. cap & (1 << 15) ? "pio " : "",
  334. cap & (1 << 14) ? "slum " : "",
  335. cap & (1 << 13) ? "part " : "",
  336. cap & (1 << 7) ? "ccc " : "",
  337. cap & (1 << 6) ? "ems " : "",
  338. cap & (1 << 5) ? "sxs " : "",
  339. cap2 & (1 << 2) ? "apst " : "",
  340. cap2 & (1 << 1) ? "nvmp " : "",
  341. cap2 & (1 << 0) ? "boh " : "");
  342. }
  343. #if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT)
  344. static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
  345. {
  346. #if !defined(CONFIG_DM_SCSI)
  347. u16 vendor;
  348. #endif
  349. int rc;
  350. uc_priv->dev = dev;
  351. uc_priv->host_flags = ATA_FLAG_SATA
  352. | ATA_FLAG_NO_LEGACY
  353. | ATA_FLAG_MMIO
  354. | ATA_FLAG_PIO_DMA
  355. | ATA_FLAG_NO_ATAPI;
  356. uc_priv->pio_mask = 0x1f;
  357. uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
  358. #if !defined(CONFIG_DM_SCSI)
  359. uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
  360. PCI_REGION_MEM);
  361. /* Take from kernel:
  362. * JMicron-specific fixup:
  363. * make sure we're in AHCI mode
  364. */
  365. dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
  366. if (vendor == 0x197b)
  367. dm_pci_write_config8(dev, 0x41, 0xa1);
  368. #else
  369. struct scsi_plat *plat = dev_get_uclass_plat(dev);
  370. uc_priv->mmio_base = (void *)plat->base;
  371. #endif
  372. debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base);
  373. /* initialize adapter */
  374. rc = ahci_host_init(uc_priv);
  375. if (rc)
  376. goto err_out;
  377. ahci_print_info(uc_priv);
  378. return 0;
  379. err_out:
  380. return rc;
  381. }
  382. #endif
  383. #define MAX_DATA_BYTE_COUNT (4*1024*1024)
  384. static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
  385. unsigned char *buf, int buf_len)
  386. {
  387. struct ahci_ioports *pp = &(uc_priv->port[port]);
  388. struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
  389. phys_addr_t pa = virt_to_phys(buf);
  390. u32 sg_count;
  391. int i;
  392. sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
  393. if (sg_count > AHCI_MAX_SG) {
  394. printf("Error:Too much sg!\n");
  395. return -1;
  396. }
  397. for (i = 0; i < sg_count; i++) {
  398. ahci_sg->addr = cpu_to_le32(lower_32_bits(pa));
  399. ahci_sg->addr_hi = cpu_to_le32(upper_32_bits(pa));
  400. if (ahci_sg->addr_hi && !(uc_priv->cap & AHCI_CAP_S64A)) {
  401. printf("Error: DMA address too high\n");
  402. return -1;
  403. }
  404. ahci_sg->flags_size = cpu_to_le32(0x3fffff &
  405. (buf_len < MAX_DATA_BYTE_COUNT ?
  406. (buf_len - 1) :
  407. (MAX_DATA_BYTE_COUNT - 1)));
  408. ahci_sg++;
  409. buf_len -= MAX_DATA_BYTE_COUNT;
  410. pa += MAX_DATA_BYTE_COUNT;
  411. }
  412. return sg_count;
  413. }
  414. static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
  415. {
  416. phys_addr_t pa = virt_to_phys((void *)pp->cmd_tbl);
  417. pp->cmd_slot->opts = cpu_to_le32(opts);
  418. pp->cmd_slot->status = 0;
  419. pp->cmd_slot->tbl_addr = cpu_to_le32(lower_32_bits(pa));
  420. #ifdef CONFIG_PHYS_64BIT
  421. pp->cmd_slot->tbl_addr_hi = cpu_to_le32(upper_32_bits(pa));
  422. #endif
  423. }
  424. static int wait_spinup(void __iomem *port_mmio)
  425. {
  426. ulong start;
  427. u32 tf_data;
  428. start = get_timer(0);
  429. do {
  430. tf_data = readl(port_mmio + PORT_TFDATA);
  431. if (!(tf_data & ATA_BUSY))
  432. return 0;
  433. } while (get_timer(start) < WAIT_MS_SPINUP);
  434. return -ETIMEDOUT;
  435. }
  436. static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
  437. {
  438. struct ahci_ioports *pp = &(uc_priv->port[port]);
  439. void __iomem *port_mmio = pp->port_mmio;
  440. u64 dma_addr;
  441. u32 port_status;
  442. void __iomem *mem;
  443. debug("Enter start port: %d\n", port);
  444. port_status = readl(port_mmio + PORT_SCR_STAT);
  445. debug("Port %d status: %x\n", port, port_status);
  446. if ((port_status & 0xf) != 0x03) {
  447. printf("No Link on this port!\n");
  448. return -1;
  449. }
  450. mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
  451. if (!mem) {
  452. free(pp);
  453. printf("%s: No mem for table!\n", __func__);
  454. return -ENOMEM;
  455. }
  456. memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
  457. /*
  458. * First item in chunk of DMA memory: 32-slot command table,
  459. * 32 bytes each in size
  460. */
  461. pp->cmd_slot =
  462. (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
  463. debug("cmd_slot = %p\n", pp->cmd_slot);
  464. mem += (AHCI_CMD_SLOT_SZ + 224);
  465. /*
  466. * Second item: Received-FIS area
  467. */
  468. pp->rx_fis = virt_to_phys((void *)mem);
  469. mem += AHCI_RX_FIS_SZ;
  470. /*
  471. * Third item: data area for storing a single command
  472. * and its scatter-gather table
  473. */
  474. pp->cmd_tbl = virt_to_phys((void *)mem);
  475. debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
  476. mem += AHCI_CMD_TBL_HDR;
  477. pp->cmd_tbl_sg =
  478. (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
  479. dma_addr = (ulong)pp->cmd_slot;
  480. writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR);
  481. writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI);
  482. dma_addr = (ulong)pp->rx_fis;
  483. writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR);
  484. writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI);
  485. #ifdef CONFIG_SUNXI_AHCI
  486. sunxi_dma_init(port_mmio);
  487. #endif
  488. writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
  489. PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
  490. PORT_CMD_START, port_mmio + PORT_CMD);
  491. debug("Exit start port %d\n", port);
  492. /*
  493. * Make sure interface is not busy based on error and status
  494. * information from task file data register before proceeding
  495. */
  496. return wait_spinup(port_mmio);
  497. }
  498. static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis,
  499. int fis_len, u8 *buf, int buf_len, u8 is_write)
  500. {
  501. struct ahci_ioports *pp = &(uc_priv->port[port]);
  502. void __iomem *port_mmio = pp->port_mmio;
  503. u32 opts;
  504. u32 port_status;
  505. int sg_count;
  506. debug("Enter %s: for port %d\n", __func__, port);
  507. if (port > uc_priv->n_ports) {
  508. printf("Invalid port number %d\n", port);
  509. return -1;
  510. }
  511. port_status = readl(port_mmio + PORT_SCR_STAT);
  512. if ((port_status & 0xf) != 0x03) {
  513. debug("No Link on port %d!\n", port);
  514. return -1;
  515. }
  516. memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
  517. sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
  518. opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
  519. ahci_fill_cmd_slot(pp, opts);
  520. ahci_dcache_flush_sata_cmd(pp);
  521. ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
  522. writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
  523. if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
  524. WAIT_MS_DATAIO, 0x1)) {
  525. printf("timeout exit!\n");
  526. return -1;
  527. }
  528. ahci_dcache_invalidate_range((unsigned long)buf,
  529. (unsigned long)buf_len);
  530. debug("%s: %d byte transferred.\n", __func__,
  531. le32_to_cpu(pp->cmd_slot->status));
  532. return 0;
  533. }
  534. static char *ata_id_strcpy(u16 *target, u16 *src, int len)
  535. {
  536. int i;
  537. for (i = 0; i < len / 2; i++)
  538. target[i] = swab16(src[i]);
  539. return (char *)target;
  540. }
  541. /*
  542. * SCSI INQUIRY command operation.
  543. */
  544. static int ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
  545. struct scsi_cmd *pccb)
  546. {
  547. static const u8 hdr[] = {
  548. 0,
  549. 0,
  550. 0x5, /* claim SPC-3 version compatibility */
  551. 2,
  552. 95 - 4,
  553. };
  554. u8 fis[20];
  555. u16 *idbuf;
  556. ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
  557. u8 port;
  558. /* Clean ccb data buffer */
  559. memset(pccb->pdata, 0, pccb->datalen);
  560. memcpy(pccb->pdata, hdr, sizeof(hdr));
  561. if (pccb->datalen <= 35)
  562. return 0;
  563. memset(fis, 0, sizeof(fis));
  564. /* Construct the FIS */
  565. fis[0] = 0x27; /* Host to device FIS. */
  566. fis[1] = 1 << 7; /* Command FIS. */
  567. fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
  568. /* Read id from sata */
  569. port = pccb->target;
  570. if (ahci_device_data_io(uc_priv, port, (u8 *)&fis, sizeof(fis),
  571. (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) {
  572. debug("scsi_ahci: SCSI inquiry command failure.\n");
  573. return -EIO;
  574. }
  575. if (!uc_priv->ataid[port]) {
  576. uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2);
  577. if (!uc_priv->ataid[port]) {
  578. printf("%s: No memory for ataid[port]\n", __func__);
  579. return -ENOMEM;
  580. }
  581. }
  582. idbuf = uc_priv->ataid[port];
  583. memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
  584. ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
  585. memcpy(&pccb->pdata[8], "ATA ", 8);
  586. ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
  587. ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
  588. #ifdef DEBUG
  589. ata_dump_id(idbuf);
  590. #endif
  591. return 0;
  592. }
  593. /*
  594. * SCSI READ10/WRITE10 command operation.
  595. */
  596. static int ata_scsiop_read_write(struct ahci_uc_priv *uc_priv,
  597. struct scsi_cmd *pccb, u8 is_write)
  598. {
  599. lbaint_t lba = 0;
  600. u16 blocks = 0;
  601. u8 fis[20];
  602. u8 *user_buffer = pccb->pdata;
  603. u32 user_buffer_size = pccb->datalen;
  604. /* Retrieve the base LBA number from the ccb structure. */
  605. if (pccb->cmd[0] == SCSI_READ16) {
  606. memcpy(&lba, pccb->cmd + 2, 8);
  607. lba = be64_to_cpu(lba);
  608. } else {
  609. u32 temp;
  610. memcpy(&temp, pccb->cmd + 2, 4);
  611. lba = be32_to_cpu(temp);
  612. }
  613. /*
  614. * Retrieve the base LBA number and the block count from
  615. * the ccb structure.
  616. *
  617. * For 10-byte and 16-byte SCSI R/W commands, transfer
  618. * length 0 means transfer 0 block of data.
  619. * However, for ATA R/W commands, sector count 0 means
  620. * 256 or 65536 sectors, not 0 sectors as in SCSI.
  621. *
  622. * WARNING: one or two older ATA drives treat 0 as 0...
  623. */
  624. if (pccb->cmd[0] == SCSI_READ16)
  625. blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
  626. else
  627. blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
  628. debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
  629. is_write ? "write" : "read", blocks, lba);
  630. /* Preset the FIS */
  631. memset(fis, 0, sizeof(fis));
  632. fis[0] = 0x27; /* Host to device FIS. */
  633. fis[1] = 1 << 7; /* Command FIS. */
  634. /* Command byte (read/write). */
  635. fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
  636. while (blocks) {
  637. u16 now_blocks; /* number of blocks per iteration */
  638. u32 transfer_size; /* number of bytes per iteration */
  639. now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
  640. transfer_size = ATA_SECT_SIZE * now_blocks;
  641. if (transfer_size > user_buffer_size) {
  642. printf("scsi_ahci: Error: buffer too small.\n");
  643. return -EIO;
  644. }
  645. /*
  646. * LBA48 SATA command but only use 32bit address range within
  647. * that (unless we've enabled 64bit LBA support). The next
  648. * smaller command range (28bit) is too small.
  649. */
  650. fis[4] = (lba >> 0) & 0xff;
  651. fis[5] = (lba >> 8) & 0xff;
  652. fis[6] = (lba >> 16) & 0xff;
  653. fis[7] = 1 << 6; /* device reg: set LBA mode */
  654. fis[8] = ((lba >> 24) & 0xff);
  655. #ifdef CONFIG_SYS_64BIT_LBA
  656. if (pccb->cmd[0] == SCSI_READ16) {
  657. fis[9] = ((lba >> 32) & 0xff);
  658. fis[10] = ((lba >> 40) & 0xff);
  659. }
  660. #endif
  661. fis[3] = 0xe0; /* features */
  662. /* Block (sector) count */
  663. fis[12] = (now_blocks >> 0) & 0xff;
  664. fis[13] = (now_blocks >> 8) & 0xff;
  665. /* Read/Write from ahci */
  666. if (ahci_device_data_io(uc_priv, pccb->target, (u8 *)&fis,
  667. sizeof(fis), user_buffer, transfer_size,
  668. is_write)) {
  669. debug("scsi_ahci: SCSI %s10 command failure.\n",
  670. is_write ? "WRITE" : "READ");
  671. return -EIO;
  672. }
  673. /* If this transaction is a write, do a following flush.
  674. * Writes in u-boot are so rare, and the logic to know when is
  675. * the last write and do a flush only there is sufficiently
  676. * difficult. Just do a flush after every write. This incurs,
  677. * usually, one extra flush when the rare writes do happen.
  678. */
  679. if (is_write) {
  680. if (-EIO == ata_io_flush(uc_priv, pccb->target))
  681. return -EIO;
  682. }
  683. user_buffer += transfer_size;
  684. user_buffer_size -= transfer_size;
  685. blocks -= now_blocks;
  686. lba += now_blocks;
  687. }
  688. return 0;
  689. }
  690. /*
  691. * SCSI READ CAPACITY10 command operation.
  692. */
  693. static int ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
  694. struct scsi_cmd *pccb)
  695. {
  696. u32 cap;
  697. u64 cap64;
  698. u32 block_size;
  699. if (!uc_priv->ataid[pccb->target]) {
  700. printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
  701. "\tNo ATA info!\n"
  702. "\tPlease run SCSI command INQUIRY first!\n");
  703. return -EPERM;
  704. }
  705. cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
  706. if (cap64 > 0x100000000ULL)
  707. cap64 = 0xffffffff;
  708. cap = cpu_to_be32(cap64);
  709. memcpy(pccb->pdata, &cap, sizeof(cap));
  710. block_size = cpu_to_be32((u32)512);
  711. memcpy(&pccb->pdata[4], &block_size, 4);
  712. return 0;
  713. }
  714. /*
  715. * SCSI READ CAPACITY16 command operation.
  716. */
  717. static int ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
  718. struct scsi_cmd *pccb)
  719. {
  720. u64 cap;
  721. u64 block_size;
  722. if (!uc_priv->ataid[pccb->target]) {
  723. printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
  724. "\tNo ATA info!\n"
  725. "\tPlease run SCSI command INQUIRY first!\n");
  726. return -EPERM;
  727. }
  728. cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
  729. cap = cpu_to_be64(cap);
  730. memcpy(pccb->pdata, &cap, sizeof(cap));
  731. block_size = cpu_to_be64((u64)512);
  732. memcpy(&pccb->pdata[8], &block_size, 8);
  733. return 0;
  734. }
  735. /*
  736. * SCSI TEST UNIT READY command operation.
  737. */
  738. static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
  739. struct scsi_cmd *pccb)
  740. {
  741. return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
  742. }
  743. static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
  744. {
  745. struct ahci_uc_priv *uc_priv;
  746. #ifdef CONFIG_DM_SCSI
  747. uc_priv = dev_get_uclass_priv(dev->parent);
  748. #else
  749. uc_priv = probe_ent;
  750. #endif
  751. int ret;
  752. switch (pccb->cmd[0]) {
  753. case SCSI_READ16:
  754. case SCSI_READ10:
  755. ret = ata_scsiop_read_write(uc_priv, pccb, 0);
  756. break;
  757. case SCSI_WRITE10:
  758. ret = ata_scsiop_read_write(uc_priv, pccb, 1);
  759. break;
  760. case SCSI_RD_CAPAC10:
  761. ret = ata_scsiop_read_capacity10(uc_priv, pccb);
  762. break;
  763. case SCSI_RD_CAPAC16:
  764. ret = ata_scsiop_read_capacity16(uc_priv, pccb);
  765. break;
  766. case SCSI_TST_U_RDY:
  767. ret = ata_scsiop_test_unit_ready(uc_priv, pccb);
  768. break;
  769. case SCSI_INQUIRY:
  770. ret = ata_scsiop_inquiry(uc_priv, pccb);
  771. break;
  772. default:
  773. printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
  774. return -ENOTSUPP;
  775. }
  776. if (ret) {
  777. debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
  778. return ret;
  779. }
  780. return 0;
  781. }
  782. static int ahci_start_ports(struct ahci_uc_priv *uc_priv)
  783. {
  784. u32 linkmap;
  785. int i;
  786. linkmap = uc_priv->link_port_map;
  787. for (i = 0; i < uc_priv->n_ports; i++) {
  788. if (((linkmap >> i) & 0x01)) {
  789. if (ahci_port_start(uc_priv, (u8) i)) {
  790. printf("Can not start port %d\n", i);
  791. continue;
  792. }
  793. }
  794. }
  795. return 0;
  796. }
  797. #ifndef CONFIG_DM_SCSI
  798. void scsi_low_level_init(int busdevfunc)
  799. {
  800. struct ahci_uc_priv *uc_priv;
  801. #ifndef CONFIG_SCSI_AHCI_PLAT
  802. probe_ent = calloc(1, sizeof(struct ahci_uc_priv));
  803. if (!probe_ent) {
  804. printf("%s: No memory for uc_priv\n", __func__);
  805. return;
  806. }
  807. uc_priv = probe_ent;
  808. struct udevice *dev;
  809. int ret;
  810. ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
  811. if (ret)
  812. return;
  813. ahci_init_one(uc_priv, dev);
  814. #else
  815. uc_priv = probe_ent;
  816. #endif
  817. ahci_start_ports(uc_priv);
  818. }
  819. #endif
  820. #ifndef CONFIG_SCSI_AHCI_PLAT
  821. int ahci_init_one_dm(struct udevice *dev)
  822. {
  823. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  824. return ahci_init_one(uc_priv, dev);
  825. }
  826. #endif
  827. int ahci_start_ports_dm(struct udevice *dev)
  828. {
  829. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  830. return ahci_start_ports(uc_priv);
  831. }
  832. #ifdef CONFIG_SCSI_AHCI_PLAT
  833. static int ahci_init_common(struct ahci_uc_priv *uc_priv, void __iomem *base)
  834. {
  835. int rc;
  836. uc_priv->host_flags = ATA_FLAG_SATA
  837. | ATA_FLAG_NO_LEGACY
  838. | ATA_FLAG_MMIO
  839. | ATA_FLAG_PIO_DMA
  840. | ATA_FLAG_NO_ATAPI;
  841. uc_priv->pio_mask = 0x1f;
  842. uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
  843. uc_priv->mmio_base = base;
  844. /* initialize adapter */
  845. rc = ahci_host_init(uc_priv);
  846. if (rc)
  847. goto err_out;
  848. ahci_print_info(uc_priv);
  849. rc = ahci_start_ports(uc_priv);
  850. err_out:
  851. return rc;
  852. }
  853. #ifndef CONFIG_DM_SCSI
  854. int ahci_init(void __iomem *base)
  855. {
  856. struct ahci_uc_priv *uc_priv;
  857. probe_ent = malloc(sizeof(struct ahci_uc_priv));
  858. if (!probe_ent) {
  859. printf("%s: No memory for uc_priv\n", __func__);
  860. return -ENOMEM;
  861. }
  862. uc_priv = probe_ent;
  863. memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
  864. return ahci_init_common(uc_priv, base);
  865. }
  866. #endif
  867. int ahci_init_dm(struct udevice *dev, void __iomem *base)
  868. {
  869. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  870. return ahci_init_common(uc_priv, base);
  871. }
  872. void __weak scsi_init(void)
  873. {
  874. }
  875. #endif /* CONFIG_SCSI_AHCI_PLAT */
  876. /*
  877. * In the general case of generic rotating media it makes sense to have a
  878. * flush capability. It probably even makes sense in the case of SSDs because
  879. * one cannot always know for sure what kind of internal cache/flush mechanism
  880. * is embodied therein. At first it was planned to invoke this after the last
  881. * write to disk and before rebooting. In practice, knowing, a priori, which
  882. * is the last write is difficult. Because writing to the disk in u-boot is
  883. * very rare, this flush command will be invoked after every block write.
  884. */
  885. static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port)
  886. {
  887. u8 fis[20];
  888. struct ahci_ioports *pp = &(uc_priv->port[port]);
  889. void __iomem *port_mmio = pp->port_mmio;
  890. u32 cmd_fis_len = 5; /* five dwords */
  891. /* Preset the FIS */
  892. memset(fis, 0, 20);
  893. fis[0] = 0x27; /* Host to device FIS. */
  894. fis[1] = 1 << 7; /* Command FIS. */
  895. fis[2] = ATA_CMD_FLUSH_EXT;
  896. memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
  897. ahci_fill_cmd_slot(pp, cmd_fis_len);
  898. ahci_dcache_flush_sata_cmd(pp);
  899. writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
  900. if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
  901. WAIT_MS_FLUSH, 0x1)) {
  902. debug("scsi_ahci: flush command timeout on port %d.\n", port);
  903. return -EIO;
  904. }
  905. return 0;
  906. }
  907. static int ahci_scsi_bus_reset(struct udevice *dev)
  908. {
  909. /* Not implemented */
  910. return 0;
  911. }
  912. #ifdef CONFIG_DM_SCSI
  913. int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp)
  914. {
  915. struct udevice *dev;
  916. int ret;
  917. ret = device_bind_driver(ahci_dev, "ahci_scsi", "ahci_scsi", &dev);
  918. if (ret)
  919. return ret;
  920. *devp = dev;
  921. return 0;
  922. }
  923. int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
  924. {
  925. struct ahci_uc_priv *uc_priv;
  926. struct scsi_plat *uc_plat;
  927. struct udevice *dev;
  928. int ret;
  929. device_find_first_child(ahci_dev, &dev);
  930. if (!dev)
  931. return -ENODEV;
  932. uc_plat = dev_get_uclass_plat(dev);
  933. uc_plat->base = base;
  934. uc_plat->max_lun = 1;
  935. uc_plat->max_id = 2;
  936. uc_priv = dev_get_uclass_priv(ahci_dev);
  937. ret = ahci_init_one(uc_priv, dev);
  938. if (ret)
  939. return ret;
  940. ret = ahci_start_ports(uc_priv);
  941. if (ret)
  942. return ret;
  943. /*
  944. * scsi_scan_dev() scans devices up-to the number of max_id.
  945. * Update max_id if the number of detected ports exceeds max_id.
  946. * This allows SCSI to scan all detected ports.
  947. */
  948. uc_plat->max_id = max_t(unsigned long, uc_priv->n_ports,
  949. uc_plat->max_id);
  950. /* If port count is less than max_id, update max_id */
  951. if (uc_priv->n_ports < uc_plat->max_id)
  952. uc_plat->max_id = uc_priv->n_ports;
  953. return 0;
  954. }
  955. int ahci_probe_scsi_pci(struct udevice *ahci_dev)
  956. {
  957. ulong base;
  958. u16 vendor, device;
  959. base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5,
  960. PCI_REGION_MEM);
  961. /*
  962. * Note:
  963. * Right now, we have only one quirk here, which is not enough to
  964. * introduce a new Kconfig option to select this. Once we have more
  965. * quirks in this AHCI code, we should add a Kconfig option for
  966. * this though.
  967. */
  968. dm_pci_read_config16(ahci_dev, PCI_VENDOR_ID, &vendor);
  969. dm_pci_read_config16(ahci_dev, PCI_DEVICE_ID, &device);
  970. if (vendor == PCI_VENDOR_ID_CAVIUM &&
  971. device == PCI_DEVICE_ID_CAVIUM_SATA)
  972. base = (uintptr_t)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_0,
  973. PCI_REGION_MEM);
  974. return ahci_probe_scsi(ahci_dev, base);
  975. }
  976. struct scsi_ops scsi_ops = {
  977. .exec = ahci_scsi_exec,
  978. .bus_reset = ahci_scsi_bus_reset,
  979. };
  980. U_BOOT_DRIVER(ahci_scsi) = {
  981. .name = "ahci_scsi",
  982. .id = UCLASS_SCSI,
  983. .ops = &scsi_ops,
  984. };
  985. #else
  986. int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
  987. {
  988. return ahci_scsi_exec(dev, pccb);
  989. }
  990. __weak int scsi_bus_reset(struct udevice *dev)
  991. {
  992. return ahci_scsi_bus_reset(dev);
  993. return 0;
  994. }
  995. #endif