controlcenterdc.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Stefan Roese <sr@denx.de>
  4. * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <dm.h>
  9. #include <init.h>
  10. #include <miiphy.h>
  11. #include <net.h>
  12. #include <tpm-v1.h>
  13. #include <asm/global_data.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/cpu.h>
  16. #include <asm-generic/gpio.h>
  17. #include <linux/delay.h>
  18. #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  19. #include "../arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h"
  20. #include "keyprogram.h"
  21. #include "dt_helpers.h"
  22. #include "hydra.h"
  23. #include "ihs_phys.h"
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #define DB_GP_88F68XX_GPP_OUT_ENA_LOW 0x7fffffff
  26. #define DB_GP_88F68XX_GPP_OUT_ENA_MID 0xffffefff
  27. #define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
  28. #define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x00001000
  29. #define DB_GP_88F68XX_GPP_POL_LOW 0x0
  30. #define DB_GP_88F68XX_GPP_POL_MID 0x0
  31. static int get_tpm(struct udevice **devp)
  32. {
  33. int rc;
  34. rc = uclass_first_device_err(UCLASS_TPM, devp);
  35. if (rc) {
  36. printf("Could not find TPM (ret=%d)\n", rc);
  37. return CMD_RET_FAILURE;
  38. }
  39. return 0;
  40. }
  41. /*
  42. * Define the DDR layout / topology here in the board file. This will
  43. * be used by the DDR3 init code in the SPL U-Boot version to configure
  44. * the DDR3 controller.
  45. */
  46. static struct mv_ddr_topology_map ddr_topology_map = {
  47. DEBUG_LEVEL_ERROR,
  48. 0x1, /* active interfaces */
  49. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  50. { { { {0x1, 0, 0, 0},
  51. {0x1, 0, 0, 0},
  52. {0x1, 0, 0, 0},
  53. {0x1, 0, 0, 0},
  54. {0x1, 0, 0, 0} },
  55. SPEED_BIN_DDR_1600K, /* speed_bin */
  56. MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
  57. MV_DDR_DIE_CAP_4GBIT, /* mem_size */
  58. MV_DDR_FREQ_533, /* frequency */
  59. 0, 0, /* cas_wl cas_l */
  60. MV_DDR_TEMP_LOW, /* temperature */
  61. MV_DDR_TIM_DEFAULT} }, /* timing */
  62. BUS_MASK_32BIT, /* Busses mask */
  63. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  64. NOT_COMBINED, /* ddr twin-die combined */
  65. { {0} }, /* raw spd data */
  66. {0} /* timing parameters */
  67. };
  68. static struct serdes_map serdes_topology_map[] = {
  69. {SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  70. {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  71. /* SATA tx polarity is inverted */
  72. {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 1},
  73. {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  74. {DEFAULT_SERDES, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  75. {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}
  76. };
  77. int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  78. {
  79. *serdes_map_array = serdes_topology_map;
  80. *count = ARRAY_SIZE(serdes_topology_map);
  81. return 0;
  82. }
  83. void board_pex_config(void)
  84. {
  85. #ifdef CONFIG_SPL_BUILD
  86. uint k;
  87. struct gpio_desc gpio = {};
  88. if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) {
  89. /* prepare FPGA reconfiguration */
  90. dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
  91. dm_gpio_set_value(&gpio, 0);
  92. /* give lunatic PCIe clock some time to stabilize */
  93. mdelay(500);
  94. /* start FPGA reconfiguration */
  95. dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN);
  96. }
  97. /* wait for FPGA done */
  98. if (!request_gpio_by_name(&gpio, "pca9698@22", 19, "fpga-done-gpio")) {
  99. for (k = 0; k < 20; ++k) {
  100. if (dm_gpio_get_value(&gpio)) {
  101. printf("FPGA done after %u rounds\n", k);
  102. break;
  103. }
  104. mdelay(100);
  105. }
  106. }
  107. /* disable FPGA reset */
  108. if (!request_gpio_by_name(&gpio, "gpio@18100", 6, "cpu-to-fpga-reset")) {
  109. dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
  110. dm_gpio_set_value(&gpio, 1);
  111. }
  112. /* wait for FPGA ready */
  113. if (!request_gpio_by_name(&gpio, "pca9698@22", 27, "fpga-ready-gpio")) {
  114. for (k = 0; k < 2; ++k) {
  115. if (!dm_gpio_get_value(&gpio))
  116. break;
  117. mdelay(100);
  118. }
  119. }
  120. #endif
  121. }
  122. struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  123. {
  124. return &ddr_topology_map;
  125. }
  126. int board_early_init_f(void)
  127. {
  128. #ifdef CONFIG_SPL_BUILD
  129. /* Configure MPP */
  130. writel(0x00111111, MVEBU_MPP_BASE + 0x00);
  131. writel(0x40040000, MVEBU_MPP_BASE + 0x04);
  132. writel(0x00466444, MVEBU_MPP_BASE + 0x08);
  133. writel(0x00043300, MVEBU_MPP_BASE + 0x0c);
  134. writel(0x44400000, MVEBU_MPP_BASE + 0x10);
  135. writel(0x20000334, MVEBU_MPP_BASE + 0x14);
  136. writel(0x40000000, MVEBU_MPP_BASE + 0x18);
  137. writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
  138. /* Set GPP Out value */
  139. writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  140. writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  141. /* Set GPP Polarity */
  142. writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
  143. writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
  144. /* Set GPP Out Enable */
  145. writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
  146. writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
  147. #endif
  148. return 0;
  149. }
  150. int board_init(void)
  151. {
  152. /* Address of boot parameters */
  153. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  154. return 0;
  155. }
  156. #ifndef CONFIG_SPL_BUILD
  157. void init_host_phys(struct mii_dev *bus)
  158. {
  159. uint k;
  160. for (k = 0; k < 2; ++k) {
  161. struct phy_device *phydev;
  162. phydev = phy_find_by_mask(bus, 1 << k,
  163. PHY_INTERFACE_MODE_SGMII);
  164. if (phydev)
  165. phy_config(phydev);
  166. }
  167. }
  168. int ccdc_eth_init(void)
  169. {
  170. uint k;
  171. uint octo_phy_mask = 0;
  172. int ret;
  173. struct mii_dev *bus;
  174. /* Init SoC's phys */
  175. bus = miiphy_get_dev_by_name("ethernet@34000");
  176. if (bus)
  177. init_host_phys(bus);
  178. bus = miiphy_get_dev_by_name("ethernet@70000");
  179. if (bus)
  180. init_host_phys(bus);
  181. /* Init octo phys */
  182. octo_phy_mask = calculate_octo_phy_mask();
  183. printf("IHS PHYS: %08x", octo_phy_mask);
  184. ret = init_octo_phys(octo_phy_mask);
  185. if (ret)
  186. return ret;
  187. printf("\n");
  188. if (!get_fpga()) {
  189. puts("fpga was NULL\n");
  190. return 1;
  191. }
  192. /* reset all FPGA-QSGMII instances */
  193. for (k = 0; k < 80; ++k)
  194. writel(1 << 31, get_fpga()->qsgmii_port_state[k]);
  195. udelay(100);
  196. for (k = 0; k < 80; ++k)
  197. writel(0, get_fpga()->qsgmii_port_state[k]);
  198. return 0;
  199. }
  200. #endif
  201. int board_late_init(void)
  202. {
  203. #ifndef CONFIG_SPL_BUILD
  204. hydra_initialize();
  205. #endif
  206. return 0;
  207. }
  208. int board_fix_fdt(void *rw_fdt_blob)
  209. {
  210. struct udevice *bus = NULL;
  211. uint k;
  212. char name[64];
  213. int err;
  214. err = uclass_get_device_by_name(UCLASS_I2C, "i2c@11000", &bus);
  215. if (err) {
  216. printf("Could not get I2C bus.\n");
  217. return err;
  218. }
  219. for (k = 0x21; k <= 0x26; k++) {
  220. snprintf(name, 64,
  221. "/soc/internal-regs/i2c@11000/pca9698@%02x", k);
  222. if (!dm_i2c_simple_probe(bus, k))
  223. fdt_disable_by_ofname(rw_fdt_blob, name);
  224. }
  225. return 0;
  226. }
  227. int last_stage_init(void)
  228. {
  229. struct udevice *tpm;
  230. int ret;
  231. #ifndef CONFIG_SPL_BUILD
  232. ccdc_eth_init();
  233. #endif
  234. ret = get_tpm(&tpm);
  235. if (ret || tpm_init(tpm) || tpm1_startup(tpm, TPM_ST_CLEAR) ||
  236. tpm1_continue_self_test(tpm)) {
  237. return 1;
  238. }
  239. mdelay(37);
  240. flush_keys(tpm);
  241. load_and_run_keyprog(tpm);
  242. return 0;
  243. }