microchip-mpfs-icicle-kit.dts 10 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /* Copyright (c) 2020 Microchip Technology Inc */
  3. /dts-v1/;
  4. #include "dt-bindings/clock/microchip-mpfs-clock.h"
  5. /* Clock frequency (in Hz) of the rtcclk */
  6. #define RTCCLK_FREQ 1000000
  7. / {
  8. #address-cells = <2>;
  9. #size-cells = <2>;
  10. model = "Microchip MPFS Icicle Kit";
  11. compatible = "microchip,mpfs-icicle-kit";
  12. aliases {
  13. serial0 = &uart0;
  14. ethernet0 = &emac1;
  15. };
  16. chosen {
  17. stdout-path = "serial0";
  18. };
  19. cpucomplex: cpus {
  20. #address-cells = <1>;
  21. #size-cells = <0>;
  22. timebase-frequency = <RTCCLK_FREQ>;
  23. cpu0: cpu@0 {
  24. clocks = <&clkcfg CLK_CPU>;
  25. compatible = "sifive,e51", "sifive,rocket0", "riscv";
  26. device_type = "cpu";
  27. i-cache-block-size = <64>;
  28. i-cache-sets = <128>;
  29. i-cache-size = <16384>;
  30. reg = <0>;
  31. riscv,isa = "rv64imac";
  32. status = "disabled";
  33. operating-points = <
  34. /* kHz uV */
  35. 600000 1100000
  36. 300000 950000
  37. 150000 750000
  38. >;
  39. cpu0intc: interrupt-controller {
  40. #interrupt-cells = <1>;
  41. compatible = "riscv,cpu-intc";
  42. interrupt-controller;
  43. };
  44. };
  45. cpu1: cpu@1 {
  46. clocks = <&clkcfg CLK_CPU>;
  47. compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  48. d-cache-block-size = <64>;
  49. d-cache-sets = <64>;
  50. d-cache-size = <32768>;
  51. d-tlb-sets = <1>;
  52. d-tlb-size = <32>;
  53. device_type = "cpu";
  54. i-cache-block-size = <64>;
  55. i-cache-sets = <64>;
  56. i-cache-size = <32768>;
  57. i-tlb-sets = <1>;
  58. i-tlb-size = <32>;
  59. mmu-type = "riscv,sv39";
  60. reg = <1>;
  61. riscv,isa = "rv64imafdc";
  62. tlb-split;
  63. status = "okay";
  64. operating-points = <
  65. /* kHz uV */
  66. 600000 1100000
  67. 300000 950000
  68. 150000 750000
  69. >;
  70. cpu1intc: interrupt-controller {
  71. #interrupt-cells = <1>;
  72. compatible = "riscv,cpu-intc";
  73. interrupt-controller;
  74. };
  75. };
  76. cpu2: cpu@2 {
  77. clocks = <&clkcfg CLK_CPU>;
  78. compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  79. d-cache-block-size = <64>;
  80. d-cache-sets = <64>;
  81. d-cache-size = <32768>;
  82. d-tlb-sets = <1>;
  83. d-tlb-size = <32>;
  84. device_type = "cpu";
  85. i-cache-block-size = <64>;
  86. i-cache-sets = <64>;
  87. i-cache-size = <32768>;
  88. i-tlb-sets = <1>;
  89. i-tlb-size = <32>;
  90. mmu-type = "riscv,sv39";
  91. reg = <2>;
  92. riscv,isa = "rv64imafdc";
  93. tlb-split;
  94. status = "okay";
  95. operating-points = <
  96. /* kHz uV */
  97. 600000 1100000
  98. 300000 950000
  99. 150000 750000
  100. >;
  101. cpu2intc: interrupt-controller {
  102. #interrupt-cells = <1>;
  103. compatible = "riscv,cpu-intc";
  104. interrupt-controller;
  105. };
  106. };
  107. cpu3: cpu@3 {
  108. clocks = <&clkcfg CLK_CPU>;
  109. compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  110. d-cache-block-size = <64>;
  111. d-cache-sets = <64>;
  112. d-cache-size = <32768>;
  113. d-tlb-sets = <1>;
  114. d-tlb-size = <32>;
  115. device_type = "cpu";
  116. i-cache-block-size = <64>;
  117. i-cache-sets = <64>;
  118. i-cache-size = <32768>;
  119. i-tlb-sets = <1>;
  120. i-tlb-size = <32>;
  121. mmu-type = "riscv,sv39";
  122. reg = <3>;
  123. riscv,isa = "rv64imafdc";
  124. tlb-split;
  125. status = "okay";
  126. operating-points = <
  127. /* kHz uV */
  128. 600000 1100000
  129. 300000 950000
  130. 150000 750000
  131. >;
  132. cpu3intc: interrupt-controller {
  133. #interrupt-cells = <1>;
  134. compatible = "riscv,cpu-intc";
  135. interrupt-controller;
  136. };
  137. };
  138. cpu4: cpu@4 {
  139. clocks = <&clkcfg CLK_CPU>;
  140. compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  141. d-cache-block-size = <64>;
  142. d-cache-sets = <64>;
  143. d-cache-size = <32768>;
  144. d-tlb-sets = <1>;
  145. d-tlb-size = <32>;
  146. device_type = "cpu";
  147. i-cache-block-size = <64>;
  148. i-cache-sets = <64>;
  149. i-cache-size = <32768>;
  150. i-tlb-sets = <1>;
  151. i-tlb-size = <32>;
  152. mmu-type = "riscv,sv39";
  153. reg = <4>;
  154. riscv,isa = "rv64imafdc";
  155. tlb-split;
  156. status = "okay";
  157. operating-points = <
  158. /* kHz uV */
  159. 600000 1100000
  160. 300000 950000
  161. 150000 750000
  162. >;
  163. cpu4intc: interrupt-controller {
  164. #interrupt-cells = <1>;
  165. compatible = "riscv,cpu-intc";
  166. interrupt-controller;
  167. };
  168. };
  169. };
  170. refclk: refclk {
  171. compatible = "fixed-clock";
  172. #clock-cells = <0>;
  173. clock-frequency = <600000000>;
  174. clock-output-names = "msspllclk";
  175. };
  176. ddr: memory@80000000 {
  177. device_type = "memory";
  178. reg = <0x0 0x80000000 0x0 0x40000000>;
  179. clocks = <&clkcfg CLK_DDRC>;
  180. };
  181. soc: soc {
  182. #address-cells = <2>;
  183. #size-cells = <2>;
  184. compatible = "microchip,mpfs-icicle-kit", "simple-bus";
  185. ranges;
  186. clint0: clint@2000000 {
  187. compatible = "riscv,clint0";
  188. interrupts-extended = <&cpu0intc 3 &cpu0intc 7
  189. &cpu1intc 3 &cpu1intc 7
  190. &cpu2intc 3 &cpu2intc 7
  191. &cpu3intc 3 &cpu3intc 7
  192. &cpu4intc 3 &cpu4intc 7>;
  193. reg = <0x0 0x2000000 0x0 0x10000>;
  194. reg-names = "control";
  195. clock-frequency = <RTCCLK_FREQ>;
  196. };
  197. cachecontroller: cache-controller@2010000 {
  198. compatible = "sifive,fu540-c000-ccache", "cache";
  199. cache-block-size = <64>;
  200. cache-level = <2>;
  201. cache-sets = <1024>;
  202. cache-size = <2097152>;
  203. cache-unified;
  204. interrupt-parent = <&plic>;
  205. interrupts = <1 2 3>;
  206. reg = <0x0 0x2010000 0x0 0x1000>;
  207. };
  208. plic: interrupt-controller@c000000 {
  209. #interrupt-cells = <1>;
  210. compatible = "sifive,plic-1.0.0";
  211. reg = <0x0 0xc000000 0x0 0x4000000>;
  212. riscv,max-priority = <7>;
  213. riscv,ndev = <186>;
  214. interrupt-controller;
  215. interrupts-extended = <
  216. &cpu0intc 11
  217. &cpu1intc 11 &cpu1intc 9
  218. &cpu2intc 11 &cpu2intc 9
  219. &cpu3intc 11 &cpu3intc 9
  220. &cpu4intc 11 &cpu4intc 9>;
  221. };
  222. uart0: serial@20000000 {
  223. compatible = "ns16550a";
  224. reg = <0x0 0x20000000 0x0 0x400>;
  225. reg-io-width = <4>;
  226. reg-shift = <2>;
  227. interrupt-parent = <&plic>;
  228. interrupts = <90>;
  229. clocks = <&clkcfg CLK_MMUART0>;
  230. status = "okay";
  231. };
  232. clkcfg: clkcfg@20002000 {
  233. compatible = "microchip,mpfs-clkcfg";
  234. reg = <0x0 0x20002000 0x0 0x1000>;
  235. reg-names = "mss_sysreg";
  236. clocks = <&refclk>;
  237. #clock-cells = <1>;
  238. clock-output-names = "cpu", "axi", "ahb", "envm",
  239. "mac0", "mac1", "mmc", "timer",
  240. "mmuart0", "mmuart1", "mmuart2",
  241. "mmuart3", "mmuart4", "spi0", "spi1",
  242. "i2c0", "i2c1", "can0", "can1", "usb",
  243. "reserved", "rtc", "qspi", "gpio0",
  244. "gpio1", "gpio2", "ddrc", "fic0",
  245. "fic1", "fic2", "fic3", "athena",
  246. "cfm";
  247. };
  248. emmc: mmc@20008000 {
  249. compatible = "cdns,sd4hc";
  250. reg = <0x0 0x20008000 0x0 0x1000>;
  251. interrupt-parent = <&plic>;
  252. interrupts = <88 89>;
  253. pinctrl-names = "default";
  254. clocks = <&clkcfg CLK_MMC>;
  255. bus-width = <4>;
  256. cap-mmc-highspeed;
  257. mmc-ddr-3_3v;
  258. max-frequency = <200000000>;
  259. non-removable;
  260. no-sd;
  261. no-sdio;
  262. voltage-ranges = <3300 3300>;
  263. status = "okay";
  264. };
  265. sdcard: sd@20008000 {
  266. compatible = "cdns,sd4hc";
  267. reg = <0x0 0x20008000 0x0 0x1000>;
  268. interrupt-parent = <&plic>;
  269. interrupts = <88>;
  270. pinctrl-names = "default";
  271. clocks = <&clkcfg CLK_MMC>;
  272. bus-width = <4>;
  273. disable-wp;
  274. cap-sd-highspeed;
  275. card-detect-delay = <200>;
  276. sd-uhs-sdr12;
  277. sd-uhs-sdr25;
  278. sd-uhs-sdr50;
  279. sd-uhs-sdr104;
  280. max-frequency = <200000000>;
  281. status = "disabled";
  282. };
  283. uart1: serial@20100000 {
  284. compatible = "ns16550a";
  285. reg = <0x0 0x20100000 0x0 0x400>;
  286. reg-io-width = <4>;
  287. reg-shift = <2>;
  288. interrupt-parent = <&plic>;
  289. interrupts = <91>;
  290. clocks = <&clkcfg CLK_MMUART1>;
  291. status = "okay";
  292. };
  293. uart2: serial@20102000 {
  294. compatible = "ns16550a";
  295. reg = <0x0 0x20102000 0x0 0x400>;
  296. reg-io-width = <4>;
  297. reg-shift = <2>;
  298. interrupt-parent = <&plic>;
  299. interrupts = <92>;
  300. clocks = <&clkcfg CLK_MMUART2>;
  301. status = "okay";
  302. };
  303. uart3: serial@20104000 {
  304. compatible = "ns16550a";
  305. reg = <0x0 0x20104000 0x0 0x400>;
  306. reg-io-width = <4>;
  307. reg-shift = <2>;
  308. interrupt-parent = <&plic>;
  309. interrupts = <93>;
  310. clocks = <&clkcfg CLK_MMUART3>;
  311. status = "okay";
  312. };
  313. i2c0: i2c@2010a000 {
  314. #address-cells = <1>;
  315. #size-cells = <0>;
  316. compatible = "microchip,mpfs-mss-i2c";
  317. reg = <0x0 0x2010a000 0x0 0x1000>;
  318. interrupt-parent = <&plic>;
  319. interrupts = <58>;
  320. clocks = <&clkcfg CLK_I2C0>;
  321. status = "disabled";
  322. };
  323. i2c1: i2c@2010b000 {
  324. #address-cells = <1>;
  325. #size-cells = <0>;
  326. compatible = "microchip,mpfs-mss-i2c";
  327. reg = <0x0 0x2010b000 0x0 0x1000>;
  328. interrupt-parent = <&plic>;
  329. interrupts = <61>;
  330. clocks = <&clkcfg CLK_I2C1>;
  331. status = "disabled";
  332. pac193x@10 {
  333. compatible = "microchip,pac1934";
  334. reg = <0x10>;
  335. samp-rate = <64>;
  336. status = "disabled";
  337. ch1: channel0 {
  338. uohms-shunt-res = <10000>;
  339. rail-name = "VDD";
  340. channel_enabled;
  341. };
  342. ch2: channel1 {
  343. uohms-shunt-res = <10000>;
  344. rail-name = "VDDA25";
  345. channel_enabled;
  346. };
  347. ch3: channel2 {
  348. uohms-shunt-res = <10000>;
  349. rail-name = "VDD25";
  350. channel_enabled;
  351. };
  352. ch4: channel3 {
  353. uohms-shunt-res = <10000>;
  354. rail-name = "VDDA";
  355. channel_enabled;
  356. };
  357. };
  358. };
  359. emac0: ethernet@20110000 {
  360. compatible = "microchip,mpfs-mss-gem";
  361. reg = <0x0 0x20110000 0x0 0x2000>;
  362. interrupt-parent = <&plic>;
  363. interrupts = <64 65 66 67>;
  364. local-mac-address = [56 34 00 FC 00 02];
  365. phy-mode = "sgmii";
  366. clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AXI>;
  367. clock-names = "pclk", "hclk";
  368. status = "disabled";
  369. #address-cells = <1>;
  370. #size-cells = <0>;
  371. phy-handle = <&phy0>;
  372. phy0: ethernet-phy@8 {
  373. reg = <8>;
  374. ti,fifo-depth = <0x01>;
  375. };
  376. };
  377. emac1: ethernet@20112000 {
  378. compatible = "microchip,mpfs-mss-gem";
  379. reg = <0x0 0x20112000 0x0 0x2000>;
  380. interrupt-parent = <&plic>;
  381. interrupts = <70 71 72 73>;
  382. local-mac-address = [00 00 00 00 00 00];
  383. phy-mode = "sgmii";
  384. clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
  385. clock-names = "pclk", "hclk";
  386. status = "okay";
  387. #address-cells = <1>;
  388. #size-cells = <0>;
  389. phy-handle = <&phy1>;
  390. phy1: ethernet-phy@9 {
  391. reg = <9>;
  392. ti,fifo-depth = <0x01>;
  393. };
  394. };
  395. gpio: gpio@20122000 {
  396. compatible = "microchip,mpfs-mss-gpio";
  397. interrupt-parent = <&plic>;
  398. interrupts = <13 14 15 16 17 18 19 20 21 22 23 24 25 26
  399. 27 28 29 30 31 32 33 34 35 36 37 38 39
  400. 40 41 42 43 44>;
  401. gpio-controller;
  402. clocks = <&clkcfg CLK_GPIO2>;
  403. reg = <0x00 0x20122000 0x0 0x1000>;
  404. reg-names = "control";
  405. #gpio-cells = <2>;
  406. status = "disabled";
  407. };
  408. };
  409. };