fu740-c000.dtsi 8.7 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /* Copyright (c) 2020-2021 SiFive, Inc */
  3. /dts-v1/;
  4. #include <dt-bindings/clock/sifive-fu740-prci.h>
  5. #include <dt-bindings/reset/sifive-fu740-prci.h>
  6. / {
  7. #address-cells = <2>;
  8. #size-cells = <2>;
  9. compatible = "sifive,fu740-c000", "sifive,fu740";
  10. aliases {
  11. serial0 = &uart0;
  12. serial1 = &uart1;
  13. ethernet0 = &eth0;
  14. };
  15. chosen {
  16. };
  17. cpus {
  18. #address-cells = <1>;
  19. #size-cells = <0>;
  20. cpu0: cpu@0 {
  21. compatible = "sifive,bullet0", "riscv";
  22. device_type = "cpu";
  23. i-cache-block-size = <64>;
  24. i-cache-sets = <128>;
  25. i-cache-size = <16384>;
  26. next-level-cache = <&ccache>;
  27. reg = <0x0>;
  28. riscv,isa = "rv64imac";
  29. status = "disabled";
  30. cpu0_intc: interrupt-controller {
  31. #interrupt-cells = <1>;
  32. compatible = "riscv,cpu-intc";
  33. interrupt-controller;
  34. };
  35. };
  36. cpu1: cpu@1 {
  37. compatible = "sifive,bullet0", "riscv";
  38. d-cache-block-size = <64>;
  39. d-cache-sets = <64>;
  40. d-cache-size = <32768>;
  41. d-tlb-sets = <1>;
  42. d-tlb-size = <40>;
  43. device_type = "cpu";
  44. i-cache-block-size = <64>;
  45. i-cache-sets = <128>;
  46. i-cache-size = <32768>;
  47. i-tlb-sets = <1>;
  48. i-tlb-size = <40>;
  49. mmu-type = "riscv,sv39";
  50. next-level-cache = <&ccache>;
  51. reg = <0x1>;
  52. riscv,isa = "rv64imafdc";
  53. tlb-split;
  54. cpu1_intc: interrupt-controller {
  55. #interrupt-cells = <1>;
  56. compatible = "riscv,cpu-intc";
  57. interrupt-controller;
  58. };
  59. };
  60. cpu2: cpu@2 {
  61. compatible = "sifive,bullet0", "riscv";
  62. d-cache-block-size = <64>;
  63. d-cache-sets = <64>;
  64. d-cache-size = <32768>;
  65. d-tlb-sets = <1>;
  66. d-tlb-size = <40>;
  67. device_type = "cpu";
  68. i-cache-block-size = <64>;
  69. i-cache-sets = <128>;
  70. i-cache-size = <32768>;
  71. i-tlb-sets = <1>;
  72. i-tlb-size = <40>;
  73. mmu-type = "riscv,sv39";
  74. next-level-cache = <&ccache>;
  75. reg = <0x2>;
  76. riscv,isa = "rv64imafdc";
  77. tlb-split;
  78. cpu2_intc: interrupt-controller {
  79. #interrupt-cells = <1>;
  80. compatible = "riscv,cpu-intc";
  81. interrupt-controller;
  82. };
  83. };
  84. cpu3: cpu@3 {
  85. compatible = "sifive,bullet0", "riscv";
  86. d-cache-block-size = <64>;
  87. d-cache-sets = <64>;
  88. d-cache-size = <32768>;
  89. d-tlb-sets = <1>;
  90. d-tlb-size = <40>;
  91. device_type = "cpu";
  92. i-cache-block-size = <64>;
  93. i-cache-sets = <128>;
  94. i-cache-size = <32768>;
  95. i-tlb-sets = <1>;
  96. i-tlb-size = <40>;
  97. mmu-type = "riscv,sv39";
  98. next-level-cache = <&ccache>;
  99. reg = <0x3>;
  100. riscv,isa = "rv64imafdc";
  101. tlb-split;
  102. cpu3_intc: interrupt-controller {
  103. #interrupt-cells = <1>;
  104. compatible = "riscv,cpu-intc";
  105. interrupt-controller;
  106. };
  107. };
  108. cpu4: cpu@4 {
  109. compatible = "sifive,bullet0", "riscv";
  110. d-cache-block-size = <64>;
  111. d-cache-sets = <64>;
  112. d-cache-size = <32768>;
  113. d-tlb-sets = <1>;
  114. d-tlb-size = <40>;
  115. device_type = "cpu";
  116. i-cache-block-size = <64>;
  117. i-cache-sets = <128>;
  118. i-cache-size = <32768>;
  119. i-tlb-sets = <1>;
  120. i-tlb-size = <40>;
  121. mmu-type = "riscv,sv39";
  122. next-level-cache = <&ccache>;
  123. reg = <0x4>;
  124. riscv,isa = "rv64imafdc";
  125. tlb-split;
  126. cpu4_intc: interrupt-controller {
  127. #interrupt-cells = <1>;
  128. compatible = "riscv,cpu-intc";
  129. interrupt-controller;
  130. };
  131. };
  132. };
  133. soc {
  134. #address-cells = <2>;
  135. #size-cells = <2>;
  136. compatible = "sifive,fu740-c000", "sifive,fu740", "simple-bus";
  137. ranges;
  138. plic0: interrupt-controller@c000000 {
  139. #interrupt-cells = <1>;
  140. compatible = "sifive,plic-1.0.0";
  141. reg = <0x0 0xc000000 0x0 0x4000000>;
  142. riscv,ndev = <69>;
  143. interrupt-controller;
  144. interrupts-extended = <
  145. &cpu0_intc 0xffffffff
  146. &cpu1_intc 0xffffffff &cpu1_intc 9
  147. &cpu2_intc 0xffffffff &cpu2_intc 9
  148. &cpu3_intc 0xffffffff &cpu3_intc 9
  149. &cpu4_intc 0xffffffff &cpu4_intc 9>;
  150. };
  151. prci: clock-controller@10000000 {
  152. compatible = "sifive,fu740-c000-prci";
  153. reg = <0x0 0x10000000 0x0 0x1000>;
  154. clocks = <&hfclk>, <&rtcclk>;
  155. #clock-cells = <1>;
  156. #reset-cells = <1>;
  157. };
  158. uart0: serial@10010000 {
  159. compatible = "sifive,fu740-c000-uart", "sifive,uart0";
  160. reg = <0x0 0x10010000 0x0 0x1000>;
  161. interrupt-parent = <&plic0>;
  162. interrupts = <39>;
  163. clocks = <&prci PRCI_CLK_PCLK>;
  164. status = "disabled";
  165. };
  166. uart1: serial@10011000 {
  167. compatible = "sifive,fu740-c000-uart", "sifive,uart0";
  168. reg = <0x0 0x10011000 0x0 0x1000>;
  169. interrupt-parent = <&plic0>;
  170. interrupts = <40>;
  171. clocks = <&prci PRCI_CLK_PCLK>;
  172. status = "disabled";
  173. };
  174. i2c0: i2c@10030000 {
  175. compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
  176. reg = <0x0 0x10030000 0x0 0x1000>;
  177. interrupt-parent = <&plic0>;
  178. interrupts = <52>;
  179. clocks = <&prci PRCI_CLK_PCLK>;
  180. reg-shift = <2>;
  181. reg-io-width = <1>;
  182. #address-cells = <1>;
  183. #size-cells = <0>;
  184. status = "disabled";
  185. };
  186. i2c1: i2c@10031000 {
  187. compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
  188. reg = <0x0 0x10031000 0x0 0x1000>;
  189. interrupt-parent = <&plic0>;
  190. interrupts = <53>;
  191. clocks = <&prci PRCI_CLK_PCLK>;
  192. reg-shift = <2>;
  193. reg-io-width = <1>;
  194. #address-cells = <1>;
  195. #size-cells = <0>;
  196. status = "disabled";
  197. };
  198. qspi0: spi@10040000 {
  199. compatible = "sifive,fu740-c000-spi", "sifive,spi0";
  200. reg = <0x0 0x10040000 0x0 0x1000
  201. 0x0 0x20000000 0x0 0x10000000>;
  202. interrupt-parent = <&plic0>;
  203. interrupts = <41>;
  204. clocks = <&prci PRCI_CLK_PCLK>;
  205. #address-cells = <1>;
  206. #size-cells = <0>;
  207. status = "disabled";
  208. };
  209. qspi1: spi@10041000 {
  210. compatible = "sifive,fu740-c000-spi", "sifive,spi0";
  211. reg = <0x0 0x10041000 0x0 0x1000
  212. 0x0 0x30000000 0x0 0x10000000>;
  213. interrupt-parent = <&plic0>;
  214. interrupts = <42>;
  215. clocks = <&prci PRCI_CLK_PCLK>;
  216. #address-cells = <1>;
  217. #size-cells = <0>;
  218. status = "disabled";
  219. };
  220. spi0: spi@10050000 {
  221. compatible = "sifive,fu740-c000-spi", "sifive,spi0";
  222. reg = <0x0 0x10050000 0x0 0x1000>;
  223. interrupt-parent = <&plic0>;
  224. interrupts = <43>;
  225. clocks = <&prci PRCI_CLK_PCLK>;
  226. #address-cells = <1>;
  227. #size-cells = <0>;
  228. status = "disabled";
  229. };
  230. eth0: ethernet@10090000 {
  231. compatible = "sifive,fu540-c000-gem";
  232. interrupt-parent = <&plic0>;
  233. interrupts = <55>;
  234. reg = <0x0 0x10090000 0x0 0x2000
  235. 0x0 0x100a0000 0x0 0x1000>;
  236. local-mac-address = [00 00 00 00 00 00];
  237. clock-names = "pclk", "hclk";
  238. clocks = <&prci PRCI_CLK_GEMGXLPLL>,
  239. <&prci PRCI_CLK_GEMGXLPLL>;
  240. #address-cells = <1>;
  241. #size-cells = <0>;
  242. status = "disabled";
  243. };
  244. pwm0: pwm@10020000 {
  245. compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
  246. reg = <0x0 0x10020000 0x0 0x1000>;
  247. interrupt-parent = <&plic0>;
  248. interrupts = <44 45 46 47>;
  249. clocks = <&prci PRCI_CLK_PCLK>;
  250. #pwm-cells = <3>;
  251. status = "disabled";
  252. };
  253. pwm1: pwm@10021000 {
  254. compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
  255. reg = <0x0 0x10021000 0x0 0x1000>;
  256. interrupt-parent = <&plic0>;
  257. interrupts = <48 49 50 51>;
  258. clocks = <&prci PRCI_CLK_PCLK>;
  259. #pwm-cells = <3>;
  260. status = "disabled";
  261. };
  262. ccache: cache-controller@2010000 {
  263. compatible = "sifive,fu740-c000-ccache", "cache";
  264. cache-block-size = <64>;
  265. cache-level = <2>;
  266. cache-sets = <2048>;
  267. cache-size = <2097152>;
  268. cache-unified;
  269. interrupt-parent = <&plic0>;
  270. interrupts = <19 21 22 20>;
  271. reg = <0x0 0x2010000 0x0 0x1000>;
  272. };
  273. gpio: gpio@10060000 {
  274. compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
  275. interrupt-parent = <&plic0>;
  276. interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
  277. <30>, <31>, <32>, <33>, <34>, <35>, <36>,
  278. <37>, <38>;
  279. reg = <0x0 0x10060000 0x0 0x1000>;
  280. gpio-controller;
  281. #gpio-cells = <2>;
  282. interrupt-controller;
  283. #interrupt-cells = <2>;
  284. clocks = <&prci PRCI_CLK_PCLK>;
  285. status = "disabled";
  286. };
  287. pcie@e00000000 {
  288. #address-cells = <3>;
  289. #interrupt-cells = <1>;
  290. #num-lanes = <8>;
  291. #size-cells = <2>;
  292. compatible = "sifive,fu740-pcie";
  293. reg = <0xe 0x00000000 0x1 0x0
  294. 0xd 0xf0000000 0x0 0x10000000
  295. 0x0 0x100d0000 0x0 0x1000>;
  296. reg-names = "dbi", "config", "mgmt";
  297. device_type = "pci";
  298. dma-coherent;
  299. bus-range = <0x0 0xff>;
  300. ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000
  301. 0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000
  302. 0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000
  303. 0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;
  304. num-lanes = <0x8>;
  305. interrupts = <56 57 58 59 60 61 62 63 64>;
  306. interrupt-names = "msi", "inta", "intb", "intc", "intd";
  307. interrupt-parent = <&plic0>;
  308. interrupt-map-mask = <0x0 0x0 0x0 0x7>;
  309. interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
  310. <0x0 0x0 0x0 0x2 &plic0 58>,
  311. <0x0 0x0 0x0 0x3 &plic0 59>,
  312. <0x0 0x0 0x0 0x4 &plic0 60>;
  313. pwren-gpios = <&gpio 5 0>;
  314. reset-gpios = <&gpio 8 0>;
  315. clocks = <&prci PRCI_CLK_PCIEAUX>;
  316. clock-names = "pcieaux";
  317. resets = <&prci PRCI_RST_PCIE_POWER_UP_N>;
  318. reset-names = "rst_n";
  319. status = "okay";
  320. };
  321. };
  322. };