fu540-c000.dtsi 7.4 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /* Copyright (c) 2018-2019 SiFive, Inc */
  3. /dts-v1/;
  4. #include <dt-bindings/clock/sifive-fu540-prci.h>
  5. / {
  6. #address-cells = <2>;
  7. #size-cells = <2>;
  8. compatible = "sifive,fu540-c000", "sifive,fu540";
  9. aliases {
  10. serial0 = &uart0;
  11. serial1 = &uart1;
  12. ethernet0 = &eth0;
  13. };
  14. chosen {
  15. };
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. cpu0: cpu@0 {
  20. compatible = "sifive,e51", "sifive,rocket0", "riscv";
  21. device_type = "cpu";
  22. i-cache-block-size = <64>;
  23. i-cache-sets = <128>;
  24. i-cache-size = <16384>;
  25. reg = <0>;
  26. riscv,isa = "rv64imac";
  27. status = "disabled";
  28. cpu0_intc: interrupt-controller {
  29. #interrupt-cells = <1>;
  30. compatible = "riscv,cpu-intc";
  31. interrupt-controller;
  32. };
  33. };
  34. cpu1: cpu@1 {
  35. compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  36. d-cache-block-size = <64>;
  37. d-cache-sets = <64>;
  38. d-cache-size = <32768>;
  39. d-tlb-sets = <1>;
  40. d-tlb-size = <32>;
  41. device_type = "cpu";
  42. i-cache-block-size = <64>;
  43. i-cache-sets = <64>;
  44. i-cache-size = <32768>;
  45. i-tlb-sets = <1>;
  46. i-tlb-size = <32>;
  47. mmu-type = "riscv,sv39";
  48. reg = <1>;
  49. riscv,isa = "rv64imafdc";
  50. tlb-split;
  51. next-level-cache = <&l2cache>;
  52. cpu1_intc: interrupt-controller {
  53. #interrupt-cells = <1>;
  54. compatible = "riscv,cpu-intc";
  55. interrupt-controller;
  56. };
  57. };
  58. cpu2: cpu@2 {
  59. compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  60. d-cache-block-size = <64>;
  61. d-cache-sets = <64>;
  62. d-cache-size = <32768>;
  63. d-tlb-sets = <1>;
  64. d-tlb-size = <32>;
  65. device_type = "cpu";
  66. i-cache-block-size = <64>;
  67. i-cache-sets = <64>;
  68. i-cache-size = <32768>;
  69. i-tlb-sets = <1>;
  70. i-tlb-size = <32>;
  71. mmu-type = "riscv,sv39";
  72. reg = <2>;
  73. riscv,isa = "rv64imafdc";
  74. tlb-split;
  75. next-level-cache = <&l2cache>;
  76. cpu2_intc: interrupt-controller {
  77. #interrupt-cells = <1>;
  78. compatible = "riscv,cpu-intc";
  79. interrupt-controller;
  80. };
  81. };
  82. cpu3: cpu@3 {
  83. compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  84. d-cache-block-size = <64>;
  85. d-cache-sets = <64>;
  86. d-cache-size = <32768>;
  87. d-tlb-sets = <1>;
  88. d-tlb-size = <32>;
  89. device_type = "cpu";
  90. i-cache-block-size = <64>;
  91. i-cache-sets = <64>;
  92. i-cache-size = <32768>;
  93. i-tlb-sets = <1>;
  94. i-tlb-size = <32>;
  95. mmu-type = "riscv,sv39";
  96. reg = <3>;
  97. riscv,isa = "rv64imafdc";
  98. tlb-split;
  99. next-level-cache = <&l2cache>;
  100. cpu3_intc: interrupt-controller {
  101. #interrupt-cells = <1>;
  102. compatible = "riscv,cpu-intc";
  103. interrupt-controller;
  104. };
  105. };
  106. cpu4: cpu@4 {
  107. compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  108. d-cache-block-size = <64>;
  109. d-cache-sets = <64>;
  110. d-cache-size = <32768>;
  111. d-tlb-sets = <1>;
  112. d-tlb-size = <32>;
  113. device_type = "cpu";
  114. i-cache-block-size = <64>;
  115. i-cache-sets = <64>;
  116. i-cache-size = <32768>;
  117. i-tlb-sets = <1>;
  118. i-tlb-size = <32>;
  119. mmu-type = "riscv,sv39";
  120. reg = <4>;
  121. riscv,isa = "rv64imafdc";
  122. tlb-split;
  123. next-level-cache = <&l2cache>;
  124. cpu4_intc: interrupt-controller {
  125. #interrupt-cells = <1>;
  126. compatible = "riscv,cpu-intc";
  127. interrupt-controller;
  128. };
  129. };
  130. };
  131. soc {
  132. #address-cells = <2>;
  133. #size-cells = <2>;
  134. compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
  135. ranges;
  136. plic0: interrupt-controller@c000000 {
  137. #interrupt-cells = <1>;
  138. compatible = "sifive,plic-1.0.0";
  139. reg = <0x0 0xc000000 0x0 0x4000000>;
  140. riscv,ndev = <53>;
  141. interrupt-controller;
  142. interrupts-extended = <
  143. &cpu0_intc 0xffffffff
  144. &cpu1_intc 0xffffffff &cpu1_intc 9
  145. &cpu2_intc 0xffffffff &cpu2_intc 9
  146. &cpu3_intc 0xffffffff &cpu3_intc 9
  147. &cpu4_intc 0xffffffff &cpu4_intc 9>;
  148. };
  149. prci: clock-controller@10000000 {
  150. compatible = "sifive,fu540-c000-prci";
  151. reg = <0x0 0x10000000 0x0 0x1000>;
  152. clocks = <&hfclk>, <&rtcclk>;
  153. #clock-cells = <1>;
  154. };
  155. uart0: serial@10010000 {
  156. compatible = "sifive,fu540-c000-uart", "sifive,uart0";
  157. reg = <0x0 0x10010000 0x0 0x1000>;
  158. interrupt-parent = <&plic0>;
  159. interrupts = <4>;
  160. clocks = <&prci PRCI_CLK_TLCLK>;
  161. status = "disabled";
  162. };
  163. dma: dma@3000000 {
  164. compatible = "sifive,fu540-c000-pdma";
  165. reg = <0x0 0x3000000 0x0 0x8000>;
  166. interrupt-parent = <&plic0>;
  167. interrupts = <23 24 25 26 27 28 29 30>;
  168. #dma-cells = <1>;
  169. };
  170. uart1: serial@10011000 {
  171. compatible = "sifive,fu540-c000-uart", "sifive,uart0";
  172. reg = <0x0 0x10011000 0x0 0x1000>;
  173. interrupt-parent = <&plic0>;
  174. interrupts = <5>;
  175. clocks = <&prci PRCI_CLK_TLCLK>;
  176. status = "disabled";
  177. };
  178. i2c0: i2c@10030000 {
  179. compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
  180. reg = <0x0 0x10030000 0x0 0x1000>;
  181. interrupt-parent = <&plic0>;
  182. interrupts = <50>;
  183. clocks = <&prci PRCI_CLK_TLCLK>;
  184. reg-shift = <2>;
  185. reg-io-width = <1>;
  186. #address-cells = <1>;
  187. #size-cells = <0>;
  188. status = "disabled";
  189. };
  190. qspi0: spi@10040000 {
  191. compatible = "sifive,fu540-c000-spi", "sifive,spi0";
  192. reg = <0x0 0x10040000 0x0 0x1000
  193. 0x0 0x20000000 0x0 0x10000000>;
  194. interrupt-parent = <&plic0>;
  195. interrupts = <51>;
  196. clocks = <&prci PRCI_CLK_TLCLK>;
  197. #address-cells = <1>;
  198. #size-cells = <0>;
  199. status = "disabled";
  200. };
  201. qspi1: spi@10041000 {
  202. compatible = "sifive,fu540-c000-spi", "sifive,spi0";
  203. reg = <0x0 0x10041000 0x0 0x1000
  204. 0x0 0x30000000 0x0 0x10000000>;
  205. interrupt-parent = <&plic0>;
  206. interrupts = <52>;
  207. clocks = <&prci PRCI_CLK_TLCLK>;
  208. #address-cells = <1>;
  209. #size-cells = <0>;
  210. status = "disabled";
  211. };
  212. qspi2: spi@10050000 {
  213. compatible = "sifive,fu540-c000-spi", "sifive,spi0";
  214. reg = <0x0 0x10050000 0x0 0x1000>;
  215. interrupt-parent = <&plic0>;
  216. interrupts = <6>;
  217. clocks = <&prci PRCI_CLK_TLCLK>;
  218. #address-cells = <1>;
  219. #size-cells = <0>;
  220. status = "disabled";
  221. };
  222. eth0: ethernet@10090000 {
  223. compatible = "sifive,fu540-c000-gem";
  224. interrupt-parent = <&plic0>;
  225. interrupts = <53>;
  226. reg = <0x0 0x10090000 0x0 0x2000
  227. 0x0 0x100a0000 0x0 0x1000>;
  228. local-mac-address = [00 00 00 00 00 00];
  229. clock-names = "pclk", "hclk";
  230. clocks = <&prci PRCI_CLK_GEMGXLPLL>,
  231. <&prci PRCI_CLK_GEMGXLPLL>;
  232. #address-cells = <1>;
  233. #size-cells = <0>;
  234. status = "disabled";
  235. };
  236. pwm0: pwm@10020000 {
  237. compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
  238. reg = <0x0 0x10020000 0x0 0x1000>;
  239. interrupt-parent = <&plic0>;
  240. interrupts = <42 43 44 45>;
  241. clocks = <&prci PRCI_CLK_TLCLK>;
  242. #pwm-cells = <3>;
  243. status = "disabled";
  244. };
  245. pwm1: pwm@10021000 {
  246. compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
  247. reg = <0x0 0x10021000 0x0 0x1000>;
  248. interrupt-parent = <&plic0>;
  249. interrupts = <46 47 48 49>;
  250. clocks = <&prci PRCI_CLK_TLCLK>;
  251. #pwm-cells = <3>;
  252. status = "disabled";
  253. };
  254. l2cache: cache-controller@2010000 {
  255. compatible = "sifive,fu540-c000-ccache", "cache";
  256. cache-block-size = <64>;
  257. cache-level = <2>;
  258. cache-sets = <1024>;
  259. cache-size = <2097152>;
  260. cache-unified;
  261. interrupt-parent = <&plic0>;
  262. interrupts = <1 2 3>;
  263. reg = <0x0 0x2010000 0x0 0x1000>;
  264. };
  265. gpio: gpio@10060000 {
  266. compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
  267. interrupt-parent = <&plic0>;
  268. interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
  269. <14>, <15>, <16>, <17>, <18>, <19>, <20>,
  270. <21>, <22>;
  271. reg = <0x0 0x10060000 0x0 0x1000>;
  272. gpio-controller;
  273. #gpio-cells = <2>;
  274. interrupt-controller;
  275. #interrupt-cells = <2>;
  276. clocks = <&prci PRCI_CLK_TLCLK>;
  277. status = "disabled";
  278. };
  279. };
  280. };