neo.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
  4. * Copyright (C) Jasbir Matharu
  5. * Copyright (C) UDOO Team
  6. *
  7. * Author: Breno Lima <breno.lima@nxp.com>
  8. * Author: Francesco Montefoschi <francesco.monte@gmail.com>
  9. */
  10. #include <init.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/crm_regs.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/iomux.h>
  15. #include <asm/arch/mx6-pins.h>
  16. #include <asm/global_data.h>
  17. #include <asm/gpio.h>
  18. #include <asm/mach-imx/iomux-v3.h>
  19. #include <dm.h>
  20. #include <env.h>
  21. #include <asm/arch/crm_regs.h>
  22. #include <asm/io.h>
  23. #include <asm/mach-imx/mxc_i2c.h>
  24. #include <asm/arch/sys_proto.h>
  25. #include <spl.h>
  26. #include <linux/delay.h>
  27. #include <linux/sizes.h>
  28. #include <common.h>
  29. #include <i2c.h>
  30. #include <power/pmic.h>
  31. #include <power/pfuze3000_pmic.h>
  32. #include <malloc.h>
  33. DECLARE_GLOBAL_DATA_PTR;
  34. enum {
  35. UDOO_NEO_TYPE_BASIC,
  36. UDOO_NEO_TYPE_BASIC_KS,
  37. UDOO_NEO_TYPE_FULL,
  38. UDOO_NEO_TYPE_EXTENDED,
  39. };
  40. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  41. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  42. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  43. #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  44. PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
  45. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  46. #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  47. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  48. PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  49. PAD_CTL_ODE)
  50. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  51. PAD_CTL_SPEED_MED | \
  52. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  53. #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  54. PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  55. #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  56. PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
  57. #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
  58. PAD_CTL_DSE_40ohm)
  59. #define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  60. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  61. PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  62. #define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \
  63. MUX_MODE_SION)
  64. int dram_init(void)
  65. {
  66. gd->ram_size = imx_ddr_size();
  67. return 0;
  68. }
  69. #ifdef CONFIG_SYS_I2C_MXC
  70. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  71. /* I2C1 for PMIC */
  72. static struct i2c_pads_info i2c_pad_info1 = {
  73. .scl = {
  74. .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
  75. .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
  76. .gp = IMX_GPIO_NR(1, 0),
  77. },
  78. .sda = {
  79. .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
  80. .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
  81. .gp = IMX_GPIO_NR(1, 1),
  82. },
  83. };
  84. #endif
  85. #ifdef CONFIG_POWER
  86. int power_init_board(void)
  87. {
  88. struct pmic *p;
  89. int ret;
  90. unsigned int reg, rev_id;
  91. ret = power_pfuze3000_init(PFUZE3000_I2C_BUS);
  92. if (ret)
  93. return ret;
  94. p = pmic_get("PFUZE3000");
  95. ret = pmic_probe(p);
  96. if (ret)
  97. return ret;
  98. pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
  99. pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
  100. printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
  101. /* disable Low Power Mode during standby mode */
  102. pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
  103. reg |= 0x1;
  104. ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
  105. if (ret)
  106. return ret;
  107. ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc);
  108. if (ret)
  109. return ret;
  110. ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc);
  111. if (ret)
  112. return ret;
  113. ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc);
  114. if (ret)
  115. return ret;
  116. ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc);
  117. if (ret)
  118. return ret;
  119. /* set SW1A standby voltage 0.975V */
  120. pmic_reg_read(p, PFUZE3000_SW1ASTBY, &reg);
  121. reg &= ~0x3f;
  122. reg |= PFUZE3000_SW1AB_SETP(9750);
  123. ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
  124. if (ret)
  125. return ret;
  126. /* set SW1B standby voltage 0.975V */
  127. pmic_reg_read(p, PFUZE3000_SW1BSTBY, &reg);
  128. reg &= ~0x3f;
  129. reg |= PFUZE3000_SW1AB_SETP(9750);
  130. ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
  131. if (ret)
  132. return ret;
  133. /* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */
  134. pmic_reg_read(p, PFUZE3000_SW1ACONF, &reg);
  135. reg &= ~0xc0;
  136. reg |= 0x40;
  137. ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg);
  138. if (ret)
  139. return ret;
  140. /* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */
  141. pmic_reg_read(p, PFUZE3000_SW1BCONF, &reg);
  142. reg &= ~0xc0;
  143. reg |= 0x40;
  144. ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg);
  145. if (ret)
  146. return ret;
  147. /* set VDD_ARM_IN to 1.350V */
  148. pmic_reg_read(p, PFUZE3000_SW1AVOLT, &reg);
  149. reg &= ~0x3f;
  150. reg |= PFUZE3000_SW1AB_SETP(13500);
  151. ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg);
  152. if (ret)
  153. return ret;
  154. /* set VDD_SOC_IN to 1.350V */
  155. pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
  156. reg &= ~0x3f;
  157. reg |= PFUZE3000_SW1AB_SETP(13500);
  158. ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
  159. if (ret)
  160. return ret;
  161. /* set DDR_1_5V to 1.350V */
  162. pmic_reg_read(p, PFUZE3000_SW3VOLT, &reg);
  163. reg &= ~0x0f;
  164. reg |= PFUZE3000_SW3_SETP(13500);
  165. ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg);
  166. if (ret)
  167. return ret;
  168. /* set VGEN2_1V5 to 1.5V */
  169. pmic_reg_read(p, PFUZE3000_VLDO2CTL, &reg);
  170. reg &= ~0x0f;
  171. reg |= PFUZE3000_VLDO_SETP(15000);
  172. /* enable */
  173. reg |= 0x10;
  174. ret = pmic_reg_write(p, PFUZE3000_VLDO2CTL, reg);
  175. if (ret)
  176. return ret;
  177. return 0;
  178. }
  179. #endif
  180. static iomux_v3_cfg_t const uart1_pads[] = {
  181. MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  182. MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  183. };
  184. static iomux_v3_cfg_t const phy_control_pads[] = {
  185. /* 25MHz Ethernet PHY Clock */
  186. MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
  187. MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  188. };
  189. static iomux_v3_cfg_t const board_recognition_pads[] = {
  190. /*Connected to R184*/
  191. MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
  192. /*Connected to R185*/
  193. MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
  194. };
  195. static iomux_v3_cfg_t const wdog_b_pad = {
  196. MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  197. };
  198. static iomux_v3_cfg_t const peri_3v3_pads[] = {
  199. MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
  200. };
  201. static void setup_iomux_uart(void)
  202. {
  203. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  204. }
  205. static int setup_fec(void)
  206. {
  207. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  208. int reg;
  209. imx_iomux_v3_setup_multiple_pads(phy_control_pads,
  210. ARRAY_SIZE(phy_control_pads));
  211. /* Reset PHY */
  212. gpio_direction_output(IMX_GPIO_NR(2, 1) , 0);
  213. udelay(10000);
  214. gpio_set_value(IMX_GPIO_NR(2, 1), 1);
  215. udelay(100);
  216. reg = readl(&anatop->pll_enet);
  217. reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
  218. writel(reg, &anatop->pll_enet);
  219. return enable_fec_anatop_clock(0, ENET_25MHZ);
  220. }
  221. int board_init(void)
  222. {
  223. /* Address of boot parameters */
  224. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  225. /*
  226. * Because kernel set WDOG_B mux before pad with the commone pinctrl
  227. * framwork now and wdog reset will be triggered once set WDOG_B mux
  228. * with default pad setting, we set pad setting here to workaround this.
  229. * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
  230. * as GPIO mux firstly here to workaround it.
  231. */
  232. imx_iomux_v3_setup_pad(wdog_b_pad);
  233. /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
  234. imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
  235. ARRAY_SIZE(peri_3v3_pads));
  236. /* Active high for ncp692 */
  237. gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
  238. #ifdef CONFIG_SYS_I2C_MXC
  239. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  240. #endif
  241. return 0;
  242. }
  243. static int get_board_value(void)
  244. {
  245. int r184, r185;
  246. imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
  247. ARRAY_SIZE(board_recognition_pads));
  248. gpio_direction_input(IMX_GPIO_NR(4, 13));
  249. gpio_direction_input(IMX_GPIO_NR(4, 0));
  250. r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
  251. r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
  252. /*
  253. * Machine selection -
  254. * Machine r184, r185
  255. * ---------------------------------
  256. * Basic 0 0
  257. * Basic Ks 0 1
  258. * Full 1 0
  259. * Extended 1 1
  260. */
  261. return (r184 << 1) + r185;
  262. }
  263. int board_early_init_f(void)
  264. {
  265. setup_iomux_uart();
  266. setup_fec();
  267. return 0;
  268. }
  269. static char *board_string(void)
  270. {
  271. switch (get_board_value()) {
  272. case UDOO_NEO_TYPE_BASIC:
  273. return "BASIC";
  274. case UDOO_NEO_TYPE_BASIC_KS:
  275. return "BASICKS";
  276. case UDOO_NEO_TYPE_FULL:
  277. return "FULL";
  278. case UDOO_NEO_TYPE_EXTENDED:
  279. return "EXTENDED";
  280. }
  281. return "UNDEFINED";
  282. }
  283. int checkboard(void)
  284. {
  285. printf("Board: UDOO Neo %s\n", board_string());
  286. return 0;
  287. }
  288. int board_late_init(void)
  289. {
  290. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  291. env_set("board_name", board_string());
  292. #endif
  293. return 0;
  294. }
  295. #ifdef CONFIG_SPL_BUILD
  296. #include <linux/libfdt.h>
  297. #include <asm/arch/mx6-ddr.h>
  298. static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
  299. .dram_dqm0 = 0x00000028,
  300. .dram_dqm1 = 0x00000028,
  301. .dram_dqm2 = 0x00000028,
  302. .dram_dqm3 = 0x00000028,
  303. .dram_ras = 0x00000020,
  304. .dram_cas = 0x00000020,
  305. .dram_odt0 = 0x00000020,
  306. .dram_odt1 = 0x00000020,
  307. .dram_sdba2 = 0x00000000,
  308. .dram_sdcke0 = 0x00003000,
  309. .dram_sdcke1 = 0x00003000,
  310. .dram_sdclk_0 = 0x00000030,
  311. .dram_sdqs0 = 0x00000028,
  312. .dram_sdqs1 = 0x00000028,
  313. .dram_sdqs2 = 0x00000028,
  314. .dram_sdqs3 = 0x00000028,
  315. .dram_reset = 0x00000020,
  316. };
  317. static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
  318. .grp_addds = 0x00000020,
  319. .grp_ddrmode_ctl = 0x00020000,
  320. .grp_ddrpke = 0x00000000,
  321. .grp_ddrmode = 0x00020000,
  322. .grp_b0ds = 0x00000028,
  323. .grp_b1ds = 0x00000028,
  324. .grp_ctlds = 0x00000020,
  325. .grp_ddr_type = 0x000c0000,
  326. .grp_b2ds = 0x00000028,
  327. .grp_b3ds = 0x00000028,
  328. };
  329. static const struct mx6_mmdc_calibration neo_mmcd_calib = {
  330. .p0_mpwldectrl0 = 0x000E000B,
  331. .p0_mpwldectrl1 = 0x000E0010,
  332. .p0_mpdgctrl0 = 0x41600158,
  333. .p0_mpdgctrl1 = 0x01500140,
  334. .p0_mprddlctl = 0x3A383E3E,
  335. .p0_mpwrdlctl = 0x3A383C38,
  336. };
  337. static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
  338. .p0_mpwldectrl0 = 0x001E0022,
  339. .p0_mpwldectrl1 = 0x001C0019,
  340. .p0_mpdgctrl0 = 0x41540150,
  341. .p0_mpdgctrl1 = 0x01440138,
  342. .p0_mprddlctl = 0x403E4644,
  343. .p0_mpwrdlctl = 0x3C3A4038,
  344. };
  345. /* MT41K256M16 */
  346. static struct mx6_ddr3_cfg neo_mem_ddr = {
  347. .mem_speed = 1600,
  348. .density = 4,
  349. .width = 16,
  350. .banks = 8,
  351. .rowaddr = 15,
  352. .coladdr = 10,
  353. .pagesz = 2,
  354. .trcd = 1375,
  355. .trcmin = 4875,
  356. .trasmin = 3500,
  357. };
  358. /* MT41K128M16 */
  359. static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
  360. .mem_speed = 1600,
  361. .density = 2,
  362. .width = 16,
  363. .banks = 8,
  364. .rowaddr = 14,
  365. .coladdr = 10,
  366. .pagesz = 2,
  367. .trcd = 1375,
  368. .trcmin = 4875,
  369. .trasmin = 3500,
  370. };
  371. static void ccgr_init(void)
  372. {
  373. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  374. writel(0xFFFFFFFF, &ccm->CCGR0);
  375. writel(0xFFFFFFFF, &ccm->CCGR1);
  376. writel(0xFFFFFFFF, &ccm->CCGR2);
  377. writel(0xFFFFFFFF, &ccm->CCGR3);
  378. writel(0xFFFFFFFF, &ccm->CCGR4);
  379. writel(0xFFFFFFFF, &ccm->CCGR5);
  380. writel(0xFFFFFFFF, &ccm->CCGR6);
  381. writel(0xFFFFFFFF, &ccm->CCGR7);
  382. }
  383. static void spl_dram_init(void)
  384. {
  385. int board = get_board_value();
  386. struct mx6_ddr_sysinfo sysinfo = {
  387. .dsize = 1, /* width of data bus: 1 = 32 bits */
  388. .cs_density = 24,
  389. .ncs = 1,
  390. .cs1_mirror = 0,
  391. .rtt_wr = 2,
  392. .rtt_nom = 2, /* RTT_Nom = RZQ/2 */
  393. .walat = 1, /* Write additional latency */
  394. .ralat = 5, /* Read additional latency */
  395. .mif3_mode = 3, /* Command prediction working mode */
  396. .bi_on = 1, /* Bank interleaving enabled */
  397. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  398. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  399. };
  400. mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  401. if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS)
  402. mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
  403. &neo_basic_mem_ddr);
  404. else
  405. mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
  406. }
  407. void board_init_f(ulong dummy)
  408. {
  409. ccgr_init();
  410. /* setup AIPS and disable watchdog */
  411. arch_cpu_init();
  412. board_early_init_f();
  413. /* setup GP timer */
  414. timer_init();
  415. /* UART clocks enabled and gd valid - init serial console */
  416. preloader_console_init();
  417. /* DDR initialization */
  418. spl_dram_init();
  419. /* Clear the BSS. */
  420. memset(__bss_start, 0, __bss_end - __bss_start);
  421. /* load/boot image from boot device */
  422. board_init_r(NULL, 0);
  423. }
  424. #endif