qe.c 11 KB

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  1. /*
  2. * Copyright (C) 2006 Freescale Semiconductor, Inc.
  3. *
  4. * Dave Liu <daveliu@freescale.com>
  5. * based on source code of Shlomi Gridish
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include "common.h"
  23. #include <command.h>
  24. #include "asm/errno.h"
  25. #include "asm/io.h"
  26. #include "asm/immap_qe.h"
  27. #include "qe.h"
  28. #if defined(CONFIG_QE)
  29. qe_map_t *qe_immr = NULL;
  30. static qe_snum_t snums[QE_NUM_OF_SNUM];
  31. DECLARE_GLOBAL_DATA_PTR;
  32. void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
  33. {
  34. u32 cecr;
  35. if (cmd == QE_RESET) {
  36. out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG));
  37. } else {
  38. out_be32(&qe_immr->cp.cecdr, cmd_data);
  39. out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG |
  40. ((u32) mcn<<QE_CR_PROTOCOL_SHIFT) | cmd));
  41. }
  42. /* Wait for the QE_CR_FLG to clear */
  43. do {
  44. cecr = in_be32(&qe_immr->cp.cecr);
  45. } while (cecr & QE_CR_FLG);
  46. return;
  47. }
  48. uint qe_muram_alloc(uint size, uint align)
  49. {
  50. uint retloc;
  51. uint align_mask, off;
  52. uint savebase;
  53. align_mask = align - 1;
  54. savebase = gd->mp_alloc_base;
  55. if ((off = (gd->mp_alloc_base & align_mask)) != 0)
  56. gd->mp_alloc_base += (align - off);
  57. if ((off = size & align_mask) != 0)
  58. size += (align - off);
  59. if ((gd->mp_alloc_base + size) >= gd->mp_alloc_top) {
  60. gd->mp_alloc_base = savebase;
  61. printf("%s: ran out of ram.\n", __FUNCTION__);
  62. }
  63. retloc = gd->mp_alloc_base;
  64. gd->mp_alloc_base += size;
  65. memset((void *)&qe_immr->muram[retloc], 0, size);
  66. __asm__ __volatile__("sync");
  67. return retloc;
  68. }
  69. void *qe_muram_addr(uint offset)
  70. {
  71. return (void *)&qe_immr->muram[offset];
  72. }
  73. static void qe_sdma_init(void)
  74. {
  75. volatile sdma_t *p;
  76. uint sdma_buffer_base;
  77. p = (volatile sdma_t *)&qe_immr->sdma;
  78. /* All of DMA transaction in bus 1 */
  79. out_be32(&p->sdaqr, 0);
  80. out_be32(&p->sdaqmr, 0);
  81. /* Allocate 2KB temporary buffer for sdma */
  82. sdma_buffer_base = qe_muram_alloc(2048, 4096);
  83. out_be32(&p->sdwbcr, sdma_buffer_base & QE_SDEBCR_BA_MASK);
  84. /* Clear sdma status */
  85. out_be32(&p->sdsr, 0x03000000);
  86. /* Enable global mode on bus 1, and 2KB buffer size */
  87. out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT));
  88. }
  89. static u8 thread_snum[QE_NUM_OF_SNUM] = {
  90. 0x04, 0x05, 0x0c, 0x0d,
  91. 0x14, 0x15, 0x1c, 0x1d,
  92. 0x24, 0x25, 0x2c, 0x2d,
  93. 0x34, 0x35, 0x88, 0x89,
  94. 0x98, 0x99, 0xa8, 0xa9,
  95. 0xb8, 0xb9, 0xc8, 0xc9,
  96. 0xd8, 0xd9, 0xe8, 0xe9
  97. };
  98. static void qe_snums_init(void)
  99. {
  100. int i;
  101. for (i = 0; i < QE_NUM_OF_SNUM; i++) {
  102. snums[i].state = QE_SNUM_STATE_FREE;
  103. snums[i].num = thread_snum[i];
  104. }
  105. }
  106. int qe_get_snum(void)
  107. {
  108. int snum = -EBUSY;
  109. int i;
  110. for (i = 0; i < QE_NUM_OF_SNUM; i++) {
  111. if (snums[i].state == QE_SNUM_STATE_FREE) {
  112. snums[i].state = QE_SNUM_STATE_USED;
  113. snum = snums[i].num;
  114. break;
  115. }
  116. }
  117. return snum;
  118. }
  119. void qe_put_snum(u8 snum)
  120. {
  121. int i;
  122. for (i = 0; i < QE_NUM_OF_SNUM; i++) {
  123. if (snums[i].num == snum) {
  124. snums[i].state = QE_SNUM_STATE_FREE;
  125. break;
  126. }
  127. }
  128. }
  129. void qe_init(uint qe_base)
  130. {
  131. /* Init the QE IMMR base */
  132. qe_immr = (qe_map_t *)qe_base;
  133. gd->mp_alloc_base = QE_DATAONLY_BASE;
  134. gd->mp_alloc_top = gd->mp_alloc_base + QE_DATAONLY_SIZE;
  135. qe_sdma_init();
  136. qe_snums_init();
  137. }
  138. void qe_reset(void)
  139. {
  140. qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
  141. (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
  142. }
  143. void qe_assign_page(uint snum, uint para_ram_base)
  144. {
  145. u32 cecr;
  146. out_be32(&qe_immr->cp.cecdr, para_ram_base);
  147. out_be32(&qe_immr->cp.cecr, ((u32) snum<<QE_CR_ASSIGN_PAGE_SNUM_SHIFT)
  148. | QE_CR_FLG | QE_ASSIGN_PAGE);
  149. /* Wait for the QE_CR_FLG to clear */
  150. do {
  151. cecr = in_be32(&qe_immr->cp.cecr);
  152. } while (cecr & QE_CR_FLG );
  153. return;
  154. }
  155. /*
  156. * brg: 0~15 as BRG1~BRG16
  157. rate: baud rate
  158. * BRG input clock comes from the BRGCLK (internal clock generated from
  159. the QE clock, it is one-half of the QE clock), If need the clock source
  160. from CLKn pin, we have te change the function.
  161. */
  162. #define BRG_CLK (gd->brg_clk)
  163. int qe_set_brg(uint brg, uint rate)
  164. {
  165. volatile uint *bp;
  166. u32 divisor;
  167. int div16 = 0;
  168. if (brg >= QE_NUM_OF_BRGS)
  169. return -EINVAL;
  170. bp = (uint *)&qe_immr->brg.brgc1;
  171. bp += brg;
  172. divisor = (BRG_CLK / rate);
  173. if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
  174. div16 = 1;
  175. divisor /= 16;
  176. }
  177. *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
  178. __asm__ __volatile__("sync");
  179. if (div16) {
  180. *bp |= QE_BRGC_DIV16;
  181. __asm__ __volatile__("sync");
  182. }
  183. return 0;
  184. }
  185. /* Set ethernet MII clock master
  186. */
  187. int qe_set_mii_clk_src(int ucc_num)
  188. {
  189. u32 cmxgcr;
  190. /* check if the UCC number is in range. */
  191. if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
  192. printf("%s: ucc num not in ranges\n", __FUNCTION__);
  193. return -EINVAL;
  194. }
  195. cmxgcr = in_be32(&qe_immr->qmx.cmxgcr);
  196. cmxgcr &= ~QE_CMXGCR_MII_ENET_MNG_MASK;
  197. cmxgcr |= (ucc_num <<QE_CMXGCR_MII_ENET_MNG_SHIFT);
  198. out_be32(&qe_immr->qmx.cmxgcr, cmxgcr);
  199. return 0;
  200. }
  201. /* The maximum number of RISCs we support */
  202. #define MAX_QE_RISC 2
  203. /* Firmware information stored here for qe_get_firmware_info() */
  204. static struct qe_firmware_info qe_firmware_info;
  205. /*
  206. * Set to 1 if QE firmware has been uploaded, and therefore
  207. * qe_firmware_info contains valid data.
  208. */
  209. static int qe_firmware_uploaded;
  210. /*
  211. * Upload a QE microcode
  212. *
  213. * This function is a worker function for qe_upload_firmware(). It does
  214. * the actual uploading of the microcode.
  215. */
  216. static void qe_upload_microcode(const void *base,
  217. const struct qe_microcode *ucode)
  218. {
  219. const u32 *code = base + be32_to_cpu(ucode->code_offset);
  220. unsigned int i;
  221. if (ucode->major || ucode->minor || ucode->revision)
  222. printf("QE: uploading microcode '%s' version %u.%u.%u\n",
  223. ucode->id, ucode->major, ucode->minor, ucode->revision);
  224. else
  225. printf("QE: uploading microcode '%s'\n", ucode->id);
  226. /* Use auto-increment */
  227. out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
  228. QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
  229. for (i = 0; i < be32_to_cpu(ucode->count); i++)
  230. out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
  231. }
  232. /*
  233. * Upload a microcode to the I-RAM at a specific address.
  234. *
  235. * See docs/README.qe_firmware for information on QE microcode uploading.
  236. *
  237. * Currently, only version 1 is supported, so the 'version' field must be
  238. * set to 1.
  239. *
  240. * The SOC model and revision are not validated, they are only displayed for
  241. * informational purposes.
  242. *
  243. * 'calc_size' is the calculated size, in bytes, of the firmware structure and
  244. * all of the microcode structures, minus the CRC.
  245. *
  246. * 'length' is the size that the structure says it is, including the CRC.
  247. */
  248. int qe_upload_firmware(const struct qe_firmware *firmware)
  249. {
  250. unsigned int i;
  251. unsigned int j;
  252. u32 crc;
  253. size_t calc_size = sizeof(struct qe_firmware);
  254. size_t length;
  255. const struct qe_header *hdr;
  256. if (!firmware) {
  257. printf("Invalid address\n");
  258. return -EINVAL;
  259. }
  260. hdr = &firmware->header;
  261. length = be32_to_cpu(hdr->length);
  262. /* Check the magic */
  263. if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
  264. (hdr->magic[2] != 'F')) {
  265. printf("Not a microcode\n");
  266. return -EPERM;
  267. }
  268. /* Check the version */
  269. if (hdr->version != 1) {
  270. printf("Unsupported version\n");
  271. return -EPERM;
  272. }
  273. /* Validate some of the fields */
  274. if ((firmware->count < 1) || (firmware->count >= MAX_QE_RISC)) {
  275. printf("Invalid data\n");
  276. return -EINVAL;
  277. }
  278. /* Validate the length and check if there's a CRC */
  279. calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
  280. for (i = 0; i < firmware->count; i++)
  281. /*
  282. * For situations where the second RISC uses the same microcode
  283. * as the first, the 'code_offset' and 'count' fields will be
  284. * zero, so it's okay to add those.
  285. */
  286. calc_size += sizeof(u32) *
  287. be32_to_cpu(firmware->microcode[i].count);
  288. /* Validate the length */
  289. if (length != calc_size + sizeof(u32)) {
  290. printf("Invalid length\n");
  291. return -EPERM;
  292. }
  293. /*
  294. * Validate the CRC. We would normally call crc32_no_comp(), but that
  295. * function isn't available unless you turn on JFFS support.
  296. */
  297. crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
  298. if (crc != (crc32(-1, (const void *) firmware, calc_size) ^ -1)) {
  299. printf("Firmware CRC is invalid\n");
  300. return -EIO;
  301. }
  302. /*
  303. * If the microcode calls for it, split the I-RAM.
  304. */
  305. if (!firmware->split) {
  306. out_be16(&qe_immr->cp.cercr,
  307. in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
  308. }
  309. if (firmware->soc.model)
  310. printf("Firmware '%s' for %u V%u.%u\n",
  311. firmware->id, be16_to_cpu(firmware->soc.model),
  312. firmware->soc.major, firmware->soc.minor);
  313. else
  314. printf("Firmware '%s'\n", firmware->id);
  315. /*
  316. * The QE only supports one microcode per RISC, so clear out all the
  317. * saved microcode information and put in the new.
  318. */
  319. memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
  320. strcpy(qe_firmware_info.id, firmware->id);
  321. qe_firmware_info.extended_modes = firmware->extended_modes;
  322. memcpy(qe_firmware_info.vtraps, firmware->vtraps,
  323. sizeof(firmware->vtraps));
  324. qe_firmware_uploaded = 1;
  325. /* Loop through each microcode. */
  326. for (i = 0; i < firmware->count; i++) {
  327. const struct qe_microcode *ucode = &firmware->microcode[i];
  328. /* Upload a microcode if it's present */
  329. if (ucode->code_offset)
  330. qe_upload_microcode(firmware, ucode);
  331. /* Program the traps for this processor */
  332. for (j = 0; j < 16; j++) {
  333. u32 trap = be32_to_cpu(ucode->traps[j]);
  334. if (trap)
  335. out_be32(&qe_immr->rsp[i].tibcr[j], trap);
  336. }
  337. /* Enable traps */
  338. out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
  339. }
  340. return 0;
  341. }
  342. struct qe_firmware_info *qe_get_firmware_info(void)
  343. {
  344. return qe_firmware_uploaded ? &qe_firmware_info : NULL;
  345. }
  346. static int qe_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  347. {
  348. ulong addr;
  349. if (argc < 3) {
  350. printf ("Usage:\n%s\n", cmdtp->usage);
  351. return 1;
  352. }
  353. if (strcmp(argv[1], "fw") == 0) {
  354. addr = simple_strtoul(argv[2], NULL, 16);
  355. if (!addr) {
  356. printf("Invalid address\n");
  357. return -EINVAL;
  358. }
  359. /*
  360. * If a length was supplied, compare that with the 'length'
  361. * field.
  362. */
  363. if (argc > 3) {
  364. ulong length = simple_strtoul(argv[3], NULL, 16);
  365. struct qe_firmware *firmware = (void *) addr;
  366. if (length != be32_to_cpu(firmware->header.length)) {
  367. printf("Length mismatch\n");
  368. return -EINVAL;
  369. }
  370. }
  371. return qe_upload_firmware((const struct qe_firmware *) addr);
  372. }
  373. printf ("Usage:\n%s\n", cmdtp->usage);
  374. return 1;
  375. }
  376. U_BOOT_CMD(
  377. qe, 4, 0, qe_cmd,
  378. "qe - QUICC Engine commands\n",
  379. "fw <addr> [<length>] - Upload firmware binary at address <addr> to "
  380. "the QE,\n\twith optional length <length> verification.\n"
  381. );
  382. #endif /* CONFIG_QE */