sbc8548.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568
  1. /*
  2. * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
  3. * Copyright 2007 Embedded Specialties, Inc.
  4. *
  5. * Copyright 2004, 2007 Freescale Semiconductor.
  6. *
  7. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #include <common.h>
  28. #include <pci.h>
  29. #include <asm/processor.h>
  30. #include <asm/immap_85xx.h>
  31. #include <asm/immap_fsl_pci.h>
  32. #include <spd.h>
  33. #include <miiphy.h>
  34. #include <libfdt.h>
  35. #include <fdt_support.h>
  36. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  37. extern void ddr_enable_ecc(unsigned int dram_size);
  38. #endif
  39. DECLARE_GLOBAL_DATA_PTR;
  40. extern long int spd_sdram(void);
  41. void local_bus_init(void);
  42. void sdram_init(void);
  43. long int fixed_sdram (void);
  44. int board_early_init_f (void)
  45. {
  46. return 0;
  47. }
  48. int checkboard (void)
  49. {
  50. volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
  51. volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
  52. printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
  53. (volatile)(*(u_char *)CFG_BD_REV) >> 4);
  54. /*
  55. * Initialize local bus.
  56. */
  57. local_bus_init ();
  58. /*
  59. * Fix CPU2 errata: A core hang possible while executing a
  60. * msync instruction and a snoopable transaction from an I/O
  61. * master tagged to make quick forward progress is present.
  62. */
  63. ecm->eebpcr |= (1 << 16);
  64. /*
  65. * Hack TSEC 3 and 4 IO voltages.
  66. */
  67. gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
  68. ecm->eedr = 0xffffffff; /* clear ecm errors */
  69. ecm->eeer = 0xffffffff; /* enable ecm errors */
  70. return 0;
  71. }
  72. long int
  73. initdram(int board_type)
  74. {
  75. long dram_size = 0;
  76. puts("Initializing\n");
  77. #if defined(CONFIG_DDR_DLL)
  78. {
  79. /*
  80. * Work around to stabilize DDR DLL MSYNC_IN.
  81. * Errata DDR9 seems to have been fixed.
  82. * This is now the workaround for Errata DDR11:
  83. * Override DLL = 1, Course Adj = 1, Tap Select = 0
  84. */
  85. volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
  86. gur->ddrdllcr = 0x81000000;
  87. asm("sync;isync;msync");
  88. udelay(200);
  89. }
  90. #endif
  91. #if defined(CONFIG_SPD_EEPROM)
  92. dram_size = spd_sdram ();
  93. #else
  94. dram_size = fixed_sdram ();
  95. #endif
  96. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  97. /*
  98. * Initialize and enable DDR ECC.
  99. */
  100. ddr_enable_ecc(dram_size);
  101. #endif
  102. /*
  103. * SDRAM Initialization
  104. */
  105. sdram_init();
  106. puts(" DDR: ");
  107. return dram_size;
  108. }
  109. /*
  110. * Initialize Local Bus
  111. */
  112. void
  113. local_bus_init(void)
  114. {
  115. volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
  116. volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
  117. uint clkdiv;
  118. uint lbc_hz;
  119. sys_info_t sysinfo;
  120. get_sys_info(&sysinfo);
  121. clkdiv = (lbc->lcrr & 0x0f) * 2;
  122. lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
  123. gur->lbiuiplldcr1 = 0x00078080;
  124. if (clkdiv == 16) {
  125. gur->lbiuiplldcr0 = 0x7c0f1bf0;
  126. } else if (clkdiv == 8) {
  127. gur->lbiuiplldcr0 = 0x6c0f1bf0;
  128. } else if (clkdiv == 4) {
  129. gur->lbiuiplldcr0 = 0x5c0f1bf0;
  130. }
  131. lbc->lcrr |= 0x00030000;
  132. asm("sync;isync;msync");
  133. lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
  134. lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
  135. }
  136. /*
  137. * Initialize SDRAM memory on the Local Bus.
  138. */
  139. void
  140. sdram_init(void)
  141. {
  142. #if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
  143. uint idx;
  144. volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
  145. uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
  146. uint lsdmr_common;
  147. puts(" SDRAM: ");
  148. print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
  149. /*
  150. * Setup SDRAM Base and Option Registers
  151. */
  152. lbc->or3 = CFG_OR3_PRELIM;
  153. asm("msync");
  154. lbc->br3 = CFG_BR3_PRELIM;
  155. asm("msync");
  156. lbc->lbcr = CFG_LBC_LBCR;
  157. asm("msync");
  158. lbc->lsrt = CFG_LBC_LSRT;
  159. lbc->mrtpr = CFG_LBC_MRTPR;
  160. asm("msync");
  161. /*
  162. * MPC8548 uses "new" 15-16 style addressing.
  163. */
  164. lsdmr_common = CFG_LBC_LSDMR_COMMON;
  165. lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
  166. /*
  167. * Issue PRECHARGE ALL command.
  168. */
  169. lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
  170. asm("sync;msync");
  171. *sdram_addr = 0xff;
  172. ppcDcbf((unsigned long) sdram_addr);
  173. udelay(100);
  174. /*
  175. * Issue 8 AUTO REFRESH commands.
  176. */
  177. for (idx = 0; idx < 8; idx++) {
  178. lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
  179. asm("sync;msync");
  180. *sdram_addr = 0xff;
  181. ppcDcbf((unsigned long) sdram_addr);
  182. udelay(100);
  183. }
  184. /*
  185. * Issue 8 MODE-set command.
  186. */
  187. lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
  188. asm("sync;msync");
  189. *sdram_addr = 0xff;
  190. ppcDcbf((unsigned long) sdram_addr);
  191. udelay(100);
  192. /*
  193. * Issue NORMAL OP command.
  194. */
  195. lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
  196. asm("sync;msync");
  197. *sdram_addr = 0xff;
  198. ppcDcbf((unsigned long) sdram_addr);
  199. udelay(200); /* Overkill. Must wait > 200 bus cycles */
  200. #endif /* enable SDRAM init */
  201. }
  202. #if defined(CFG_DRAM_TEST)
  203. int
  204. testdram(void)
  205. {
  206. uint *pstart = (uint *) CFG_MEMTEST_START;
  207. uint *pend = (uint *) CFG_MEMTEST_END;
  208. uint *p;
  209. printf("Testing DRAM from 0x%08x to 0x%08x\n",
  210. CFG_MEMTEST_START,
  211. CFG_MEMTEST_END);
  212. printf("DRAM test phase 1:\n");
  213. for (p = pstart; p < pend; p++)
  214. *p = 0xaaaaaaaa;
  215. for (p = pstart; p < pend; p++) {
  216. if (*p != 0xaaaaaaaa) {
  217. printf ("DRAM test fails at: %08x\n", (uint) p);
  218. return 1;
  219. }
  220. }
  221. printf("DRAM test phase 2:\n");
  222. for (p = pstart; p < pend; p++)
  223. *p = 0x55555555;
  224. for (p = pstart; p < pend; p++) {
  225. if (*p != 0x55555555) {
  226. printf ("DRAM test fails at: %08x\n", (uint) p);
  227. return 1;
  228. }
  229. }
  230. printf("DRAM test passed.\n");
  231. return 0;
  232. }
  233. #endif
  234. #if !defined(CONFIG_SPD_EEPROM)
  235. /*************************************************************************
  236. * fixed_sdram init -- doesn't use serial presence detect.
  237. * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
  238. ************************************************************************/
  239. long int fixed_sdram (void)
  240. {
  241. #define CFG_DDR_CONTROL 0xc300c000
  242. volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
  243. ddr->cs0_bnds = 0x0000007f;
  244. ddr->cs1_bnds = 0x008000ff;
  245. ddr->cs2_bnds = 0x00000000;
  246. ddr->cs3_bnds = 0x00000000;
  247. ddr->cs0_config = 0x80010101;
  248. ddr->cs1_config = 0x80010101;
  249. ddr->cs2_config = 0x00000000;
  250. ddr->cs3_config = 0x00000000;
  251. ddr->ext_refrec = 0x00000000;
  252. ddr->timing_cfg_0 = 0x00220802;
  253. ddr->timing_cfg_1 = 0x38377322;
  254. ddr->timing_cfg_2 = 0x0fa044C7;
  255. ddr->sdram_cfg = 0x4300C000;
  256. ddr->sdram_cfg_2 = 0x24401000;
  257. ddr->sdram_mode = 0x23C00542;
  258. ddr->sdram_mode_2 = 0x00000000;
  259. ddr->sdram_interval = 0x05080100;
  260. ddr->sdram_md_cntl = 0x00000000;
  261. ddr->sdram_data_init = 0x00000000;
  262. ddr->sdram_clk_cntl = 0x03800000;
  263. asm("sync;isync;msync");
  264. udelay(500);
  265. #if defined (CONFIG_DDR_ECC)
  266. /* Enable ECC checking */
  267. ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
  268. #else
  269. ddr->sdram_cfg = CFG_DDR_CONTROL;
  270. #endif
  271. return CFG_SDRAM_SIZE * 1024 * 1024;
  272. }
  273. #endif
  274. #if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
  275. /* For some reason the Tundra PCI bridge shows up on itself as a
  276. * different device. Work around that by refusing to configure it.
  277. */
  278. void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
  279. static struct pci_config_table pci_sbc8548_config_table[] = {
  280. {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
  281. {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
  282. {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
  283. mpc85xx_config_via_usbide, {0,0,0}},
  284. {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
  285. mpc85xx_config_via_usb, {0,0,0}},
  286. {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
  287. mpc85xx_config_via_usb2, {0,0,0}},
  288. {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
  289. mpc85xx_config_via_power, {0,0,0}},
  290. {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
  291. mpc85xx_config_via_ac97, {0,0,0}},
  292. {},
  293. };
  294. static struct pci_controller pci1_hose = {
  295. config_table: pci_sbc8548_config_table};
  296. #endif /* CONFIG_PCI */
  297. #ifdef CONFIG_PCI2
  298. static struct pci_controller pci2_hose;
  299. #endif /* CONFIG_PCI2 */
  300. #ifdef CONFIG_PCIE1
  301. static struct pci_controller pcie1_hose;
  302. #endif /* CONFIG_PCIE1 */
  303. int first_free_busno=0;
  304. void
  305. pci_init_board(void)
  306. {
  307. volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
  308. #ifdef CONFIG_PCI1
  309. {
  310. volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
  311. extern void fsl_pci_init(struct pci_controller *hose);
  312. struct pci_controller *hose = &pci1_hose;
  313. struct pci_config_table *table;
  314. uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
  315. uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
  316. uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
  317. uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
  318. uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
  319. if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
  320. printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
  321. (pci_32) ? 32 : 64,
  322. (pci_speed == 33333000) ? "33" :
  323. (pci_speed == 66666000) ? "66" : "unknown",
  324. pci_clk_sel ? "sync" : "async",
  325. pci_agent ? "agent" : "host",
  326. pci_arb ? "arbiter" : "external-arbiter"
  327. );
  328. /* inbound */
  329. pci_set_region(hose->regions + 0,
  330. CFG_PCI_MEMORY_BUS,
  331. CFG_PCI_MEMORY_PHYS,
  332. CFG_PCI_MEMORY_SIZE,
  333. PCI_REGION_MEM | PCI_REGION_MEMORY);
  334. /* outbound memory */
  335. pci_set_region(hose->regions + 1,
  336. CFG_PCI1_MEM_BASE,
  337. CFG_PCI1_MEM_PHYS,
  338. CFG_PCI1_MEM_SIZE,
  339. PCI_REGION_MEM);
  340. /* outbound io */
  341. pci_set_region(hose->regions + 2,
  342. CFG_PCI1_IO_BASE,
  343. CFG_PCI1_IO_PHYS,
  344. CFG_PCI1_IO_SIZE,
  345. PCI_REGION_IO);
  346. hose->region_count = 3;
  347. /* relocate config table pointers */
  348. hose->config_table = \
  349. (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
  350. for (table = hose->config_table; table && table->vendor; table++)
  351. table->config_device += gd->reloc_off;
  352. hose->first_busno=first_free_busno;
  353. pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
  354. fsl_pci_init(hose);
  355. first_free_busno=hose->last_busno+1;
  356. printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
  357. #ifdef CONFIG_PCIX_CHECK
  358. if (!(gur->pordevsr & PORDEVSR_PCI)) {
  359. /* PCI-X init */
  360. if (CONFIG_SYS_CLK_FREQ < 66000000)
  361. printf("PCI-X will only work at 66 MHz\n");
  362. reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
  363. | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
  364. pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
  365. }
  366. #endif
  367. } else {
  368. printf (" PCI: disabled\n");
  369. }
  370. }
  371. #else
  372. gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
  373. #endif
  374. #ifdef CONFIG_PCI2
  375. {
  376. uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
  377. uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
  378. if (pci_dual) {
  379. printf (" PCI2: 32 bit, 66 MHz, %s\n",
  380. pci2_clk_sel ? "sync" : "async");
  381. } else {
  382. printf (" PCI2: disabled\n");
  383. }
  384. }
  385. #else
  386. gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
  387. #endif /* CONFIG_PCI2 */
  388. #ifdef CONFIG_PCIE1
  389. {
  390. volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
  391. extern void fsl_pci_init(struct pci_controller *hose);
  392. struct pci_controller *hose = &pcie1_hose;
  393. int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
  394. int pcie_configured = io_sel >= 1;
  395. if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
  396. printf ("\n PCIE connected to slot as %s (base address %x)",
  397. pcie_ep ? "End Point" : "Root Complex",
  398. (uint)pci);
  399. if (pci->pme_msg_det) {
  400. pci->pme_msg_det = 0xffffffff;
  401. debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
  402. }
  403. printf ("\n");
  404. /* inbound */
  405. pci_set_region(hose->regions + 0,
  406. CFG_PCI_MEMORY_BUS,
  407. CFG_PCI_MEMORY_PHYS,
  408. CFG_PCI_MEMORY_SIZE,
  409. PCI_REGION_MEM | PCI_REGION_MEMORY);
  410. /* outbound memory */
  411. pci_set_region(hose->regions + 1,
  412. CFG_PCIE1_MEM_BASE,
  413. CFG_PCIE1_MEM_PHYS,
  414. CFG_PCIE1_MEM_SIZE,
  415. PCI_REGION_MEM);
  416. /* outbound io */
  417. pci_set_region(hose->regions + 2,
  418. CFG_PCIE1_IO_BASE,
  419. CFG_PCIE1_IO_PHYS,
  420. CFG_PCIE1_IO_SIZE,
  421. PCI_REGION_IO);
  422. hose->region_count = 3;
  423. hose->first_busno=first_free_busno;
  424. pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
  425. fsl_pci_init(hose);
  426. printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
  427. first_free_busno=hose->last_busno+1;
  428. } else {
  429. printf (" PCIE: disabled\n");
  430. }
  431. }
  432. #else
  433. gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
  434. #endif
  435. }
  436. int last_stage_init(void)
  437. {
  438. return 0;
  439. }
  440. #if defined(CONFIG_OF_BOARD_SETUP)
  441. void
  442. ft_pci_setup(void *blob, bd_t *bd)
  443. {
  444. int node, tmp[2];
  445. const char *path;
  446. node = fdt_path_offset(blob, "/aliases");
  447. tmp[0] = 0;
  448. if (node >= 0) {
  449. #ifdef CONFIG_PCI1
  450. path = fdt_getprop(blob, node, "pci0", NULL);
  451. if (path) {
  452. tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
  453. do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
  454. }
  455. #endif
  456. #ifdef CONFIG_PCIE1
  457. path = fdt_getprop(blob, node, "pci1", NULL);
  458. if (path) {
  459. tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
  460. do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
  461. }
  462. #endif
  463. }
  464. }
  465. #endif
  466. #if defined(CONFIG_OF_BOARD_SETUP)
  467. void
  468. ft_board_setup(void *blob, bd_t *bd)
  469. {
  470. ft_cpu_setup(blob, bd);
  471. #ifdef CONFIG_PCI
  472. ft_pci_setup(blob, bd);
  473. #endif
  474. }
  475. #endif