init.S 7.0 KB

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  1. /*
  2. * Copyright 2007
  3. * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
  4. * Copyright 2004, 2007 Freescale Semiconductor.
  5. * Copyright 2002,2003, Motorola Inc.
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <ppc_asm.tmpl>
  26. #include <ppc_defs.h>
  27. #include <asm/cache.h>
  28. #include <asm/mmu.h>
  29. #include <config.h>
  30. #include <mpc85xx.h>
  31. #define LAWAR_TRGT_PCI1 0x00000000
  32. #define LAWAR_TRGT_PCI2 0x00100000
  33. #define LAWAR_TRGT_PCIE 0x00200000
  34. #define LAWAR_TRGT_DDR 0x00f00000
  35. /*
  36. * TLB0 and TLB1 Entries
  37. *
  38. * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
  39. * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
  40. * these TLB entries are established.
  41. *
  42. * The TLB entries for DDR are dynamically setup in spd_sdram()
  43. * and use TLB1 Entries 8 through 15 as needed according to the
  44. * size of DDR memory.
  45. *
  46. * MAS0: tlbsel, esel, nv
  47. * MAS1: valid, iprot, tid, ts, tsize
  48. * MAS2: epn, x0, x1, w, i, m, g, e
  49. * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  50. */
  51. #define entry_start \
  52. mflr r1 ; \
  53. bl 0f ;
  54. #define entry_end \
  55. 0: mflr r0 ; \
  56. mtlr r1 ; \
  57. blr ;
  58. .section .bootpg, "ax"
  59. .globl tlb1_entry
  60. tlb1_entry:
  61. entry_start
  62. /*
  63. * Number of TLB0 and TLB1 entries in the following table
  64. */
  65. .long (2f-1f)/16
  66. 1:
  67. #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
  68. /*
  69. * TLB0 4K Non-cacheable, guarded
  70. * 0xff700000 4K Initial CCSRBAR mapping
  71. *
  72. * This ends up at a TLB0 Index==0 entry, and must not collide
  73. * with other TLB0 Entries.
  74. */
  75. .long FSL_BOOKE_MAS0(0, 0, 0)
  76. .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
  77. .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
  78. .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
  79. #else
  80. #error("Update the number of table entries in tlb1_entry")
  81. #endif
  82. /*
  83. * TLB0 16K Cacheable, guarded
  84. * Temporary Global data for initialization
  85. *
  86. * Use four 4K TLB0 entries. These entries must be cacheable
  87. * as they provide the bootstrap memory before the memory
  88. * controler and real memory have been configured.
  89. *
  90. * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
  91. * and must not collide with other TLB0 entries.
  92. */
  93. .long FSL_BOOKE_MAS0(0, 0, 0)
  94. .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
  95. .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, MAS2_G)
  96. .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
  97. .long FSL_BOOKE_MAS0(0, 0, 0)
  98. .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
  99. .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, MAS2_G)
  100. .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0,
  101. (MAS3_SX|MAS3_SW|MAS3_SR))
  102. .long FSL_BOOKE_MAS0(0, 0, 0)
  103. .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
  104. .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, MAS2_G)
  105. .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0,
  106. (MAS3_SX|MAS3_SW|MAS3_SR))
  107. .long FSL_BOOKE_MAS0(0, 0, 0)
  108. .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
  109. .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, MAS2_G)
  110. .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0,
  111. (MAS3_SX|MAS3_SW|MAS3_SR))
  112. /* TLB 1 Initializations */
  113. /*
  114. * TLB 0, 1: 128M Non-cacheable, guarded
  115. * 0xf8000000 128M FLASH
  116. * Out of reset this entry is only 4K.
  117. */
  118. .long FSL_BOOKE_MAS0(1, 0, 0)
  119. .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
  120. .long FSL_BOOKE_MAS2(CFG_FLASH_BASE + 0x4000000, (MAS2_I|MAS2_G))
  121. .long FSL_BOOKE_MAS3(CFG_FLASH_BASE + 0x4000000, 0,
  122. (MAS3_SX|MAS3_SW|MAS3_SR))
  123. .long FSL_BOOKE_MAS0(1, 1, 0)
  124. .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
  125. .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
  126. .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
  127. /*
  128. * TLB 2: 1G Non-cacheable, guarded
  129. * 0x80000000 1G PCI1/PCIE 8,9,a,b
  130. */
  131. .long FSL_BOOKE_MAS0(1, 2, 0)
  132. .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
  133. .long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G))
  134. .long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
  135. /*
  136. * TLB 3, 4: 512M Non-cacheable, guarded
  137. * 0xc0000000 1G PCI2
  138. */
  139. .long FSL_BOOKE_MAS0(1, 3, 0)
  140. .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  141. .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G))
  142. .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
  143. .long FSL_BOOKE_MAS0(1, 4, 0)
  144. .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  145. .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
  146. .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0,
  147. (MAS3_SX|MAS3_SW|MAS3_SR))
  148. /*
  149. * TLB 5: 64M Non-cacheable, guarded
  150. * 0xe000_0000 1M CCSRBAR
  151. * 0xe200_0000 1M PCI1 IO
  152. * 0xe210_0000 1M PCI2 IO
  153. * 0xe300_0000 1M PCIe IO
  154. */
  155. .long FSL_BOOKE_MAS0(1, 5, 0)
  156. .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
  157. .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
  158. .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
  159. 2:
  160. entry_end
  161. /*
  162. * LAW(Local Access Window) configuration:
  163. *
  164. * 0x0000_0000 0x7fff_ffff DDR 2G
  165. * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
  166. * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
  167. * 0xc000_0000 0xdfff_ffff PCI2 MEM 512M
  168. * 0xe000_0000 0xe000_ffff CCSR 1M
  169. * 0xe200_0000 0xe10f_ffff PCI1 IO 1M
  170. * 0xe280_0000 0xe20f_ffff PCI2 IO 1M
  171. * 0xe300_0000 0xe30f_ffff PCIe IO 1M
  172. * 0xf800_0000 0xffff_ffff FLASH (boot bank) 128M
  173. *
  174. * Notes:
  175. * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
  176. * If flash is 8M at default position (last 8M), no LAW needed.
  177. *
  178. * LAW 0 is reserved for boot mapping
  179. */
  180. .section .bootpg, "ax"
  181. .globl law_entry
  182. law_entry:
  183. entry_start
  184. .long (4f-3f)/8
  185. 3:
  186. .long 0
  187. .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_1G)) & ~LAWAR_EN
  188. .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
  189. .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
  190. .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
  191. .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
  192. .long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
  193. .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
  194. .long (CFG_PCI2_IO_PHYS>>12) & 0xfffff
  195. .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
  196. .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
  197. .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M)
  198. .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
  199. .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M)
  200. /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
  201. .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
  202. .long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
  203. 4:
  204. entry_end