pxa_lcd.c 16 KB

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  1. /*
  2. * PXA LCD Controller
  3. *
  4. * (C) Copyright 2001-2002
  5. * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. /************************************************************************/
  10. /* ** HEADER FILES */
  11. /************************************************************************/
  12. #include <config.h>
  13. #include <common.h>
  14. #include <version.h>
  15. #include <stdarg.h>
  16. #include <linux/types.h>
  17. #include <stdio_dev.h>
  18. #include <lcd.h>
  19. #include <asm/arch/pxa-regs.h>
  20. #include <asm/io.h>
  21. /* #define DEBUG */
  22. #ifdef CONFIG_LCD
  23. /*----------------------------------------------------------------------*/
  24. /*
  25. * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
  26. * your display.
  27. */
  28. #ifdef CONFIG_PXA_VGA
  29. /* LCD outputs connected to a video DAC */
  30. # define LCD_BPP LCD_COLOR8
  31. /* you have to set lccr0 and lccr3 (including pcd) */
  32. # define REG_LCCR0 0x003008f8
  33. # define REG_LCCR3 0x0300FF01
  34. /* 640x480x16 @ 61 Hz */
  35. vidinfo_t panel_info = {
  36. .vl_col = 640,
  37. .vl_row = 480,
  38. .vl_width = 640,
  39. .vl_height = 480,
  40. .vl_clkp = CONFIG_SYS_HIGH,
  41. .vl_oep = CONFIG_SYS_HIGH,
  42. .vl_hsp = CONFIG_SYS_HIGH,
  43. .vl_vsp = CONFIG_SYS_HIGH,
  44. .vl_dp = CONFIG_SYS_HIGH,
  45. .vl_bpix = LCD_BPP,
  46. .vl_lbw = 0,
  47. .vl_splt = 0,
  48. .vl_clor = 0,
  49. .vl_tft = 1,
  50. .vl_hpw = 40,
  51. .vl_blw = 56,
  52. .vl_elw = 56,
  53. .vl_vpw = 20,
  54. .vl_bfw = 8,
  55. .vl_efw = 8,
  56. };
  57. #endif /* CONFIG_PXA_VIDEO */
  58. /*----------------------------------------------------------------------*/
  59. #ifdef CONFIG_SHARP_LM8V31
  60. # define LCD_BPP LCD_COLOR8
  61. # define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */
  62. /* you have to set lccr0 and lccr3 (including pcd) */
  63. # define REG_LCCR0 0x0030087C
  64. # define REG_LCCR3 0x0340FF08
  65. vidinfo_t panel_info = {
  66. .vl_col = 640,
  67. .vl_row = 480,
  68. .vl_width = 157,
  69. .vl_height = 118,
  70. .vl_clkp = CONFIG_SYS_HIGH,
  71. .vl_oep = CONFIG_SYS_HIGH,
  72. .vl_hsp = CONFIG_SYS_HIGH,
  73. .vl_vsp = CONFIG_SYS_HIGH,
  74. .vl_dp = CONFIG_SYS_HIGH,
  75. .vl_bpix = LCD_BPP,
  76. .vl_lbw = 0,
  77. .vl_splt = 1,
  78. .vl_clor = 1,
  79. .vl_tft = 0,
  80. .vl_hpw = 1,
  81. .vl_blw = 3,
  82. .vl_elw = 3,
  83. .vl_vpw = 1,
  84. .vl_bfw = 0,
  85. .vl_efw = 0,
  86. };
  87. #endif /* CONFIG_SHARP_LM8V31 */
  88. /*----------------------------------------------------------------------*/
  89. #ifdef CONFIG_VOIPAC_LCD
  90. # define LCD_BPP LCD_COLOR8
  91. # define LCD_INVERT_COLORS
  92. /* you have to set lccr0 and lccr3 (including pcd) */
  93. # define REG_LCCR0 0x043008f8
  94. # define REG_LCCR3 0x0340FF08
  95. vidinfo_t panel_info = {
  96. .vl_col = 640,
  97. .vl_row = 480,
  98. .vl_width = 157,
  99. .vl_height = 118,
  100. .vl_clkp = CONFIG_SYS_HIGH,
  101. .vl_oep = CONFIG_SYS_HIGH,
  102. .vl_hsp = CONFIG_SYS_HIGH,
  103. .vl_vsp = CONFIG_SYS_HIGH,
  104. .vl_dp = CONFIG_SYS_HIGH,
  105. .vl_bpix = LCD_BPP,
  106. .vl_lbw = 0,
  107. .vl_splt = 1,
  108. .vl_clor = 1,
  109. .vl_tft = 1,
  110. .vl_hpw = 32,
  111. .vl_blw = 144,
  112. .vl_elw = 32,
  113. .vl_vpw = 2,
  114. .vl_bfw = 13,
  115. .vl_efw = 30,
  116. };
  117. #endif /* CONFIG_VOIPAC_LCD */
  118. /*----------------------------------------------------------------------*/
  119. #ifdef CONFIG_HITACHI_SX14
  120. /* Hitachi SX14Q004-ZZA color STN LCD */
  121. #define LCD_BPP LCD_COLOR8
  122. /* you have to set lccr0 and lccr3 (including pcd) */
  123. #define REG_LCCR0 0x00301079
  124. #define REG_LCCR3 0x0340FF20
  125. vidinfo_t panel_info = {
  126. .vl_col = 320,
  127. .vl_row = 240,
  128. .vl_width = 167,
  129. .vl_height = 109,
  130. .vl_clkp = CONFIG_SYS_HIGH,
  131. .vl_oep = CONFIG_SYS_HIGH,
  132. .vl_hsp = CONFIG_SYS_HIGH,
  133. .vl_vsp = CONFIG_SYS_HIGH,
  134. .vl_dp = CONFIG_SYS_HIGH,
  135. .vl_bpix = LCD_BPP,
  136. .vl_lbw = 1,
  137. .vl_splt = 0,
  138. .vl_clor = 1,
  139. .vl_tft = 0,
  140. .vl_hpw = 1,
  141. .vl_blw = 1,
  142. .vl_elw = 1,
  143. .vl_vpw = 7,
  144. .vl_bfw = 0,
  145. .vl_efw = 0,
  146. };
  147. #endif /* CONFIG_HITACHI_SX14 */
  148. /*----------------------------------------------------------------------*/
  149. #ifdef CONFIG_LMS283GF05
  150. # define LCD_BPP LCD_COLOR8
  151. /*# define LCD_INVERT_COLORS*/
  152. /* you have to set lccr0 and lccr3 (including pcd) */
  153. # define REG_LCCR0 0x043008f8
  154. # define REG_LCCR3 0x03b00009
  155. vidinfo_t panel_info = {
  156. .vl_col = 240,
  157. .vl_row = 320,
  158. .vl_width = 240,
  159. .vl_height = 320,
  160. .vl_clkp = CONFIG_SYS_HIGH,
  161. .vl_oep = CONFIG_SYS_LOW,
  162. .vl_hsp = CONFIG_SYS_LOW,
  163. .vl_vsp = CONFIG_SYS_LOW,
  164. .vl_dp = CONFIG_SYS_HIGH,
  165. .vl_bpix = LCD_BPP,
  166. .vl_lbw = 0,
  167. .vl_splt = 1,
  168. .vl_clor = 1,
  169. .vl_tft = 1,
  170. .vl_hpw = 4,
  171. .vl_blw = 4,
  172. .vl_elw = 8,
  173. .vl_vpw = 4,
  174. .vl_bfw = 4,
  175. .vl_efw = 8,
  176. };
  177. #endif /* CONFIG_LMS283GF05 */
  178. /*----------------------------------------------------------------------*/
  179. #ifdef CONFIG_ACX517AKN
  180. # define LCD_BPP LCD_COLOR8
  181. /* you have to set lccr0 and lccr3 (including pcd) */
  182. # define REG_LCCR0 0x003008f9
  183. # define REG_LCCR3 0x03700006
  184. vidinfo_t panel_info = {
  185. .vl_col = 320,
  186. .vl_row = 320,
  187. .vl_width = 320,
  188. .vl_height = 320,
  189. .vl_clkp = CONFIG_SYS_HIGH,
  190. .vl_oep = CONFIG_SYS_LOW,
  191. .vl_hsp = CONFIG_SYS_LOW,
  192. .vl_vsp = CONFIG_SYS_LOW,
  193. .vl_dp = CONFIG_SYS_HIGH,
  194. .vl_bpix = LCD_BPP,
  195. .vl_lbw = 0,
  196. .vl_splt = 1,
  197. .vl_clor = 1,
  198. .vl_tft = 1,
  199. .vl_hpw = 0x04,
  200. .vl_blw = 0x1c,
  201. .vl_elw = 0x08,
  202. .vl_vpw = 0x01,
  203. .vl_bfw = 0x07,
  204. .vl_efw = 0x08,
  205. };
  206. #endif /* CONFIG_ACX517AKN */
  207. #ifdef CONFIG_ACX544AKN
  208. # define LCD_BPP LCD_COLOR16
  209. /* you have to set lccr0 and lccr3 (including pcd) */
  210. # define REG_LCCR0 0x003008f9
  211. # define REG_LCCR3 0x04700007 /* 16bpp */
  212. vidinfo_t panel_info = {
  213. .vl_col = 320,
  214. .vl_row = 320,
  215. .vl_width = 320,
  216. .vl_height = 320,
  217. .vl_clkp = CONFIG_SYS_LOW,
  218. .vl_oep = CONFIG_SYS_LOW,
  219. .vl_hsp = CONFIG_SYS_LOW,
  220. .vl_vsp = CONFIG_SYS_LOW,
  221. .vl_dp = CONFIG_SYS_LOW,
  222. .vl_bpix = LCD_BPP,
  223. .vl_lbw = 0,
  224. .vl_splt = 0,
  225. .vl_clor = 1,
  226. .vl_tft = 1,
  227. .vl_hpw = 0x05,
  228. .vl_blw = 0x13,
  229. .vl_elw = 0x08,
  230. .vl_vpw = 0x02,
  231. .vl_bfw = 0x07,
  232. .vl_efw = 0x05,
  233. };
  234. #endif /* CONFIG_ACX544AKN */
  235. /*----------------------------------------------------------------------*/
  236. #ifdef CONFIG_LQ038J7DH53
  237. # define LCD_BPP LCD_COLOR8
  238. /* you have to set lccr0 and lccr3 (including pcd) */
  239. # define REG_LCCR0 0x003008f9
  240. # define REG_LCCR3 0x03700004
  241. vidinfo_t panel_info = {
  242. .vl_col = 320,
  243. .vl_row = 480,
  244. .vl_width = 320,
  245. .vl_height = 480,
  246. .vl_clkp = CONFIG_SYS_HIGH,
  247. .vl_oep = CONFIG_SYS_LOW,
  248. .vl_hsp = CONFIG_SYS_LOW,
  249. .vl_vsp = CONFIG_SYS_LOW,
  250. .vl_dp = CONFIG_SYS_HIGH,
  251. .vl_bpix = LCD_BPP,
  252. .vl_lbw = 0,
  253. .vl_splt = 1,
  254. .vl_clor = 1,
  255. .vl_tft = 1,
  256. .vl_hpw = 0x04,
  257. .vl_blw = 0x20,
  258. .vl_elw = 0x01,
  259. .vl_vpw = 0x01,
  260. .vl_bfw = 0x04,
  261. .vl_efw = 0x01,
  262. };
  263. #endif /* CONFIG_ACX517AKN */
  264. /*----------------------------------------------------------------------*/
  265. #ifdef CONFIG_LITTLETON_LCD
  266. # define LCD_BPP LCD_COLOR8
  267. /* you have to set lccr0 and lccr3 (including pcd) */
  268. # define REG_LCCR0 0x003008f8
  269. # define REG_LCCR3 0x0300FF04
  270. vidinfo_t panel_info = {
  271. .vl_col = 480,
  272. .vl_row = 640,
  273. .vl_width = 480,
  274. .vl_height = 640,
  275. .vl_clkp = CONFIG_SYS_HIGH,
  276. .vl_oep = CONFIG_SYS_HIGH,
  277. .vl_hsp = CONFIG_SYS_HIGH,
  278. .vl_vsp = CONFIG_SYS_HIGH,
  279. .vl_dp = CONFIG_SYS_HIGH,
  280. .vl_bpix = LCD_BPP,
  281. .vl_lbw = 0,
  282. .vl_splt = 0,
  283. .vl_clor = 0,
  284. .vl_tft = 1,
  285. .vl_hpw = 9,
  286. .vl_blw = 8,
  287. .vl_elw = 24,
  288. .vl_vpw = 2,
  289. .vl_bfw = 2,
  290. .vl_efw = 4,
  291. };
  292. #endif /* CONFIG_LITTLETON_LCD */
  293. /*----------------------------------------------------------------------*/
  294. static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
  295. static void pxafb_setup_gpio (vidinfo_t *vid);
  296. static void pxafb_enable_controller (vidinfo_t *vid);
  297. static int pxafb_init (vidinfo_t *vid);
  298. /************************************************************************/
  299. /* --------------- PXA chipset specific functions ------------------- */
  300. /************************************************************************/
  301. void lcd_ctrl_init (void *lcdbase)
  302. {
  303. pxafb_init_mem(lcdbase, &panel_info);
  304. pxafb_init(&panel_info);
  305. pxafb_setup_gpio(&panel_info);
  306. pxafb_enable_controller(&panel_info);
  307. }
  308. /*----------------------------------------------------------------------*/
  309. #if LCD_BPP == LCD_COLOR8
  310. void
  311. lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
  312. {
  313. struct pxafb_info *fbi = &panel_info.pxa;
  314. unsigned short *palette = (unsigned short *)fbi->palette;
  315. u_int val;
  316. if (regno < fbi->palette_size) {
  317. val = ((red << 8) & 0xf800);
  318. val |= ((green << 4) & 0x07e0);
  319. val |= (blue & 0x001f);
  320. #ifdef LCD_INVERT_COLORS
  321. palette[regno] = ~val;
  322. #else
  323. palette[regno] = val;
  324. #endif
  325. }
  326. debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
  327. regno, &palette[regno],
  328. red, green, blue,
  329. palette[regno]);
  330. }
  331. #endif /* LCD_COLOR8 */
  332. /*----------------------------------------------------------------------*/
  333. #if LCD_BPP == LCD_MONOCHROME
  334. void lcd_initcolregs (void)
  335. {
  336. struct pxafb_info *fbi = &panel_info.pxa;
  337. cmap = (ushort *)fbi->palette;
  338. ushort regno;
  339. for (regno = 0; regno < 16; regno++) {
  340. cmap[regno * 2] = 0;
  341. cmap[(regno * 2) + 1] = regno & 0x0f;
  342. }
  343. }
  344. #endif /* LCD_MONOCHROME */
  345. /*----------------------------------------------------------------------*/
  346. __weak void lcd_enable(void)
  347. {
  348. }
  349. /************************************************************************/
  350. /* ** PXA255 specific routines */
  351. /************************************************************************/
  352. /*
  353. * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
  354. * descriptors and palette areas.
  355. */
  356. ulong calc_fbsize (void)
  357. {
  358. ulong size;
  359. int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
  360. size = line_length * panel_info.vl_row;
  361. size += PAGE_SIZE;
  362. return size;
  363. }
  364. static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
  365. {
  366. u_long palette_mem_size;
  367. struct pxafb_info *fbi = &vid->pxa;
  368. int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
  369. fbi->screen = (u_long)lcdbase;
  370. fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
  371. palette_mem_size = fbi->palette_size * sizeof(u16);
  372. debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
  373. /* locate palette and descs at end of page following fb */
  374. fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
  375. return 0;
  376. }
  377. #ifdef CONFIG_CPU_MONAHANS
  378. static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
  379. #else
  380. static void pxafb_setup_gpio (vidinfo_t *vid)
  381. {
  382. u_long lccr0;
  383. /*
  384. * setup is based on type of panel supported
  385. */
  386. lccr0 = vid->pxa.reg_lccr0;
  387. /* 4 bit interface */
  388. if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
  389. {
  390. debug("Setting GPIO for 4 bit data\n");
  391. /* bits 58-61 */
  392. writel(readl(GPDR1) | (0xf << 26), GPDR1);
  393. writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
  394. GAFR1_U);
  395. /* bits 74-77 */
  396. writel(readl(GPDR2) | (0xf << 10), GPDR2);
  397. writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
  398. GAFR2_L);
  399. }
  400. /* 8 bit interface */
  401. else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
  402. (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
  403. {
  404. debug("Setting GPIO for 8 bit data\n");
  405. /* bits 58-65 */
  406. writel(readl(GPDR1) | (0x3f << 26), GPDR1);
  407. writel(readl(GPDR2) | (0x3), GPDR2);
  408. writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
  409. GAFR1_U);
  410. writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
  411. /* bits 74-77 */
  412. writel(readl(GPDR2) | (0xf << 10), GPDR2);
  413. writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
  414. GAFR2_L);
  415. }
  416. /* 16 bit interface */
  417. else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
  418. {
  419. debug("Setting GPIO for 16 bit data\n");
  420. /* bits 58-77 */
  421. writel(readl(GPDR1) | (0x3f << 26), GPDR1);
  422. writel(readl(GPDR2) | 0x00003fff, GPDR2);
  423. writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
  424. GAFR1_U);
  425. writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
  426. }
  427. else
  428. {
  429. printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
  430. }
  431. }
  432. #endif
  433. static void pxafb_enable_controller (vidinfo_t *vid)
  434. {
  435. debug("Enabling LCD controller\n");
  436. /* Sequence from 11.7.10 */
  437. writel(vid->pxa.reg_lccr3, LCCR3);
  438. writel(vid->pxa.reg_lccr2, LCCR2);
  439. writel(vid->pxa.reg_lccr1, LCCR1);
  440. writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
  441. writel(vid->pxa.fdadr0, FDADR0);
  442. writel(vid->pxa.fdadr1, FDADR1);
  443. writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
  444. #ifdef CONFIG_CPU_MONAHANS
  445. writel(readl(CKENA) | CKENA_1_LCD, CKENA);
  446. #else
  447. writel(readl(CKEN) | CKEN16_LCD, CKEN);
  448. #endif
  449. debug("FDADR0 = 0x%08x\n", readl(FDADR0));
  450. debug("FDADR1 = 0x%08x\n", readl(FDADR1));
  451. debug("LCCR0 = 0x%08x\n", readl(LCCR0));
  452. debug("LCCR1 = 0x%08x\n", readl(LCCR1));
  453. debug("LCCR2 = 0x%08x\n", readl(LCCR2));
  454. debug("LCCR3 = 0x%08x\n", readl(LCCR3));
  455. }
  456. static int pxafb_init (vidinfo_t *vid)
  457. {
  458. struct pxafb_info *fbi = &vid->pxa;
  459. debug("Configuring PXA LCD\n");
  460. fbi->reg_lccr0 = REG_LCCR0;
  461. fbi->reg_lccr3 = REG_LCCR3;
  462. debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
  463. vid->vl_col, vid->vl_hpw,
  464. vid->vl_blw, vid->vl_elw);
  465. debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
  466. vid->vl_row, vid->vl_vpw,
  467. vid->vl_bfw, vid->vl_efw);
  468. fbi->reg_lccr1 =
  469. LCCR1_DisWdth(vid->vl_col) +
  470. LCCR1_HorSnchWdth(vid->vl_hpw) +
  471. LCCR1_BegLnDel(vid->vl_blw) +
  472. LCCR1_EndLnDel(vid->vl_elw);
  473. fbi->reg_lccr2 =
  474. LCCR2_DisHght(vid->vl_row) +
  475. LCCR2_VrtSnchWdth(vid->vl_vpw) +
  476. LCCR2_BegFrmDel(vid->vl_bfw) +
  477. LCCR2_EndFrmDel(vid->vl_efw);
  478. fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
  479. fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
  480. | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
  481. /* setup dma descriptors */
  482. fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
  483. fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
  484. fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
  485. #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
  486. (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
  487. (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
  488. /* populate descriptors */
  489. fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
  490. fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
  491. fbi->dmadesc_fblow->fidr = 0;
  492. fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
  493. fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
  494. fbi->dmadesc_fbhigh->fsadr = fbi->screen;
  495. fbi->dmadesc_fbhigh->fidr = 0;
  496. fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
  497. fbi->dmadesc_palette->fsadr = fbi->palette;
  498. fbi->dmadesc_palette->fidr = 0;
  499. fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
  500. if( NBITS(vid->vl_bpix) < 12)
  501. {
  502. /* assume any mode with <12 bpp is palette driven */
  503. fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
  504. fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
  505. /* flips back and forth between pal and fbhigh */
  506. fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
  507. }
  508. else
  509. {
  510. /* palette shouldn't be loaded in true-color mode */
  511. fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
  512. fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
  513. }
  514. debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
  515. debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
  516. debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
  517. debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
  518. debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
  519. debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
  520. debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
  521. debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
  522. debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
  523. debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
  524. debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
  525. debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
  526. return 0;
  527. }
  528. /************************************************************************/
  529. /************************************************************************/
  530. #endif /* CONFIG_LCD */