ipu.h 7.5 KB

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  1. /*
  2. * Porting to u-boot:
  3. *
  4. * (C) Copyright 2010
  5. * Stefano Babic, DENX Software Engineering, sbabic@denx.de
  6. *
  7. * Linux IPU driver for MX51:
  8. *
  9. * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
  10. *
  11. * SPDX-License-Identifier: GPL-2.0+
  12. */
  13. #ifndef __ASM_ARCH_IPU_H__
  14. #define __ASM_ARCH_IPU_H__
  15. #include <linux/types.h>
  16. #include <ipu_pixfmt.h>
  17. #define IDMA_CHAN_INVALID 0xFF
  18. #define HIGH_RESOLUTION_WIDTH 1024
  19. struct clk {
  20. const char *name;
  21. int id;
  22. /* Source clock this clk depends on */
  23. struct clk *parent;
  24. /* Secondary clock to enable/disable with this clock */
  25. struct clk *secondary;
  26. /* Current clock rate */
  27. unsigned long rate;
  28. /* Reference count of clock enable/disable */
  29. __s8 usecount;
  30. /* Register bit position for clock's enable/disable control. */
  31. u8 enable_shift;
  32. /* Register address for clock's enable/disable control. */
  33. void *enable_reg;
  34. u32 flags;
  35. /*
  36. * Function ptr to recalculate the clock's rate based on parent
  37. * clock's rate
  38. */
  39. void (*recalc) (struct clk *);
  40. /*
  41. * Function ptr to set the clock to a new rate. The rate must match a
  42. * supported rate returned from round_rate. Leave blank if clock is not
  43. * programmable
  44. */
  45. int (*set_rate) (struct clk *, unsigned long);
  46. /*
  47. * Function ptr to round the requested clock rate to the nearest
  48. * supported rate that is less than or equal to the requested rate.
  49. */
  50. unsigned long (*round_rate) (struct clk *, unsigned long);
  51. /*
  52. * Function ptr to enable the clock. Leave blank if clock can not
  53. * be gated.
  54. */
  55. int (*enable) (struct clk *);
  56. /*
  57. * Function ptr to disable the clock. Leave blank if clock can not
  58. * be gated.
  59. */
  60. void (*disable) (struct clk *);
  61. /* Function ptr to set the parent clock of the clock. */
  62. int (*set_parent) (struct clk *, struct clk *);
  63. };
  64. /*
  65. * Enumeration of Synchronous (Memory-less) panel types
  66. */
  67. typedef enum {
  68. IPU_PANEL_SHARP_TFT,
  69. IPU_PANEL_TFT,
  70. } ipu_panel_t;
  71. /*
  72. * IPU Driver channels definitions.
  73. * Note these are different from IDMA channels
  74. */
  75. #define IPU_MAX_CH 32
  76. #define _MAKE_CHAN(num, v_in, g_in, a_in, out) \
  77. ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out)
  78. #define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24))
  79. #define IPU_CHAN_ID(ch) (ch >> 24)
  80. #define IPU_CHAN_ALT(ch) (ch & 0x02000000)
  81. #define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F)
  82. #define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F)
  83. #define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F)
  84. #define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F))
  85. #define NO_DMA 0x3F
  86. #define ALT 1
  87. /*
  88. * Enumeration of IPU logical channels. An IPU logical channel is defined as a
  89. * combination of an input (memory to IPU), output (IPU to memory), and/or
  90. * secondary input IDMA channels and in some cases an Image Converter task.
  91. * Some channels consist of only an input or output.
  92. */
  93. typedef enum {
  94. CHAN_NONE = -1,
  95. MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA),
  96. MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA),
  97. MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA),
  98. MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA),
  99. MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA),
  100. MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA),
  101. MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0),
  102. MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0),
  103. DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
  104. DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
  105. } ipu_channel_t;
  106. /*
  107. * Enumeration of types of buffers for a logical channel.
  108. */
  109. typedef enum {
  110. IPU_OUTPUT_BUFFER = 0, /*< Buffer for output from IPU */
  111. IPU_ALPHA_IN_BUFFER = 1, /*< Buffer for input to IPU */
  112. IPU_GRAPH_IN_BUFFER = 2, /*< Buffer for input to IPU */
  113. IPU_VIDEO_IN_BUFFER = 3, /*< Buffer for input to IPU */
  114. IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,
  115. IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,
  116. } ipu_buffer_t;
  117. #define IPU_PANEL_SERIAL 1
  118. #define IPU_PANEL_PARALLEL 2
  119. struct ipu_channel {
  120. u8 video_in_dma;
  121. u8 alpha_in_dma;
  122. u8 graph_in_dma;
  123. u8 out_dma;
  124. };
  125. enum ipu_dmfc_type {
  126. DMFC_NORMAL = 0,
  127. DMFC_HIGH_RESOLUTION_DC,
  128. DMFC_HIGH_RESOLUTION_DP,
  129. DMFC_HIGH_RESOLUTION_ONLY_DP,
  130. };
  131. /*
  132. * Union of initialization parameters for a logical channel.
  133. */
  134. typedef union {
  135. struct {
  136. uint32_t di;
  137. unsigned char interlaced;
  138. } mem_dc_sync;
  139. struct {
  140. uint32_t temp;
  141. } mem_sdc_fg;
  142. struct {
  143. uint32_t di;
  144. unsigned char interlaced;
  145. uint32_t in_pixel_fmt;
  146. uint32_t out_pixel_fmt;
  147. unsigned char alpha_chan_en;
  148. } mem_dp_bg_sync;
  149. struct {
  150. uint32_t temp;
  151. } mem_sdc_bg;
  152. struct {
  153. uint32_t di;
  154. unsigned char interlaced;
  155. uint32_t in_pixel_fmt;
  156. uint32_t out_pixel_fmt;
  157. unsigned char alpha_chan_en;
  158. } mem_dp_fg_sync;
  159. } ipu_channel_params_t;
  160. /*
  161. * Enumeration of IPU interrupts.
  162. */
  163. enum ipu_irq_line {
  164. IPU_IRQ_DP_SF_END = 448 + 3,
  165. IPU_IRQ_DC_FC_1 = 448 + 9,
  166. };
  167. /*
  168. * Bitfield of Display Interface signal polarities.
  169. */
  170. typedef struct {
  171. unsigned datamask_en:1;
  172. unsigned ext_clk:1;
  173. unsigned interlaced:1;
  174. unsigned odd_field_first:1;
  175. unsigned clksel_en:1;
  176. unsigned clkidle_en:1;
  177. unsigned data_pol:1; /* true = inverted */
  178. unsigned clk_pol:1; /* true = rising edge */
  179. unsigned enable_pol:1;
  180. unsigned Hsync_pol:1; /* true = active high */
  181. unsigned Vsync_pol:1;
  182. } ipu_di_signal_cfg_t;
  183. typedef enum {
  184. RGB,
  185. YCbCr,
  186. YUV
  187. } ipu_color_space_t;
  188. /* Common IPU API */
  189. int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params);
  190. void ipu_uninit_channel(ipu_channel_t channel);
  191. int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
  192. uint32_t pixel_fmt,
  193. uint16_t width, uint16_t height,
  194. uint32_t stride,
  195. dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
  196. uint32_t u_offset, uint32_t v_offset);
  197. int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
  198. uint32_t bufNum, dma_addr_t phyaddr);
  199. int32_t ipu_is_channel_busy(ipu_channel_t channel);
  200. void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
  201. uint32_t bufNum);
  202. int32_t ipu_enable_channel(ipu_channel_t channel);
  203. int32_t ipu_disable_channel(ipu_channel_t channel);
  204. int32_t ipu_init_sync_panel(int disp,
  205. uint32_t pixel_clk,
  206. uint16_t width, uint16_t height,
  207. uint32_t pixel_fmt,
  208. uint16_t h_start_width, uint16_t h_sync_width,
  209. uint16_t h_end_width, uint16_t v_start_width,
  210. uint16_t v_sync_width, uint16_t v_end_width,
  211. uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);
  212. int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
  213. uint8_t alpha);
  214. int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
  215. uint32_t colorKey);
  216. uint32_t bytes_per_pixel(uint32_t fmt);
  217. void clk_enable(struct clk *clk);
  218. void clk_disable(struct clk *clk);
  219. u32 clk_get_rate(struct clk *clk);
  220. int clk_set_rate(struct clk *clk, unsigned long rate);
  221. long clk_round_rate(struct clk *clk, unsigned long rate);
  222. int clk_set_parent(struct clk *clk, struct clk *parent);
  223. int clk_get_usecount(struct clk *clk);
  224. struct clk *clk_get_parent(struct clk *clk);
  225. void ipu_dump_registers(void);
  226. int ipu_probe(void);
  227. void ipu_dmfc_init(int dmfc_type, int first);
  228. void ipu_init_dc_mappings(void);
  229. void ipu_dmfc_set_wait4eot(int dma_chan, int width);
  230. void ipu_dc_init(int dc_chan, int di, unsigned char interlaced);
  231. void ipu_dc_uninit(int dc_chan);
  232. void ipu_dp_dc_enable(ipu_channel_t channel);
  233. int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
  234. uint32_t out_pixel_fmt);
  235. void ipu_dp_uninit(ipu_channel_t channel);
  236. void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap);
  237. ipu_color_space_t format_to_colorspace(uint32_t fmt);
  238. #endif