README.x86 4.2 KB

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  1. #
  2. # Copyright (C) 2014, Simon Glass <sjg@chromium.org>
  3. # Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
  4. #
  5. # SPDX-License-Identifier: GPL-2.0+
  6. #
  7. U-Boot on x86
  8. =============
  9. This document describes the information about U-Boot running on x86 targets,
  10. including supported boards, build instructions, todo list, etc.
  11. Status
  12. ------
  13. U-Boot supports running as a coreboot [1] payload on x86. So far only Link
  14. (Chromebook Pixel) has been tested, but it should work with minimal adjustments
  15. on other x86 boards since coreboot deals with most of the low-level details.
  16. U-Boot also supports booting directly from x86 reset vector without coreboot,
  17. aka raw support or bare support. Currently Link and Intel Crown Bay board
  18. support running U-Boot 'bare metal'.
  19. As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux
  20. kernel as part of a FIT image. It also supports a compressed zImage.
  21. Build Instructions
  22. ------------------
  23. Building U-Boot as a coreboot payload is just like building U-Boot for targets
  24. on other architectures, like below:
  25. $ make coreboot-x86_defconfig
  26. $ make all
  27. Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
  28. little bit tricky, as generally it requires several binary blobs which are not
  29. shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
  30. not turned on by default in the U-Boot source tree. Firstly, you need turn it
  31. on by uncommenting the following line in the main U-Boot Makefile:
  32. # ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
  33. Link-specific instructions:
  34. First, you need the following binary blobs:
  35. * descriptor.bin - Intel flash descriptor
  36. * me.bin - Intel Management Engine
  37. * mrc.bin - Memory Reference Code, which sets up SDRAM
  38. * video ROM - sets up the display
  39. You can get these binary blobs by:
  40. $ git clone http://review.coreboot.org/p/blobs.git
  41. $ cd blobs
  42. Find the following files:
  43. * ./mainboard/google/link/descriptor.bin
  44. * ./mainboard/google/link/me.bin
  45. * ./northbridge/intel/sandybridge/systemagent-ivybridge.bin
  46. The 3rd one should be renamed to mrc.bin.
  47. As for the video ROM, you can get it here [2].
  48. Make sure all these binary blobs are put in the board directory.
  49. Now you can build U-Boot and obtain u-boot.rom:
  50. $ make chromebook_link_defconfig
  51. $ make all
  52. Intel Crown Bay specific instructions:
  53. U-Boot support of Intel Crown Bay board [3] relies on a binary blob called
  54. Firmware Support Package [4] to perform all the necessary initialization steps
  55. as documented in the BIOS Writer Guide, including initialization of the CPU,
  56. memory controller, chipset and certain bus interfaces.
  57. Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T,
  58. install it on your host and locate the FSP binary blob. Note this platform
  59. also requires a Chipset Micro Code (CMC) state machine binary to be present in
  60. the SPI flash where u-boot.rom resides, and this CMC binary blob can be found
  61. in this FSP package too.
  62. * ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd
  63. * ./Microcode/C0_22211.BIN
  64. Rename the first one to fsp.bin and second one to cmc.bin and put them in the
  65. board directory.
  66. Now you can build U-Boot and obtaim u-boot.rom
  67. $ make crownbay_defconfig
  68. $ make all
  69. CPU Microcode
  70. -------------
  71. Modern CPU usually requires a special bit stream called microcode [5] to be
  72. loaded on the processor after power up in order to function properly. U-Boot
  73. has already integrated these as hex dumps in the source tree.
  74. Driver Model
  75. ------------
  76. x86 has been converted to use driver model for serial and GPIO.
  77. Device Tree
  78. -----------
  79. x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to
  80. be turned on. Not every device on the board is configured via devie tree, but
  81. more and more devices will be added as time goes by. Check out the directory
  82. arch/x86/dts/ for these device tree source files.
  83. TODO List
  84. ---------
  85. - MTRR support (for performance)
  86. - Audio
  87. - Chrome OS verified boot
  88. - SMI and ACPI support, to provide platform info and facilities to Linux
  89. References
  90. ----------
  91. [1] http://www.coreboot.org
  92. [2] http://www.coreboot.org/~stepan/pci8086,0166.rom
  93. [3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
  94. [4] http://www.intel.com/fsp
  95. [5] http://en.wikipedia.org/wiki/Microcode