README.socfpga 1.8 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253
  1. --------------------------------------------
  2. SOCFPGA Documentation for U-Boot and SPL
  3. --------------------------------------------
  4. This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore
  5. based SOCFPGA. To know more about the hardware itself, please refer to
  6. www.altera.com.
  7. --------------------------------------------
  8. socfpga_dw_mmc
  9. --------------------------------------------
  10. Here are macro and detailed configuration required to enable DesignWare SDMMC
  11. controller support within SOCFPGA
  12. #define CONFIG_MMC
  13. -> To enable the SD MMC framework support
  14. #define CONFIG_SDMMC_BASE (SOCFPGA_SDMMC_ADDRESS)
  15. -> The base address of CSR register for DesignWare SDMMC controller
  16. #define CONFIG_GENERIC_MMC
  17. -> Enable the generic MMC driver
  18. #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
  19. -> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
  20. #define CONFIG_DWMMC
  21. -> Enable the common DesignWare SDMMC controller framework
  22. #define CONFIG_SOCFPGA_DWMMC
  23. -> Enable the SOCFPGA specific driver for DesignWare SDMMC controller
  24. #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
  25. -> The FIFO depth for SOCFPGA DesignWare SDMMC controller
  26. #define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
  27. -> Phase-shifted clock of sdmmc_clk for controller to drive command and data to
  28. the card to meet hold time requirements. SD clock is running at 50MHz and
  29. drvsel is set to shift 135 degrees (3 * 45 degrees). With that, the hold time
  30. is 135 / 360 * 20ns = 7.5ns.
  31. #define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
  32. -> Phase-shifted clock of sdmmc_clk used to sample the command and data from
  33. the card
  34. #define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH 4
  35. -> Bus width of data line which either 1, 4 or 8 and based on board routing.
  36. #define CONFIG_SOCFPGA_DWMMC_BUS_HZ 50000000
  37. -> The clock rate to controller. Do note the controller have a wrapper which
  38. divide the clock from PLL by 4.