cmd_pci.c 15 KB

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  1. /*
  2. * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  3. * Andreas Heppel <aheppel@sysgo.de>
  4. *
  5. * (C) Copyright 2002
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. */
  11. /*
  12. * PCI routines
  13. */
  14. #include <common.h>
  15. #include <bootretry.h>
  16. #include <cli.h>
  17. #include <command.h>
  18. #include <asm/processor.h>
  19. #include <asm/io.h>
  20. #include <pci.h>
  21. /*
  22. * Follows routines for the output of infos about devices on PCI bus.
  23. */
  24. void pci_header_show(pci_dev_t dev);
  25. void pci_header_show_brief(pci_dev_t dev);
  26. /*
  27. * Subroutine: pciinfo
  28. *
  29. * Description: Show information about devices on PCI bus.
  30. * Depending on the define CONFIG_SYS_SHORT_PCI_LISTING
  31. * the output will be more or less exhaustive.
  32. *
  33. * Inputs: bus_no the number of the bus to be scanned.
  34. *
  35. * Return: None
  36. *
  37. */
  38. void pciinfo(int BusNum, int ShortPCIListing)
  39. {
  40. struct pci_controller *hose = pci_bus_to_hose(BusNum);
  41. int Device;
  42. int Function;
  43. unsigned char HeaderType;
  44. unsigned short VendorID;
  45. pci_dev_t dev;
  46. if (!hose)
  47. return;
  48. printf("Scanning PCI devices on bus %d\n", BusNum);
  49. if (ShortPCIListing) {
  50. printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
  51. printf("_____________________________________________________________\n");
  52. }
  53. for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
  54. HeaderType = 0;
  55. VendorID = 0;
  56. for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
  57. /*
  58. * If this is not a multi-function device, we skip the rest.
  59. */
  60. if (Function && !(HeaderType & 0x80))
  61. break;
  62. dev = PCI_BDF(BusNum, Device, Function);
  63. if (pci_skip_dev(hose, dev))
  64. continue;
  65. pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
  66. if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
  67. continue;
  68. if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);
  69. if (ShortPCIListing)
  70. {
  71. printf("%02x.%02x.%02x ", BusNum, Device, Function);
  72. pci_header_show_brief(dev);
  73. }
  74. else
  75. {
  76. printf("\nFound PCI device %02x.%02x.%02x:\n",
  77. BusNum, Device, Function);
  78. pci_header_show(dev);
  79. }
  80. }
  81. }
  82. }
  83. /*
  84. * Subroutine: pci_header_show_brief
  85. *
  86. * Description: Reads and prints the header of the
  87. * specified PCI device in short form.
  88. *
  89. * Inputs: dev Bus+Device+Function number
  90. *
  91. * Return: None
  92. *
  93. */
  94. void pci_header_show_brief(pci_dev_t dev)
  95. {
  96. u16 vendor, device;
  97. u8 class, subclass;
  98. pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
  99. pci_read_config_word(dev, PCI_DEVICE_ID, &device);
  100. pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
  101. pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
  102. printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
  103. vendor, device,
  104. pci_class_str(class), subclass);
  105. }
  106. /*
  107. * Subroutine: PCI_Header_Show
  108. *
  109. * Description: Reads the header of the specified PCI device.
  110. *
  111. * Inputs: BusDevFunc Bus+Device+Function number
  112. *
  113. * Return: None
  114. *
  115. */
  116. void pci_header_show(pci_dev_t dev)
  117. {
  118. u8 _byte, header_type;
  119. u16 _word;
  120. u32 _dword;
  121. #define PRINT(msg, type, reg) \
  122. pci_read_config_##type(dev, reg, &_##type); \
  123. printf(msg, _##type)
  124. #define PRINT2(msg, type, reg, func) \
  125. pci_read_config_##type(dev, reg, &_##type); \
  126. printf(msg, _##type, func(_##type))
  127. pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
  128. PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID);
  129. PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID);
  130. PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND);
  131. PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
  132. PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
  133. PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
  134. pci_class_str);
  135. PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
  136. PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
  137. PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
  138. PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER);
  139. PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
  140. PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
  141. PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
  142. switch (header_type & 0x03) {
  143. case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
  144. PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
  145. PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
  146. PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
  147. PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
  148. PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
  149. PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
  150. PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
  151. PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
  152. PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
  153. PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
  154. PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
  155. PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
  156. PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
  157. break;
  158. case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
  159. PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
  160. PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
  161. PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
  162. PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
  163. PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
  164. PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE);
  165. PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT);
  166. PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS);
  167. PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE);
  168. PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT);
  169. PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
  170. PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
  171. PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
  172. PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
  173. PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16);
  174. PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
  175. PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1);
  176. PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
  177. PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
  178. PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
  179. break;
  180. case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
  181. PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
  182. PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
  183. PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
  184. PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
  185. PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
  186. PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
  187. PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
  188. PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
  189. PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
  190. PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
  191. PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
  192. PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
  193. PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
  194. PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
  195. PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
  196. PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
  197. PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
  198. PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
  199. PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
  200. PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
  201. PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
  202. PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
  203. PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
  204. PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
  205. break;
  206. default:
  207. printf("unknown header\n");
  208. break;
  209. }
  210. #undef PRINT
  211. #undef PRINT2
  212. }
  213. /* Convert the "bus.device.function" identifier into a number.
  214. */
  215. static pci_dev_t get_pci_dev(char* name)
  216. {
  217. char cnum[12];
  218. int len, i, iold, n;
  219. int bdfs[3] = {0,0,0};
  220. len = strlen(name);
  221. if (len > 8)
  222. return -1;
  223. for (i = 0, iold = 0, n = 0; i < len; i++) {
  224. if (name[i] == '.') {
  225. memcpy(cnum, &name[iold], i - iold);
  226. cnum[i - iold] = '\0';
  227. bdfs[n++] = simple_strtoul(cnum, NULL, 16);
  228. iold = i + 1;
  229. }
  230. }
  231. strcpy(cnum, &name[iold]);
  232. if (n == 0)
  233. n = 1;
  234. bdfs[n] = simple_strtoul(cnum, NULL, 16);
  235. return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
  236. }
  237. static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
  238. {
  239. #define DISP_LINE_LEN 16
  240. ulong i, nbytes, linebytes;
  241. int rc = 0;
  242. if (length == 0)
  243. length = 0x40 / size; /* Standard PCI configuration space */
  244. /* Print the lines.
  245. * once, and all accesses are with the specified bus width.
  246. */
  247. nbytes = length * size;
  248. do {
  249. uint val4;
  250. ushort val2;
  251. u_char val1;
  252. printf("%08lx:", addr);
  253. linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
  254. for (i=0; i<linebytes; i+= size) {
  255. if (size == 4) {
  256. pci_read_config_dword(bdf, addr, &val4);
  257. printf(" %08x", val4);
  258. } else if (size == 2) {
  259. pci_read_config_word(bdf, addr, &val2);
  260. printf(" %04x", val2);
  261. } else {
  262. pci_read_config_byte(bdf, addr, &val1);
  263. printf(" %02x", val1);
  264. }
  265. addr += size;
  266. }
  267. printf("\n");
  268. nbytes -= linebytes;
  269. if (ctrlc()) {
  270. rc = 1;
  271. break;
  272. }
  273. } while (nbytes > 0);
  274. return (rc);
  275. }
  276. static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
  277. {
  278. if (size == 4) {
  279. pci_write_config_dword(bdf, addr, value);
  280. }
  281. else if (size == 2) {
  282. ushort val = value & 0xffff;
  283. pci_write_config_word(bdf, addr, val);
  284. }
  285. else {
  286. u_char val = value & 0xff;
  287. pci_write_config_byte(bdf, addr, val);
  288. }
  289. return 0;
  290. }
  291. static int
  292. pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
  293. {
  294. ulong i;
  295. int nbytes;
  296. uint val4;
  297. ushort val2;
  298. u_char val1;
  299. /* Print the address, followed by value. Then accept input for
  300. * the next value. A non-converted value exits.
  301. */
  302. do {
  303. printf("%08lx:", addr);
  304. if (size == 4) {
  305. pci_read_config_dword(bdf, addr, &val4);
  306. printf(" %08x", val4);
  307. }
  308. else if (size == 2) {
  309. pci_read_config_word(bdf, addr, &val2);
  310. printf(" %04x", val2);
  311. }
  312. else {
  313. pci_read_config_byte(bdf, addr, &val1);
  314. printf(" %02x", val1);
  315. }
  316. nbytes = cli_readline(" ? ");
  317. if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
  318. /* <CR> pressed as only input, don't modify current
  319. * location and move to next. "-" pressed will go back.
  320. */
  321. if (incrflag)
  322. addr += nbytes ? -size : size;
  323. nbytes = 1;
  324. /* good enough to not time out */
  325. bootretry_reset_cmd_timeout();
  326. }
  327. #ifdef CONFIG_BOOT_RETRY_TIME
  328. else if (nbytes == -2) {
  329. break; /* timed out, exit the command */
  330. }
  331. #endif
  332. else {
  333. char *endp;
  334. i = simple_strtoul(console_buffer, &endp, 16);
  335. nbytes = endp - console_buffer;
  336. if (nbytes) {
  337. /* good enough to not time out
  338. */
  339. bootretry_reset_cmd_timeout();
  340. pci_cfg_write (bdf, addr, size, i);
  341. if (incrflag)
  342. addr += size;
  343. }
  344. }
  345. } while (nbytes);
  346. return 0;
  347. }
  348. /* PCI Configuration Space access commands
  349. *
  350. * Syntax:
  351. * pci display[.b, .w, .l] bus.device.function} [addr] [len]
  352. * pci next[.b, .w, .l] bus.device.function [addr]
  353. * pci modify[.b, .w, .l] bus.device.function [addr]
  354. * pci write[.b, .w, .l] bus.device.function addr value
  355. */
  356. static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  357. {
  358. ulong addr = 0, value = 0, size = 0;
  359. pci_dev_t bdf = 0;
  360. char cmd = 's';
  361. if (argc > 1)
  362. cmd = argv[1][0];
  363. switch (cmd) {
  364. case 'd': /* display */
  365. case 'n': /* next */
  366. case 'm': /* modify */
  367. case 'w': /* write */
  368. /* Check for a size specification. */
  369. size = cmd_get_data_size(argv[1], 4);
  370. if (argc > 3)
  371. addr = simple_strtoul(argv[3], NULL, 16);
  372. if (argc > 4)
  373. value = simple_strtoul(argv[4], NULL, 16);
  374. case 'h': /* header */
  375. if (argc < 3)
  376. goto usage;
  377. if ((bdf = get_pci_dev(argv[2])) == -1)
  378. return 1;
  379. break;
  380. #ifdef CONFIG_CMD_PCI_ENUM
  381. case 'e':
  382. break;
  383. #endif
  384. default: /* scan bus */
  385. value = 1; /* short listing */
  386. bdf = 0; /* bus number */
  387. if (argc > 1) {
  388. if (argv[argc-1][0] == 'l') {
  389. value = 0;
  390. argc--;
  391. }
  392. if (argc > 1)
  393. bdf = simple_strtoul(argv[1], NULL, 16);
  394. }
  395. pciinfo(bdf, value);
  396. return 0;
  397. }
  398. switch (argv[1][0]) {
  399. case 'h': /* header */
  400. pci_header_show(bdf);
  401. return 0;
  402. case 'd': /* display */
  403. return pci_cfg_display(bdf, addr, size, value);
  404. #ifdef CONFIG_CMD_PCI_ENUM
  405. case 'e':
  406. pci_init();
  407. return 0;
  408. #endif
  409. case 'n': /* next */
  410. if (argc < 4)
  411. goto usage;
  412. return pci_cfg_modify(bdf, addr, size, value, 0);
  413. case 'm': /* modify */
  414. if (argc < 4)
  415. goto usage;
  416. return pci_cfg_modify(bdf, addr, size, value, 1);
  417. case 'w': /* write */
  418. if (argc < 5)
  419. goto usage;
  420. return pci_cfg_write(bdf, addr, size, value);
  421. }
  422. return 1;
  423. usage:
  424. return CMD_RET_USAGE;
  425. }
  426. /***************************************************/
  427. #ifdef CONFIG_SYS_LONGHELP
  428. static char pci_help_text[] =
  429. "[bus] [long]\n"
  430. " - short or long list of PCI devices on bus 'bus'\n"
  431. #ifdef CONFIG_CMD_PCI_ENUM
  432. "pci enum\n"
  433. " - re-enumerate PCI buses\n"
  434. #endif
  435. "pci header b.d.f\n"
  436. " - show header of PCI device 'bus.device.function'\n"
  437. "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
  438. " - display PCI configuration space (CFG)\n"
  439. "pci next[.b, .w, .l] b.d.f address\n"
  440. " - modify, read and keep CFG address\n"
  441. "pci modify[.b, .w, .l] b.d.f address\n"
  442. " - modify, auto increment CFG address\n"
  443. "pci write[.b, .w, .l] b.d.f address value\n"
  444. " - write to CFG address";
  445. #endif
  446. U_BOOT_CMD(
  447. pci, 5, 1, do_pci,
  448. "list and access PCI Configuration Space", pci_help_text
  449. );