actions,s900-cmu.h 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Device Tree binding constants for Actions Semi S900 Clock Management Unit
  4. //
  5. // Copyright (c) 2014 Actions Semi Inc.
  6. // Copyright (c) 2018 Linaro Ltd.
  7. #ifndef __DT_BINDINGS_CLOCK_S900_CMU_H
  8. #define __DT_BINDINGS_CLOCK_S900_CMU_H
  9. #define CLK_NONE 0
  10. /* fixed rate clocks */
  11. #define CLK_LOSC 1
  12. #define CLK_HOSC 2
  13. /* pll clocks */
  14. #define CLK_CORE_PLL 3
  15. #define CLK_DEV_PLL 4
  16. #define CLK_DDR_PLL 5
  17. #define CLK_NAND_PLL 6
  18. #define CLK_DISPLAY_PLL 7
  19. #define CLK_DSI_PLL 8
  20. #define CLK_ASSIST_PLL 9
  21. #define CLK_AUDIO_PLL 10
  22. /* system clock */
  23. #define CLK_CPU 15
  24. #define CLK_DEV 16
  25. #define CLK_NOC 17
  26. #define CLK_NOC_MUX 18
  27. #define CLK_NOC_DIV 19
  28. #define CLK_AHB 20
  29. #define CLK_APB 21
  30. #define CLK_DMAC 22
  31. /* peripheral device clock */
  32. #define CLK_GPIO 23
  33. #define CLK_BISP 24
  34. #define CLK_CSI0 25
  35. #define CLK_CSI1 26
  36. #define CLK_DE0 27
  37. #define CLK_DE1 28
  38. #define CLK_DE2 29
  39. #define CLK_DE3 30
  40. #define CLK_DSI 32
  41. #define CLK_GPU 33
  42. #define CLK_GPU_CORE 34
  43. #define CLK_GPU_MEM 35
  44. #define CLK_GPU_SYS 36
  45. #define CLK_HDE 37
  46. #define CLK_I2C0 38
  47. #define CLK_I2C1 39
  48. #define CLK_I2C2 40
  49. #define CLK_I2C3 41
  50. #define CLK_I2C4 42
  51. #define CLK_I2C5 43
  52. #define CLK_I2SRX 44
  53. #define CLK_I2STX 45
  54. #define CLK_IMX 46
  55. #define CLK_LCD 47
  56. #define CLK_NAND0 48
  57. #define CLK_NAND1 49
  58. #define CLK_PWM0 50
  59. #define CLK_PWM1 51
  60. #define CLK_PWM2 52
  61. #define CLK_PWM3 53
  62. #define CLK_PWM4 54
  63. #define CLK_PWM5 55
  64. #define CLK_SD0 56
  65. #define CLK_SD1 57
  66. #define CLK_SD2 58
  67. #define CLK_SD3 59
  68. #define CLK_SENSOR 60
  69. #define CLK_SPEED_SENSOR 61
  70. #define CLK_SPI0 62
  71. #define CLK_SPI1 63
  72. #define CLK_SPI2 64
  73. #define CLK_SPI3 65
  74. #define CLK_THERMAL_SENSOR 66
  75. #define CLK_UART0 67
  76. #define CLK_UART1 68
  77. #define CLK_UART2 69
  78. #define CLK_UART3 70
  79. #define CLK_UART4 71
  80. #define CLK_UART5 72
  81. #define CLK_UART6 73
  82. #define CLK_VCE 74
  83. #define CLK_VDE 75
  84. #define CLK_USB3_480MPLL0 76
  85. #define CLK_USB3_480MPHY0 77
  86. #define CLK_USB3_5GPHY 78
  87. #define CLK_USB3_CCE 79
  88. #define CLK_USB3_MAC 80
  89. #define CLK_TIMER 83
  90. #define CLK_HDMI_AUDIO 84
  91. #define CLK_24M 85
  92. #define CLK_EDP 86
  93. #define CLK_24M_EDP 87
  94. #define CLK_EDP_PLL 88
  95. #define CLK_EDP_LINK 89
  96. #define CLK_USB2H0_PLLEN 90
  97. #define CLK_USB2H0_PHY 91
  98. #define CLK_USB2H0_CCE 92
  99. #define CLK_USB2H1_PLLEN 93
  100. #define CLK_USB2H1_PHY 94
  101. #define CLK_USB2H1_CCE 95
  102. #define CLK_DDR0 96
  103. #define CLK_DDR1 97
  104. #define CLK_DMM 98
  105. #define CLK_ETH_MAC 99
  106. #define CLK_RMII_REF 100
  107. #define CLK_NR_CLKS (CLK_RMII_REF + 1)
  108. #endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */