mpc8xxx_spi.c 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
  4. * With help from the common/soft_spi and arch/powerpc/cpu/mpc8260 drivers
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <malloc.h>
  11. #include <spi.h>
  12. #include <asm/mpc8xxx_spi.h>
  13. #include <asm-generic/gpio.h>
  14. #include <dm/device_compat.h>
  15. enum {
  16. SPI_EV_NE = BIT(31 - 22), /* Receiver Not Empty */
  17. SPI_EV_NF = BIT(31 - 23), /* Transmitter Not Full */
  18. };
  19. enum {
  20. SPI_MODE_LOOP = BIT(31 - 1), /* Loopback mode */
  21. SPI_MODE_CI = BIT(31 - 2), /* Clock invert */
  22. SPI_MODE_CP = BIT(31 - 3), /* Clock phase */
  23. SPI_MODE_DIV16 = BIT(31 - 4), /* Divide clock source by 16 */
  24. SPI_MODE_REV = BIT(31 - 5), /* Reverse mode - MSB first */
  25. SPI_MODE_MS = BIT(31 - 6), /* Always master */
  26. SPI_MODE_EN = BIT(31 - 7), /* Enable interface */
  27. SPI_MODE_LEN_MASK = 0xf00000,
  28. SPI_MODE_LEN_SHIFT = 20,
  29. SPI_MODE_PM_SHIFT = 16,
  30. SPI_MODE_PM_MASK = 0xf0000,
  31. SPI_COM_LST = BIT(31 - 9),
  32. };
  33. struct mpc8xxx_priv {
  34. spi8xxx_t *spi;
  35. struct gpio_desc gpios[16];
  36. int cs_count;
  37. ulong clk_rate;
  38. };
  39. #define SPI_TIMEOUT 1000
  40. static int mpc8xxx_spi_ofdata_to_platdata(struct udevice *dev)
  41. {
  42. struct mpc8xxx_priv *priv = dev_get_priv(dev);
  43. struct clk clk;
  44. int ret;
  45. priv->spi = (spi8xxx_t *)dev_read_addr(dev);
  46. ret = gpio_request_list_by_name(dev, "gpios", priv->gpios,
  47. ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
  48. if (ret < 0)
  49. return -EINVAL;
  50. priv->cs_count = ret;
  51. ret = clk_get_by_index(dev, 0, &clk);
  52. if (ret) {
  53. dev_err(dev, "%s: clock not defined\n", __func__);
  54. return ret;
  55. }
  56. priv->clk_rate = clk_get_rate(&clk);
  57. if (!priv->clk_rate) {
  58. dev_err(dev, "%s: failed to get clock rate\n", __func__);
  59. return -EINVAL;
  60. }
  61. return 0;
  62. }
  63. static int mpc8xxx_spi_probe(struct udevice *dev)
  64. {
  65. struct mpc8xxx_priv *priv = dev_get_priv(dev);
  66. spi8xxx_t *spi = priv->spi;
  67. /*
  68. * SPI pins on the MPC83xx are not muxed, so all we do is initialize
  69. * some registers
  70. */
  71. out_be32(&priv->spi->mode, SPI_MODE_REV | SPI_MODE_MS);
  72. /* set len to 8 bits */
  73. setbits_be32(&spi->mode, (8 - 1) << SPI_MODE_LEN_SHIFT);
  74. setbits_be32(&spi->mode, SPI_MODE_EN);
  75. /* Clear all SPI events */
  76. setbits_be32(&priv->spi->event, 0xffffffff);
  77. /* Mask all SPI interrupts */
  78. clrbits_be32(&priv->spi->mask, 0xffffffff);
  79. /* LST bit doesn't do anything, so disregard */
  80. out_be32(&priv->spi->com, 0);
  81. return 0;
  82. }
  83. static void mpc8xxx_spi_cs_activate(struct udevice *dev)
  84. {
  85. struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
  86. struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
  87. dm_gpio_set_dir_flags(&priv->gpios[platdata->cs], GPIOD_IS_OUT);
  88. dm_gpio_set_value(&priv->gpios[platdata->cs], 0);
  89. }
  90. static void mpc8xxx_spi_cs_deactivate(struct udevice *dev)
  91. {
  92. struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
  93. struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
  94. dm_gpio_set_dir_flags(&priv->gpios[platdata->cs], GPIOD_IS_OUT);
  95. dm_gpio_set_value(&priv->gpios[platdata->cs], 1);
  96. }
  97. static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen,
  98. const void *dout, void *din, ulong flags)
  99. {
  100. struct udevice *bus = dev->parent;
  101. struct mpc8xxx_priv *priv = dev_get_priv(bus);
  102. spi8xxx_t *spi = priv->spi;
  103. struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
  104. u32 tmpdin = 0, tmpdout = 0, n;
  105. const u8 *cout = dout;
  106. u8 *cin = din;
  107. debug("%s: slave %s:%u dout %08X din %08X bitlen %u\n", __func__,
  108. bus->name, platdata->cs, (uint)dout, (uint)din, bitlen);
  109. if (platdata->cs >= priv->cs_count) {
  110. dev_err(dev, "chip select index %d too large (cs_count=%d)\n",
  111. platdata->cs, priv->cs_count);
  112. return -EINVAL;
  113. }
  114. if (bitlen % 8) {
  115. printf("*** spi_xfer: bitlen must be multiple of 8\n");
  116. return -ENOTSUPP;
  117. }
  118. if (flags & SPI_XFER_BEGIN)
  119. mpc8xxx_spi_cs_activate(dev);
  120. /* Clear all SPI events */
  121. setbits_be32(&spi->event, 0xffffffff);
  122. n = bitlen / 8;
  123. /* Handle data in 8-bit chunks */
  124. while (n--) {
  125. ulong start;
  126. if (cout)
  127. tmpdout = *cout++;
  128. /* Write the data out */
  129. out_be32(&spi->tx, tmpdout);
  130. debug("*** %s: ... %08x written\n", __func__, tmpdout);
  131. /*
  132. * Wait for SPI transmit to get out
  133. * or time out (1 second = 1000 ms)
  134. * The NE event must be read and cleared first
  135. */
  136. start = get_timer(0);
  137. do {
  138. u32 event = in_be32(&spi->event);
  139. bool have_ne = event & SPI_EV_NE;
  140. bool have_nf = event & SPI_EV_NF;
  141. if (!have_ne)
  142. continue;
  143. tmpdin = in_be32(&spi->rx);
  144. setbits_be32(&spi->event, SPI_EV_NE);
  145. if (cin)
  146. *cin++ = tmpdin;
  147. /*
  148. * Only bail when we've had both NE and NF events.
  149. * This will cause timeouts on RO devices, so maybe
  150. * in the future put an arbitrary delay after writing
  151. * the device. Arbitrary delays suck, though...
  152. */
  153. if (have_nf)
  154. break;
  155. mdelay(1);
  156. } while (get_timer(start) < SPI_TIMEOUT);
  157. if (get_timer(start) >= SPI_TIMEOUT) {
  158. debug("*** %s: Time out during SPI transfer\n",
  159. __func__);
  160. return -ETIMEDOUT;
  161. }
  162. debug("*** %s: transfer ended. Value=%08x\n", __func__, tmpdin);
  163. }
  164. if (flags & SPI_XFER_END)
  165. mpc8xxx_spi_cs_deactivate(dev);
  166. return 0;
  167. }
  168. static int mpc8xxx_spi_set_speed(struct udevice *dev, uint speed)
  169. {
  170. struct mpc8xxx_priv *priv = dev_get_priv(dev);
  171. spi8xxx_t *spi = priv->spi;
  172. u32 bits, mask, div16, pm;
  173. u32 mode;
  174. ulong clk;
  175. clk = priv->clk_rate;
  176. if (clk / 64 > speed) {
  177. div16 = SPI_MODE_DIV16;
  178. clk /= 16;
  179. } else {
  180. div16 = 0;
  181. }
  182. pm = (clk - 1)/(4*speed) + 1;
  183. if (pm > 16) {
  184. dev_err(dev, "requested speed %u too small\n", speed);
  185. return -EINVAL;
  186. }
  187. pm--;
  188. bits = div16 | (pm << SPI_MODE_PM_SHIFT);
  189. mask = SPI_MODE_DIV16 | SPI_MODE_PM_MASK;
  190. mode = in_be32(&spi->mode);
  191. if ((mode & mask) != bits) {
  192. /* Must clear mode[EN] while changing speed. */
  193. mode &= ~(mask | SPI_MODE_EN);
  194. out_be32(&spi->mode, mode);
  195. mode |= bits;
  196. out_be32(&spi->mode, mode);
  197. mode |= SPI_MODE_EN;
  198. out_be32(&spi->mode, mode);
  199. }
  200. debug("requested speed %u, set speed to %lu/(%s4*%u) == %lu\n",
  201. speed, priv->clk_rate, div16 ? "16*" : "", pm + 1,
  202. clk/(4*(pm + 1)));
  203. return 0;
  204. }
  205. static int mpc8xxx_spi_set_mode(struct udevice *dev, uint mode)
  206. {
  207. /* TODO(mario.six@gdsys.cc): Using SPI_CPHA (for clock phase) and
  208. * SPI_CPOL (for clock polarity) should work
  209. */
  210. return 0;
  211. }
  212. static const struct dm_spi_ops mpc8xxx_spi_ops = {
  213. .xfer = mpc8xxx_spi_xfer,
  214. .set_speed = mpc8xxx_spi_set_speed,
  215. .set_mode = mpc8xxx_spi_set_mode,
  216. /*
  217. * cs_info is not needed, since we require all chip selects to be
  218. * in the device tree explicitly
  219. */
  220. };
  221. static const struct udevice_id mpc8xxx_spi_ids[] = {
  222. { .compatible = "fsl,spi" },
  223. { }
  224. };
  225. U_BOOT_DRIVER(mpc8xxx_spi) = {
  226. .name = "mpc8xxx_spi",
  227. .id = UCLASS_SPI,
  228. .of_match = mpc8xxx_spi_ids,
  229. .ops = &mpc8xxx_spi_ops,
  230. .ofdata_to_platdata = mpc8xxx_spi_ofdata_to_platdata,
  231. .probe = mpc8xxx_spi_probe,
  232. .priv_auto_alloc_size = sizeof(struct mpc8xxx_priv),
  233. };