pxa3xx_nand.c 50 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * drivers/mtd/nand/raw/pxa3xx_nand.c
  4. *
  5. * Copyright © 2005 Intel Corporation
  6. * Copyright © 2006 Marvell International Ltd.
  7. */
  8. #include <common.h>
  9. #include <malloc.h>
  10. #include <fdtdec.h>
  11. #include <nand.h>
  12. #include <dm/device_compat.h>
  13. #include <dm/devres.h>
  14. #include <linux/err.h>
  15. #include <linux/errno.h>
  16. #include <asm/io.h>
  17. #include <asm/arch/cpu.h>
  18. #include <linux/mtd/mtd.h>
  19. #include <linux/mtd/rawnand.h>
  20. #include <linux/types.h>
  21. #include "pxa3xx_nand.h"
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #define TIMEOUT_DRAIN_FIFO 5 /* in ms */
  24. #define CHIP_DELAY_TIMEOUT 200
  25. #define NAND_STOP_DELAY 40
  26. /*
  27. * Define a buffer size for the initial command that detects the flash device:
  28. * STATUS, READID and PARAM.
  29. * ONFI param page is 256 bytes, and there are three redundant copies
  30. * to be read. JEDEC param page is 512 bytes, and there are also three
  31. * redundant copies to be read.
  32. * Hence this buffer should be at least 512 x 3. Let's pick 2048.
  33. */
  34. #define INIT_BUFFER_SIZE 2048
  35. /* registers and bit definitions */
  36. #define NDCR (0x00) /* Control register */
  37. #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
  38. #define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
  39. #define NDSR (0x14) /* Status Register */
  40. #define NDPCR (0x18) /* Page Count Register */
  41. #define NDBDR0 (0x1C) /* Bad Block Register 0 */
  42. #define NDBDR1 (0x20) /* Bad Block Register 1 */
  43. #define NDECCCTRL (0x28) /* ECC control */
  44. #define NDDB (0x40) /* Data Buffer */
  45. #define NDCB0 (0x48) /* Command Buffer0 */
  46. #define NDCB1 (0x4C) /* Command Buffer1 */
  47. #define NDCB2 (0x50) /* Command Buffer2 */
  48. #define NDCR_SPARE_EN (0x1 << 31)
  49. #define NDCR_ECC_EN (0x1 << 30)
  50. #define NDCR_DMA_EN (0x1 << 29)
  51. #define NDCR_ND_RUN (0x1 << 28)
  52. #define NDCR_DWIDTH_C (0x1 << 27)
  53. #define NDCR_DWIDTH_M (0x1 << 26)
  54. #define NDCR_PAGE_SZ (0x1 << 24)
  55. #define NDCR_NCSX (0x1 << 23)
  56. #define NDCR_ND_MODE (0x3 << 21)
  57. #define NDCR_NAND_MODE (0x0)
  58. #define NDCR_CLR_PG_CNT (0x1 << 20)
  59. #define NFCV1_NDCR_ARB_CNTL (0x1 << 19)
  60. #define NDCR_RD_ID_CNT_MASK (0x7 << 16)
  61. #define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
  62. #define NDCR_RA_START (0x1 << 15)
  63. #define NDCR_PG_PER_BLK (0x1 << 14)
  64. #define NDCR_ND_ARB_EN (0x1 << 12)
  65. #define NDCR_INT_MASK (0xFFF)
  66. #define NDSR_MASK (0xfff)
  67. #define NDSR_ERR_CNT_OFF (16)
  68. #define NDSR_ERR_CNT_MASK (0x1f)
  69. #define NDSR_ERR_CNT(sr) ((sr >> NDSR_ERR_CNT_OFF) & NDSR_ERR_CNT_MASK)
  70. #define NDSR_RDY (0x1 << 12)
  71. #define NDSR_FLASH_RDY (0x1 << 11)
  72. #define NDSR_CS0_PAGED (0x1 << 10)
  73. #define NDSR_CS1_PAGED (0x1 << 9)
  74. #define NDSR_CS0_CMDD (0x1 << 8)
  75. #define NDSR_CS1_CMDD (0x1 << 7)
  76. #define NDSR_CS0_BBD (0x1 << 6)
  77. #define NDSR_CS1_BBD (0x1 << 5)
  78. #define NDSR_UNCORERR (0x1 << 4)
  79. #define NDSR_CORERR (0x1 << 3)
  80. #define NDSR_WRDREQ (0x1 << 2)
  81. #define NDSR_RDDREQ (0x1 << 1)
  82. #define NDSR_WRCMDREQ (0x1)
  83. #define NDCB0_LEN_OVRD (0x1 << 28)
  84. #define NDCB0_ST_ROW_EN (0x1 << 26)
  85. #define NDCB0_AUTO_RS (0x1 << 25)
  86. #define NDCB0_CSEL (0x1 << 24)
  87. #define NDCB0_EXT_CMD_TYPE_MASK (0x7 << 29)
  88. #define NDCB0_EXT_CMD_TYPE(x) (((x) << 29) & NDCB0_EXT_CMD_TYPE_MASK)
  89. #define NDCB0_CMD_TYPE_MASK (0x7 << 21)
  90. #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
  91. #define NDCB0_NC (0x1 << 20)
  92. #define NDCB0_DBC (0x1 << 19)
  93. #define NDCB0_ADDR_CYC_MASK (0x7 << 16)
  94. #define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
  95. #define NDCB0_CMD2_MASK (0xff << 8)
  96. #define NDCB0_CMD1_MASK (0xff)
  97. #define NDCB0_ADDR_CYC_SHIFT (16)
  98. #define EXT_CMD_TYPE_DISPATCH 6 /* Command dispatch */
  99. #define EXT_CMD_TYPE_NAKED_RW 5 /* Naked read or Naked write */
  100. #define EXT_CMD_TYPE_READ 4 /* Read */
  101. #define EXT_CMD_TYPE_DISP_WR 4 /* Command dispatch with write */
  102. #define EXT_CMD_TYPE_FINAL 3 /* Final command */
  103. #define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */
  104. #define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */
  105. /*
  106. * This should be large enough to read 'ONFI' and 'JEDEC'.
  107. * Let's use 7 bytes, which is the maximum ID count supported
  108. * by the controller (see NDCR_RD_ID_CNT_MASK).
  109. */
  110. #define READ_ID_BYTES 7
  111. /* macros for registers read/write */
  112. #define nand_writel(info, off, val) \
  113. writel((val), (info)->mmio_base + (off))
  114. #define nand_readl(info, off) \
  115. readl((info)->mmio_base + (off))
  116. /* error code and state */
  117. enum {
  118. ERR_NONE = 0,
  119. ERR_DMABUSERR = -1,
  120. ERR_SENDCMD = -2,
  121. ERR_UNCORERR = -3,
  122. ERR_BBERR = -4,
  123. ERR_CORERR = -5,
  124. };
  125. enum {
  126. STATE_IDLE = 0,
  127. STATE_PREPARED,
  128. STATE_CMD_HANDLE,
  129. STATE_DMA_READING,
  130. STATE_DMA_WRITING,
  131. STATE_DMA_DONE,
  132. STATE_PIO_READING,
  133. STATE_PIO_WRITING,
  134. STATE_CMD_DONE,
  135. STATE_READY,
  136. };
  137. enum pxa3xx_nand_variant {
  138. PXA3XX_NAND_VARIANT_PXA,
  139. PXA3XX_NAND_VARIANT_ARMADA370,
  140. };
  141. struct pxa3xx_nand_host {
  142. struct nand_chip chip;
  143. void *info_data;
  144. /* page size of attached chip */
  145. int use_ecc;
  146. int cs;
  147. /* calculated from pxa3xx_nand_flash data */
  148. unsigned int col_addr_cycles;
  149. unsigned int row_addr_cycles;
  150. };
  151. struct pxa3xx_nand_info {
  152. struct nand_hw_control controller;
  153. struct pxa3xx_nand_platform_data *pdata;
  154. struct clk *clk;
  155. void __iomem *mmio_base;
  156. unsigned long mmio_phys;
  157. int cmd_complete, dev_ready;
  158. unsigned int buf_start;
  159. unsigned int buf_count;
  160. unsigned int buf_size;
  161. unsigned int data_buff_pos;
  162. unsigned int oob_buff_pos;
  163. unsigned char *data_buff;
  164. unsigned char *oob_buff;
  165. struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
  166. unsigned int state;
  167. /*
  168. * This driver supports NFCv1 (as found in PXA SoC)
  169. * and NFCv2 (as found in Armada 370/XP SoC).
  170. */
  171. enum pxa3xx_nand_variant variant;
  172. int cs;
  173. int use_ecc; /* use HW ECC ? */
  174. int force_raw; /* prevent use_ecc to be set */
  175. int ecc_bch; /* using BCH ECC? */
  176. int use_spare; /* use spare ? */
  177. int need_wait;
  178. /* Amount of real data per full chunk */
  179. unsigned int chunk_size;
  180. /* Amount of spare data per full chunk */
  181. unsigned int spare_size;
  182. /* Number of full chunks (i.e chunk_size + spare_size) */
  183. unsigned int nfullchunks;
  184. /*
  185. * Total number of chunks. If equal to nfullchunks, then there
  186. * are only full chunks. Otherwise, there is one last chunk of
  187. * size (last_chunk_size + last_spare_size)
  188. */
  189. unsigned int ntotalchunks;
  190. /* Amount of real data in the last chunk */
  191. unsigned int last_chunk_size;
  192. /* Amount of spare data in the last chunk */
  193. unsigned int last_spare_size;
  194. unsigned int ecc_size;
  195. unsigned int ecc_err_cnt;
  196. unsigned int max_bitflips;
  197. int retcode;
  198. /*
  199. * Variables only valid during command
  200. * execution. step_chunk_size and step_spare_size is the
  201. * amount of real data and spare data in the current
  202. * chunk. cur_chunk is the current chunk being
  203. * read/programmed.
  204. */
  205. unsigned int step_chunk_size;
  206. unsigned int step_spare_size;
  207. unsigned int cur_chunk;
  208. /* cached register value */
  209. uint32_t reg_ndcr;
  210. uint32_t ndtr0cs0;
  211. uint32_t ndtr1cs0;
  212. /* generated NDCBx register values */
  213. uint32_t ndcb0;
  214. uint32_t ndcb1;
  215. uint32_t ndcb2;
  216. uint32_t ndcb3;
  217. };
  218. static struct pxa3xx_nand_timing timing[] = {
  219. /*
  220. * tCH Enable signal hold time
  221. * tCS Enable signal setup time
  222. * tWH ND_nWE high duration
  223. * tWP ND_nWE pulse time
  224. * tRH ND_nRE high duration
  225. * tRP ND_nRE pulse width
  226. * tR ND_nWE high to ND_nRE low for read
  227. * tWHR ND_nWE high to ND_nRE low for status read
  228. * tAR ND_ALE low to ND_nRE low delay
  229. */
  230. /*ch cs wh wp rh rp r whr ar */
  231. { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
  232. { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
  233. { 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
  234. { 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
  235. { 5, 20, 10, 12, 10, 12, 25000, 60, 10, },
  236. };
  237. static struct pxa3xx_nand_flash builtin_flash_types[] = {
  238. /*
  239. * chip_id
  240. * flash_width Width of Flash memory (DWIDTH_M)
  241. * dfc_width Width of flash controller(DWIDTH_C)
  242. * *timing
  243. * http://www.linux-mtd.infradead.org/nand-data/nanddata.html
  244. */
  245. { 0x46ec, 16, 16, &timing[1] },
  246. { 0xdaec, 8, 8, &timing[1] },
  247. { 0xd7ec, 8, 8, &timing[1] },
  248. { 0xa12c, 8, 8, &timing[2] },
  249. { 0xb12c, 16, 16, &timing[2] },
  250. { 0xdc2c, 8, 8, &timing[2] },
  251. { 0xcc2c, 16, 16, &timing[2] },
  252. { 0xba20, 16, 16, &timing[3] },
  253. { 0xda98, 8, 8, &timing[4] },
  254. };
  255. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  256. static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
  257. static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
  258. static struct nand_bbt_descr bbt_main_descr = {
  259. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
  260. | NAND_BBT_2BIT | NAND_BBT_VERSION,
  261. .offs = 8,
  262. .len = 6,
  263. .veroffs = 14,
  264. .maxblocks = 8, /* Last 8 blocks in each chip */
  265. .pattern = bbt_pattern
  266. };
  267. static struct nand_bbt_descr bbt_mirror_descr = {
  268. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
  269. | NAND_BBT_2BIT | NAND_BBT_VERSION,
  270. .offs = 8,
  271. .len = 6,
  272. .veroffs = 14,
  273. .maxblocks = 8, /* Last 8 blocks in each chip */
  274. .pattern = bbt_mirror_pattern
  275. };
  276. #endif
  277. static struct nand_ecclayout ecc_layout_2KB_bch4bit = {
  278. .eccbytes = 32,
  279. .eccpos = {
  280. 32, 33, 34, 35, 36, 37, 38, 39,
  281. 40, 41, 42, 43, 44, 45, 46, 47,
  282. 48, 49, 50, 51, 52, 53, 54, 55,
  283. 56, 57, 58, 59, 60, 61, 62, 63},
  284. .oobfree = { {2, 30} }
  285. };
  286. static struct nand_ecclayout ecc_layout_2KB_bch8bit = {
  287. .eccbytes = 64,
  288. .eccpos = {
  289. 32, 33, 34, 35, 36, 37, 38, 39,
  290. 40, 41, 42, 43, 44, 45, 46, 47,
  291. 48, 49, 50, 51, 52, 53, 54, 55,
  292. 56, 57, 58, 59, 60, 61, 62, 63,
  293. 64, 65, 66, 67, 68, 69, 70, 71,
  294. 72, 73, 74, 75, 76, 77, 78, 79,
  295. 80, 81, 82, 83, 84, 85, 86, 87,
  296. 88, 89, 90, 91, 92, 93, 94, 95},
  297. .oobfree = { {1, 4}, {6, 26} }
  298. };
  299. static struct nand_ecclayout ecc_layout_4KB_bch4bit = {
  300. .eccbytes = 64,
  301. .eccpos = {
  302. 32, 33, 34, 35, 36, 37, 38, 39,
  303. 40, 41, 42, 43, 44, 45, 46, 47,
  304. 48, 49, 50, 51, 52, 53, 54, 55,
  305. 56, 57, 58, 59, 60, 61, 62, 63,
  306. 96, 97, 98, 99, 100, 101, 102, 103,
  307. 104, 105, 106, 107, 108, 109, 110, 111,
  308. 112, 113, 114, 115, 116, 117, 118, 119,
  309. 120, 121, 122, 123, 124, 125, 126, 127},
  310. /* Bootrom looks in bytes 0 & 5 for bad blocks */
  311. .oobfree = { {6, 26}, { 64, 32} }
  312. };
  313. static struct nand_ecclayout ecc_layout_8KB_bch4bit = {
  314. .eccbytes = 128,
  315. .eccpos = {
  316. 32, 33, 34, 35, 36, 37, 38, 39,
  317. 40, 41, 42, 43, 44, 45, 46, 47,
  318. 48, 49, 50, 51, 52, 53, 54, 55,
  319. 56, 57, 58, 59, 60, 61, 62, 63,
  320. 96, 97, 98, 99, 100, 101, 102, 103,
  321. 104, 105, 106, 107, 108, 109, 110, 111,
  322. 112, 113, 114, 115, 116, 117, 118, 119,
  323. 120, 121, 122, 123, 124, 125, 126, 127,
  324. 160, 161, 162, 163, 164, 165, 166, 167,
  325. 168, 169, 170, 171, 172, 173, 174, 175,
  326. 176, 177, 178, 179, 180, 181, 182, 183,
  327. 184, 185, 186, 187, 188, 189, 190, 191,
  328. 224, 225, 226, 227, 228, 229, 230, 231,
  329. 232, 233, 234, 235, 236, 237, 238, 239,
  330. 240, 241, 242, 243, 244, 245, 246, 247,
  331. 248, 249, 250, 251, 252, 253, 254, 255},
  332. /* Bootrom looks in bytes 0 & 5 for bad blocks */
  333. .oobfree = { {1, 4}, {6, 26}, { 64, 32}, {128, 32}, {192, 32} }
  334. };
  335. static struct nand_ecclayout ecc_layout_4KB_bch8bit = {
  336. .eccbytes = 128,
  337. .eccpos = {
  338. 32, 33, 34, 35, 36, 37, 38, 39,
  339. 40, 41, 42, 43, 44, 45, 46, 47,
  340. 48, 49, 50, 51, 52, 53, 54, 55,
  341. 56, 57, 58, 59, 60, 61, 62, 63},
  342. .oobfree = { }
  343. };
  344. static struct nand_ecclayout ecc_layout_8KB_bch8bit = {
  345. .eccbytes = 256,
  346. .eccpos = {},
  347. /* HW ECC handles all ECC data and all spare area is free for OOB */
  348. .oobfree = {{0, 160} }
  349. };
  350. #define NDTR0_tCH(c) (min((c), 7) << 19)
  351. #define NDTR0_tCS(c) (min((c), 7) << 16)
  352. #define NDTR0_tWH(c) (min((c), 7) << 11)
  353. #define NDTR0_tWP(c) (min((c), 7) << 8)
  354. #define NDTR0_tRH(c) (min((c), 7) << 3)
  355. #define NDTR0_tRP(c) (min((c), 7) << 0)
  356. #define NDTR1_tR(c) (min((c), 65535) << 16)
  357. #define NDTR1_tWHR(c) (min((c), 15) << 4)
  358. #define NDTR1_tAR(c) (min((c), 15) << 0)
  359. /* convert nano-seconds to nand flash controller clock cycles */
  360. #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
  361. static enum pxa3xx_nand_variant pxa3xx_nand_get_variant(void)
  362. {
  363. /* We only support the Armada 370/XP/38x for now */
  364. return PXA3XX_NAND_VARIANT_ARMADA370;
  365. }
  366. static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
  367. const struct pxa3xx_nand_timing *t)
  368. {
  369. struct pxa3xx_nand_info *info = host->info_data;
  370. unsigned long nand_clk = mvebu_get_nand_clock();
  371. uint32_t ndtr0, ndtr1;
  372. ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
  373. NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
  374. NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
  375. NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
  376. NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
  377. NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
  378. ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
  379. NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
  380. NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
  381. info->ndtr0cs0 = ndtr0;
  382. info->ndtr1cs0 = ndtr1;
  383. nand_writel(info, NDTR0CS0, ndtr0);
  384. nand_writel(info, NDTR1CS0, ndtr1);
  385. }
  386. static void pxa3xx_nand_set_sdr_timing(struct pxa3xx_nand_host *host,
  387. const struct nand_sdr_timings *t)
  388. {
  389. struct pxa3xx_nand_info *info = host->info_data;
  390. struct nand_chip *chip = &host->chip;
  391. unsigned long nand_clk = mvebu_get_nand_clock();
  392. uint32_t ndtr0, ndtr1;
  393. u32 tCH_min = DIV_ROUND_UP(t->tCH_min, 1000);
  394. u32 tCS_min = DIV_ROUND_UP(t->tCS_min, 1000);
  395. u32 tWH_min = DIV_ROUND_UP(t->tWH_min, 1000);
  396. u32 tWP_min = DIV_ROUND_UP(t->tWC_min - t->tWH_min, 1000);
  397. u32 tREH_min = DIV_ROUND_UP(t->tREH_min, 1000);
  398. u32 tRP_min = DIV_ROUND_UP(t->tRC_min - t->tREH_min, 1000);
  399. u32 tR = chip->chip_delay * 1000;
  400. u32 tWHR_min = DIV_ROUND_UP(t->tWHR_min, 1000);
  401. u32 tAR_min = DIV_ROUND_UP(t->tAR_min, 1000);
  402. /* fallback to a default value if tR = 0 */
  403. if (!tR)
  404. tR = 20000;
  405. ndtr0 = NDTR0_tCH(ns2cycle(tCH_min, nand_clk)) |
  406. NDTR0_tCS(ns2cycle(tCS_min, nand_clk)) |
  407. NDTR0_tWH(ns2cycle(tWH_min, nand_clk)) |
  408. NDTR0_tWP(ns2cycle(tWP_min, nand_clk)) |
  409. NDTR0_tRH(ns2cycle(tREH_min, nand_clk)) |
  410. NDTR0_tRP(ns2cycle(tRP_min, nand_clk));
  411. ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) |
  412. NDTR1_tWHR(ns2cycle(tWHR_min, nand_clk)) |
  413. NDTR1_tAR(ns2cycle(tAR_min, nand_clk));
  414. info->ndtr0cs0 = ndtr0;
  415. info->ndtr1cs0 = ndtr1;
  416. nand_writel(info, NDTR0CS0, ndtr0);
  417. nand_writel(info, NDTR1CS0, ndtr1);
  418. }
  419. static int pxa3xx_nand_init_timings(struct pxa3xx_nand_host *host)
  420. {
  421. const struct nand_sdr_timings *timings;
  422. struct nand_chip *chip = &host->chip;
  423. struct pxa3xx_nand_info *info = host->info_data;
  424. const struct pxa3xx_nand_flash *f = NULL;
  425. struct mtd_info *mtd = nand_to_mtd(&host->chip);
  426. int mode, id, ntypes, i;
  427. mode = onfi_get_async_timing_mode(chip);
  428. if (mode == ONFI_TIMING_MODE_UNKNOWN) {
  429. ntypes = ARRAY_SIZE(builtin_flash_types);
  430. chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
  431. id = chip->read_byte(mtd);
  432. id |= chip->read_byte(mtd) << 0x8;
  433. for (i = 0; i < ntypes; i++) {
  434. f = &builtin_flash_types[i];
  435. if (f->chip_id == id)
  436. break;
  437. }
  438. if (i == ntypes) {
  439. dev_err(&info->pdev->dev, "Error: timings not found\n");
  440. return -EINVAL;
  441. }
  442. pxa3xx_nand_set_timing(host, f->timing);
  443. if (f->flash_width == 16) {
  444. info->reg_ndcr |= NDCR_DWIDTH_M;
  445. chip->options |= NAND_BUSWIDTH_16;
  446. }
  447. info->reg_ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
  448. } else {
  449. mode = fls(mode) - 1;
  450. if (mode < 0)
  451. mode = 0;
  452. timings = onfi_async_timing_mode_to_sdr_timings(mode);
  453. if (IS_ERR(timings))
  454. return PTR_ERR(timings);
  455. pxa3xx_nand_set_sdr_timing(host, timings);
  456. }
  457. return 0;
  458. }
  459. /**
  460. * NOTE: it is a must to set ND_RUN first, then write
  461. * command buffer, otherwise, it does not work.
  462. * We enable all the interrupt at the same time, and
  463. * let pxa3xx_nand_irq to handle all logic.
  464. */
  465. static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
  466. {
  467. uint32_t ndcr;
  468. ndcr = info->reg_ndcr;
  469. if (info->use_ecc) {
  470. ndcr |= NDCR_ECC_EN;
  471. if (info->ecc_bch)
  472. nand_writel(info, NDECCCTRL, 0x1);
  473. } else {
  474. ndcr &= ~NDCR_ECC_EN;
  475. if (info->ecc_bch)
  476. nand_writel(info, NDECCCTRL, 0x0);
  477. }
  478. ndcr &= ~NDCR_DMA_EN;
  479. if (info->use_spare)
  480. ndcr |= NDCR_SPARE_EN;
  481. else
  482. ndcr &= ~NDCR_SPARE_EN;
  483. ndcr |= NDCR_ND_RUN;
  484. /* clear status bits and run */
  485. nand_writel(info, NDSR, NDSR_MASK);
  486. nand_writel(info, NDCR, 0);
  487. nand_writel(info, NDCR, ndcr);
  488. }
  489. static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
  490. {
  491. uint32_t ndcr;
  492. ndcr = nand_readl(info, NDCR);
  493. nand_writel(info, NDCR, ndcr | int_mask);
  494. }
  495. static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
  496. {
  497. if (info->ecc_bch && !info->force_raw) {
  498. u32 ts;
  499. /*
  500. * According to the datasheet, when reading from NDDB
  501. * with BCH enabled, after each 32 bytes reads, we
  502. * have to make sure that the NDSR.RDDREQ bit is set.
  503. *
  504. * Drain the FIFO 8 32 bits reads at a time, and skip
  505. * the polling on the last read.
  506. */
  507. while (len > 8) {
  508. readsl(info->mmio_base + NDDB, data, 8);
  509. ts = get_timer(0);
  510. while (!(nand_readl(info, NDSR) & NDSR_RDDREQ)) {
  511. if (get_timer(ts) > TIMEOUT_DRAIN_FIFO) {
  512. dev_err(&info->pdev->dev,
  513. "Timeout on RDDREQ while draining the FIFO\n");
  514. return;
  515. }
  516. }
  517. data += 32;
  518. len -= 8;
  519. }
  520. }
  521. readsl(info->mmio_base + NDDB, data, len);
  522. }
  523. static void handle_data_pio(struct pxa3xx_nand_info *info)
  524. {
  525. int data_len = info->step_chunk_size;
  526. /*
  527. * In raw mode, include the spare area and the ECC bytes that are not
  528. * consumed by the controller in the data section. Do not reorganize
  529. * here, do it in the ->read_page_raw() handler instead.
  530. */
  531. if (info->force_raw)
  532. data_len += info->step_spare_size + info->ecc_size;
  533. switch (info->state) {
  534. case STATE_PIO_WRITING:
  535. if (info->step_chunk_size)
  536. writesl(info->mmio_base + NDDB,
  537. info->data_buff + info->data_buff_pos,
  538. DIV_ROUND_UP(data_len, 4));
  539. if (info->step_spare_size)
  540. writesl(info->mmio_base + NDDB,
  541. info->oob_buff + info->oob_buff_pos,
  542. DIV_ROUND_UP(info->step_spare_size, 4));
  543. break;
  544. case STATE_PIO_READING:
  545. if (data_len)
  546. drain_fifo(info,
  547. info->data_buff + info->data_buff_pos,
  548. DIV_ROUND_UP(data_len, 4));
  549. if (info->force_raw)
  550. break;
  551. if (info->step_spare_size)
  552. drain_fifo(info,
  553. info->oob_buff + info->oob_buff_pos,
  554. DIV_ROUND_UP(info->step_spare_size, 4));
  555. break;
  556. default:
  557. dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
  558. info->state);
  559. BUG();
  560. }
  561. /* Update buffer pointers for multi-page read/write */
  562. info->data_buff_pos += data_len;
  563. info->oob_buff_pos += info->step_spare_size;
  564. }
  565. static void pxa3xx_nand_irq_thread(struct pxa3xx_nand_info *info)
  566. {
  567. handle_data_pio(info);
  568. info->state = STATE_CMD_DONE;
  569. nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
  570. }
  571. static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
  572. {
  573. unsigned int status, is_completed = 0, is_ready = 0;
  574. unsigned int ready, cmd_done;
  575. irqreturn_t ret = IRQ_HANDLED;
  576. if (info->cs == 0) {
  577. ready = NDSR_FLASH_RDY;
  578. cmd_done = NDSR_CS0_CMDD;
  579. } else {
  580. ready = NDSR_RDY;
  581. cmd_done = NDSR_CS1_CMDD;
  582. }
  583. /* TODO - find out why we need the delay during write operation. */
  584. ndelay(1);
  585. status = nand_readl(info, NDSR);
  586. if (status & NDSR_UNCORERR)
  587. info->retcode = ERR_UNCORERR;
  588. if (status & NDSR_CORERR) {
  589. info->retcode = ERR_CORERR;
  590. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 &&
  591. info->ecc_bch)
  592. info->ecc_err_cnt = NDSR_ERR_CNT(status);
  593. else
  594. info->ecc_err_cnt = 1;
  595. /*
  596. * Each chunk composing a page is corrected independently,
  597. * and we need to store maximum number of corrected bitflips
  598. * to return it to the MTD layer in ecc.read_page().
  599. */
  600. info->max_bitflips = max_t(unsigned int,
  601. info->max_bitflips,
  602. info->ecc_err_cnt);
  603. }
  604. if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
  605. info->state = (status & NDSR_RDDREQ) ?
  606. STATE_PIO_READING : STATE_PIO_WRITING;
  607. /* Call the IRQ thread in U-Boot directly */
  608. pxa3xx_nand_irq_thread(info);
  609. return 0;
  610. }
  611. if (status & cmd_done) {
  612. info->state = STATE_CMD_DONE;
  613. is_completed = 1;
  614. }
  615. if (status & ready) {
  616. info->state = STATE_READY;
  617. is_ready = 1;
  618. }
  619. /*
  620. * Clear all status bit before issuing the next command, which
  621. * can and will alter the status bits and will deserve a new
  622. * interrupt on its own. This lets the controller exit the IRQ
  623. */
  624. nand_writel(info, NDSR, status);
  625. if (status & NDSR_WRCMDREQ) {
  626. status &= ~NDSR_WRCMDREQ;
  627. info->state = STATE_CMD_HANDLE;
  628. /*
  629. * Command buffer registers NDCB{0-2} (and optionally NDCB3)
  630. * must be loaded by writing directly either 12 or 16
  631. * bytes directly to NDCB0, four bytes at a time.
  632. *
  633. * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored
  634. * but each NDCBx register can be read.
  635. */
  636. nand_writel(info, NDCB0, info->ndcb0);
  637. nand_writel(info, NDCB0, info->ndcb1);
  638. nand_writel(info, NDCB0, info->ndcb2);
  639. /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
  640. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
  641. nand_writel(info, NDCB0, info->ndcb3);
  642. }
  643. if (is_completed)
  644. info->cmd_complete = 1;
  645. if (is_ready)
  646. info->dev_ready = 1;
  647. return ret;
  648. }
  649. static inline int is_buf_blank(uint8_t *buf, size_t len)
  650. {
  651. for (; len > 0; len--)
  652. if (*buf++ != 0xff)
  653. return 0;
  654. return 1;
  655. }
  656. static void set_command_address(struct pxa3xx_nand_info *info,
  657. unsigned int page_size, uint16_t column, int page_addr)
  658. {
  659. /* small page addr setting */
  660. if (page_size < info->chunk_size) {
  661. info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
  662. | (column & 0xFF);
  663. info->ndcb2 = 0;
  664. } else {
  665. info->ndcb1 = ((page_addr & 0xFFFF) << 16)
  666. | (column & 0xFFFF);
  667. if (page_addr & 0xFF0000)
  668. info->ndcb2 = (page_addr & 0xFF0000) >> 16;
  669. else
  670. info->ndcb2 = 0;
  671. }
  672. }
  673. static void prepare_start_command(struct pxa3xx_nand_info *info, int command)
  674. {
  675. struct pxa3xx_nand_host *host = info->host[info->cs];
  676. struct mtd_info *mtd = nand_to_mtd(&host->chip);
  677. /* reset data and oob column point to handle data */
  678. info->buf_start = 0;
  679. info->buf_count = 0;
  680. info->data_buff_pos = 0;
  681. info->oob_buff_pos = 0;
  682. info->step_chunk_size = 0;
  683. info->step_spare_size = 0;
  684. info->cur_chunk = 0;
  685. info->use_ecc = 0;
  686. info->use_spare = 1;
  687. info->retcode = ERR_NONE;
  688. info->ecc_err_cnt = 0;
  689. info->ndcb3 = 0;
  690. info->need_wait = 0;
  691. switch (command) {
  692. case NAND_CMD_READ0:
  693. case NAND_CMD_READOOB:
  694. case NAND_CMD_PAGEPROG:
  695. if (!info->force_raw)
  696. info->use_ecc = 1;
  697. break;
  698. case NAND_CMD_PARAM:
  699. info->use_spare = 0;
  700. break;
  701. default:
  702. info->ndcb1 = 0;
  703. info->ndcb2 = 0;
  704. break;
  705. }
  706. /*
  707. * If we are about to issue a read command, or about to set
  708. * the write address, then clean the data buffer.
  709. */
  710. if (command == NAND_CMD_READ0 ||
  711. command == NAND_CMD_READOOB ||
  712. command == NAND_CMD_SEQIN) {
  713. info->buf_count = mtd->writesize + mtd->oobsize;
  714. memset(info->data_buff, 0xFF, info->buf_count);
  715. }
  716. }
  717. static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
  718. int ext_cmd_type, uint16_t column, int page_addr)
  719. {
  720. int addr_cycle, exec_cmd;
  721. struct pxa3xx_nand_host *host;
  722. struct mtd_info *mtd;
  723. host = info->host[info->cs];
  724. mtd = nand_to_mtd(&host->chip);
  725. addr_cycle = 0;
  726. exec_cmd = 1;
  727. if (info->cs != 0)
  728. info->ndcb0 = NDCB0_CSEL;
  729. else
  730. info->ndcb0 = 0;
  731. if (command == NAND_CMD_SEQIN)
  732. exec_cmd = 0;
  733. addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
  734. + host->col_addr_cycles);
  735. switch (command) {
  736. case NAND_CMD_READOOB:
  737. case NAND_CMD_READ0:
  738. info->buf_start = column;
  739. info->ndcb0 |= NDCB0_CMD_TYPE(0)
  740. | addr_cycle
  741. | NAND_CMD_READ0;
  742. if (command == NAND_CMD_READOOB)
  743. info->buf_start += mtd->writesize;
  744. if (info->cur_chunk < info->nfullchunks) {
  745. info->step_chunk_size = info->chunk_size;
  746. info->step_spare_size = info->spare_size;
  747. } else {
  748. info->step_chunk_size = info->last_chunk_size;
  749. info->step_spare_size = info->last_spare_size;
  750. }
  751. /*
  752. * Multiple page read needs an 'extended command type' field,
  753. * which is either naked-read or last-read according to the
  754. * state.
  755. */
  756. if (info->force_raw) {
  757. info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8) |
  758. NDCB0_LEN_OVRD |
  759. NDCB0_EXT_CMD_TYPE(ext_cmd_type);
  760. info->ndcb3 = info->step_chunk_size +
  761. info->step_spare_size + info->ecc_size;
  762. } else if (mtd->writesize == info->chunk_size) {
  763. info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
  764. } else if (mtd->writesize > info->chunk_size) {
  765. info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8)
  766. | NDCB0_LEN_OVRD
  767. | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
  768. info->ndcb3 = info->step_chunk_size +
  769. info->step_spare_size;
  770. }
  771. set_command_address(info, mtd->writesize, column, page_addr);
  772. break;
  773. case NAND_CMD_SEQIN:
  774. info->buf_start = column;
  775. set_command_address(info, mtd->writesize, 0, page_addr);
  776. /*
  777. * Multiple page programming needs to execute the initial
  778. * SEQIN command that sets the page address.
  779. */
  780. if (mtd->writesize > info->chunk_size) {
  781. info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
  782. | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
  783. | addr_cycle
  784. | command;
  785. exec_cmd = 1;
  786. }
  787. break;
  788. case NAND_CMD_PAGEPROG:
  789. if (is_buf_blank(info->data_buff,
  790. (mtd->writesize + mtd->oobsize))) {
  791. exec_cmd = 0;
  792. break;
  793. }
  794. if (info->cur_chunk < info->nfullchunks) {
  795. info->step_chunk_size = info->chunk_size;
  796. info->step_spare_size = info->spare_size;
  797. } else {
  798. info->step_chunk_size = info->last_chunk_size;
  799. info->step_spare_size = info->last_spare_size;
  800. }
  801. /* Second command setting for large pages */
  802. if (mtd->writesize > info->chunk_size) {
  803. /*
  804. * Multiple page write uses the 'extended command'
  805. * field. This can be used to issue a command dispatch
  806. * or a naked-write depending on the current stage.
  807. */
  808. info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
  809. | NDCB0_LEN_OVRD
  810. | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
  811. info->ndcb3 = info->step_chunk_size +
  812. info->step_spare_size;
  813. /*
  814. * This is the command dispatch that completes a chunked
  815. * page program operation.
  816. */
  817. if (info->cur_chunk == info->ntotalchunks) {
  818. info->ndcb0 = NDCB0_CMD_TYPE(0x1)
  819. | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
  820. | command;
  821. info->ndcb1 = 0;
  822. info->ndcb2 = 0;
  823. info->ndcb3 = 0;
  824. }
  825. } else {
  826. info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
  827. | NDCB0_AUTO_RS
  828. | NDCB0_ST_ROW_EN
  829. | NDCB0_DBC
  830. | (NAND_CMD_PAGEPROG << 8)
  831. | NAND_CMD_SEQIN
  832. | addr_cycle;
  833. }
  834. break;
  835. case NAND_CMD_PARAM:
  836. info->buf_count = INIT_BUFFER_SIZE;
  837. info->ndcb0 |= NDCB0_CMD_TYPE(0)
  838. | NDCB0_ADDR_CYC(1)
  839. | NDCB0_LEN_OVRD
  840. | command;
  841. info->ndcb1 = (column & 0xFF);
  842. info->ndcb3 = INIT_BUFFER_SIZE;
  843. info->step_chunk_size = INIT_BUFFER_SIZE;
  844. break;
  845. case NAND_CMD_READID:
  846. info->buf_count = READ_ID_BYTES;
  847. info->ndcb0 |= NDCB0_CMD_TYPE(3)
  848. | NDCB0_ADDR_CYC(1)
  849. | command;
  850. info->ndcb1 = (column & 0xFF);
  851. info->step_chunk_size = 8;
  852. break;
  853. case NAND_CMD_STATUS:
  854. info->buf_count = 1;
  855. info->ndcb0 |= NDCB0_CMD_TYPE(4)
  856. | NDCB0_ADDR_CYC(1)
  857. | command;
  858. info->step_chunk_size = 8;
  859. break;
  860. case NAND_CMD_ERASE1:
  861. info->ndcb0 |= NDCB0_CMD_TYPE(2)
  862. | NDCB0_AUTO_RS
  863. | NDCB0_ADDR_CYC(3)
  864. | NDCB0_DBC
  865. | (NAND_CMD_ERASE2 << 8)
  866. | NAND_CMD_ERASE1;
  867. info->ndcb1 = page_addr;
  868. info->ndcb2 = 0;
  869. break;
  870. case NAND_CMD_RESET:
  871. info->ndcb0 |= NDCB0_CMD_TYPE(5)
  872. | command;
  873. break;
  874. case NAND_CMD_ERASE2:
  875. exec_cmd = 0;
  876. break;
  877. default:
  878. exec_cmd = 0;
  879. dev_err(&info->pdev->dev, "non-supported command %x\n",
  880. command);
  881. break;
  882. }
  883. return exec_cmd;
  884. }
  885. static void nand_cmdfunc(struct mtd_info *mtd, unsigned command,
  886. int column, int page_addr)
  887. {
  888. struct nand_chip *chip = mtd_to_nand(mtd);
  889. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  890. struct pxa3xx_nand_info *info = host->info_data;
  891. int exec_cmd;
  892. /*
  893. * if this is a x16 device ,then convert the input
  894. * "byte" address into a "word" address appropriate
  895. * for indexing a word-oriented device
  896. */
  897. if (info->reg_ndcr & NDCR_DWIDTH_M)
  898. column /= 2;
  899. /*
  900. * There may be different NAND chip hooked to
  901. * different chip select, so check whether
  902. * chip select has been changed, if yes, reset the timing
  903. */
  904. if (info->cs != host->cs) {
  905. info->cs = host->cs;
  906. nand_writel(info, NDTR0CS0, info->ndtr0cs0);
  907. nand_writel(info, NDTR1CS0, info->ndtr1cs0);
  908. }
  909. prepare_start_command(info, command);
  910. info->state = STATE_PREPARED;
  911. exec_cmd = prepare_set_command(info, command, 0, column, page_addr);
  912. if (exec_cmd) {
  913. u32 ts;
  914. info->cmd_complete = 0;
  915. info->dev_ready = 0;
  916. info->need_wait = 1;
  917. pxa3xx_nand_start(info);
  918. ts = get_timer(0);
  919. while (1) {
  920. u32 status;
  921. status = nand_readl(info, NDSR);
  922. if (status)
  923. pxa3xx_nand_irq(info);
  924. if (info->cmd_complete)
  925. break;
  926. if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
  927. dev_err(&info->pdev->dev, "Wait timeout!!!\n");
  928. return;
  929. }
  930. }
  931. }
  932. info->state = STATE_IDLE;
  933. }
  934. static void nand_cmdfunc_extended(struct mtd_info *mtd,
  935. const unsigned command,
  936. int column, int page_addr)
  937. {
  938. struct nand_chip *chip = mtd_to_nand(mtd);
  939. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  940. struct pxa3xx_nand_info *info = host->info_data;
  941. int exec_cmd, ext_cmd_type;
  942. /*
  943. * if this is a x16 device then convert the input
  944. * "byte" address into a "word" address appropriate
  945. * for indexing a word-oriented device
  946. */
  947. if (info->reg_ndcr & NDCR_DWIDTH_M)
  948. column /= 2;
  949. /*
  950. * There may be different NAND chip hooked to
  951. * different chip select, so check whether
  952. * chip select has been changed, if yes, reset the timing
  953. */
  954. if (info->cs != host->cs) {
  955. info->cs = host->cs;
  956. nand_writel(info, NDTR0CS0, info->ndtr0cs0);
  957. nand_writel(info, NDTR1CS0, info->ndtr1cs0);
  958. }
  959. /* Select the extended command for the first command */
  960. switch (command) {
  961. case NAND_CMD_READ0:
  962. case NAND_CMD_READOOB:
  963. ext_cmd_type = EXT_CMD_TYPE_MONO;
  964. break;
  965. case NAND_CMD_SEQIN:
  966. ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
  967. break;
  968. case NAND_CMD_PAGEPROG:
  969. ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
  970. break;
  971. default:
  972. ext_cmd_type = 0;
  973. break;
  974. }
  975. prepare_start_command(info, command);
  976. /*
  977. * Prepare the "is ready" completion before starting a command
  978. * transaction sequence. If the command is not executed the
  979. * completion will be completed, see below.
  980. *
  981. * We can do that inside the loop because the command variable
  982. * is invariant and thus so is the exec_cmd.
  983. */
  984. info->need_wait = 1;
  985. info->dev_ready = 0;
  986. do {
  987. u32 ts;
  988. info->state = STATE_PREPARED;
  989. exec_cmd = prepare_set_command(info, command, ext_cmd_type,
  990. column, page_addr);
  991. if (!exec_cmd) {
  992. info->need_wait = 0;
  993. info->dev_ready = 1;
  994. break;
  995. }
  996. info->cmd_complete = 0;
  997. pxa3xx_nand_start(info);
  998. ts = get_timer(0);
  999. while (1) {
  1000. u32 status;
  1001. status = nand_readl(info, NDSR);
  1002. if (status)
  1003. pxa3xx_nand_irq(info);
  1004. if (info->cmd_complete)
  1005. break;
  1006. if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
  1007. dev_err(&info->pdev->dev, "Wait timeout!!!\n");
  1008. return;
  1009. }
  1010. }
  1011. /* Only a few commands need several steps */
  1012. if (command != NAND_CMD_PAGEPROG &&
  1013. command != NAND_CMD_READ0 &&
  1014. command != NAND_CMD_READOOB)
  1015. break;
  1016. info->cur_chunk++;
  1017. /* Check if the sequence is complete */
  1018. if (info->cur_chunk == info->ntotalchunks &&
  1019. command != NAND_CMD_PAGEPROG)
  1020. break;
  1021. /*
  1022. * After a splitted program command sequence has issued
  1023. * the command dispatch, the command sequence is complete.
  1024. */
  1025. if (info->cur_chunk == (info->ntotalchunks + 1) &&
  1026. command == NAND_CMD_PAGEPROG &&
  1027. ext_cmd_type == EXT_CMD_TYPE_DISPATCH)
  1028. break;
  1029. if (command == NAND_CMD_READ0 || command == NAND_CMD_READOOB) {
  1030. /* Last read: issue a 'last naked read' */
  1031. if (info->cur_chunk == info->ntotalchunks - 1)
  1032. ext_cmd_type = EXT_CMD_TYPE_LAST_RW;
  1033. else
  1034. ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
  1035. /*
  1036. * If a splitted program command has no more data to transfer,
  1037. * the command dispatch must be issued to complete.
  1038. */
  1039. } else if (command == NAND_CMD_PAGEPROG &&
  1040. info->cur_chunk == info->ntotalchunks) {
  1041. ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
  1042. }
  1043. } while (1);
  1044. info->state = STATE_IDLE;
  1045. }
  1046. static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
  1047. struct nand_chip *chip, const uint8_t *buf, int oob_required,
  1048. int page)
  1049. {
  1050. chip->write_buf(mtd, buf, mtd->writesize);
  1051. chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
  1052. return 0;
  1053. }
  1054. static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
  1055. struct nand_chip *chip, uint8_t *buf, int oob_required,
  1056. int page)
  1057. {
  1058. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1059. struct pxa3xx_nand_info *info = host->info_data;
  1060. int bf;
  1061. chip->read_buf(mtd, buf, mtd->writesize);
  1062. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  1063. if (info->retcode == ERR_CORERR && info->use_ecc) {
  1064. mtd->ecc_stats.corrected += info->ecc_err_cnt;
  1065. } else if (info->retcode == ERR_UNCORERR && info->ecc_bch) {
  1066. /*
  1067. * Empty pages will trigger uncorrectable errors. Re-read the
  1068. * entire page in raw mode and check for bits not being "1".
  1069. * If there are more than the supported strength, then it means
  1070. * this is an actual uncorrectable error.
  1071. */
  1072. chip->ecc.read_page_raw(mtd, chip, buf, oob_required, page);
  1073. bf = nand_check_erased_ecc_chunk(buf, mtd->writesize,
  1074. chip->oob_poi, mtd->oobsize,
  1075. NULL, 0, chip->ecc.strength);
  1076. if (bf < 0) {
  1077. mtd->ecc_stats.failed++;
  1078. } else if (bf) {
  1079. mtd->ecc_stats.corrected += bf;
  1080. info->max_bitflips = max_t(unsigned int,
  1081. info->max_bitflips, bf);
  1082. info->retcode = ERR_CORERR;
  1083. } else {
  1084. info->retcode = ERR_NONE;
  1085. }
  1086. } else if (info->retcode == ERR_UNCORERR && !info->ecc_bch) {
  1087. /* Raw read is not supported with Hamming ECC engine */
  1088. if (is_buf_blank(buf, mtd->writesize))
  1089. info->retcode = ERR_NONE;
  1090. else
  1091. mtd->ecc_stats.failed++;
  1092. }
  1093. return info->max_bitflips;
  1094. }
  1095. static int pxa3xx_nand_read_page_raw(struct mtd_info *mtd,
  1096. struct nand_chip *chip, uint8_t *buf,
  1097. int oob_required, int page)
  1098. {
  1099. struct pxa3xx_nand_host *host = chip->priv;
  1100. struct pxa3xx_nand_info *info = host->info_data;
  1101. int chunk, ecc_off_buf;
  1102. if (!info->ecc_bch)
  1103. return -ENOTSUPP;
  1104. /*
  1105. * Set the force_raw boolean, then re-call ->cmdfunc() that will run
  1106. * pxa3xx_nand_start(), which will actually disable the ECC engine.
  1107. */
  1108. info->force_raw = true;
  1109. chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
  1110. ecc_off_buf = (info->nfullchunks * info->spare_size) +
  1111. info->last_spare_size;
  1112. for (chunk = 0; chunk < info->nfullchunks; chunk++) {
  1113. chip->read_buf(mtd,
  1114. buf + (chunk * info->chunk_size),
  1115. info->chunk_size);
  1116. chip->read_buf(mtd,
  1117. chip->oob_poi +
  1118. (chunk * (info->spare_size)),
  1119. info->spare_size);
  1120. chip->read_buf(mtd,
  1121. chip->oob_poi + ecc_off_buf +
  1122. (chunk * (info->ecc_size)),
  1123. info->ecc_size - 2);
  1124. }
  1125. if (info->ntotalchunks > info->nfullchunks) {
  1126. chip->read_buf(mtd,
  1127. buf + (info->nfullchunks * info->chunk_size),
  1128. info->last_chunk_size);
  1129. chip->read_buf(mtd,
  1130. chip->oob_poi +
  1131. (info->nfullchunks * (info->spare_size)),
  1132. info->last_spare_size);
  1133. chip->read_buf(mtd,
  1134. chip->oob_poi + ecc_off_buf +
  1135. (info->nfullchunks * (info->ecc_size)),
  1136. info->ecc_size - 2);
  1137. }
  1138. info->force_raw = false;
  1139. return 0;
  1140. }
  1141. static int pxa3xx_nand_read_oob_raw(struct mtd_info *mtd,
  1142. struct nand_chip *chip, int page)
  1143. {
  1144. /* Invalidate page cache */
  1145. chip->pagebuf = -1;
  1146. return chip->ecc.read_page_raw(mtd, chip, chip->buffers->databuf, true,
  1147. page);
  1148. }
  1149. static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
  1150. {
  1151. struct nand_chip *chip = mtd_to_nand(mtd);
  1152. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1153. struct pxa3xx_nand_info *info = host->info_data;
  1154. char retval = 0xFF;
  1155. if (info->buf_start < info->buf_count)
  1156. /* Has just send a new command? */
  1157. retval = info->data_buff[info->buf_start++];
  1158. return retval;
  1159. }
  1160. static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
  1161. {
  1162. struct nand_chip *chip = mtd_to_nand(mtd);
  1163. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1164. struct pxa3xx_nand_info *info = host->info_data;
  1165. u16 retval = 0xFFFF;
  1166. if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
  1167. retval = *((u16 *)(info->data_buff+info->buf_start));
  1168. info->buf_start += 2;
  1169. }
  1170. return retval;
  1171. }
  1172. static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  1173. {
  1174. struct nand_chip *chip = mtd_to_nand(mtd);
  1175. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1176. struct pxa3xx_nand_info *info = host->info_data;
  1177. int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
  1178. memcpy(buf, info->data_buff + info->buf_start, real_len);
  1179. info->buf_start += real_len;
  1180. }
  1181. static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
  1182. const uint8_t *buf, int len)
  1183. {
  1184. struct nand_chip *chip = mtd_to_nand(mtd);
  1185. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1186. struct pxa3xx_nand_info *info = host->info_data;
  1187. int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
  1188. memcpy(info->data_buff + info->buf_start, buf, real_len);
  1189. info->buf_start += real_len;
  1190. }
  1191. static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
  1192. {
  1193. return;
  1194. }
  1195. static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
  1196. {
  1197. struct nand_chip *chip = mtd_to_nand(mtd);
  1198. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1199. struct pxa3xx_nand_info *info = host->info_data;
  1200. if (info->need_wait) {
  1201. u32 ts;
  1202. info->need_wait = 0;
  1203. ts = get_timer(0);
  1204. while (1) {
  1205. u32 status;
  1206. status = nand_readl(info, NDSR);
  1207. if (status)
  1208. pxa3xx_nand_irq(info);
  1209. if (info->dev_ready)
  1210. break;
  1211. if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
  1212. dev_err(&info->pdev->dev, "Ready timeout!!!\n");
  1213. return NAND_STATUS_FAIL;
  1214. }
  1215. }
  1216. }
  1217. /* pxa3xx_nand_send_command has waited for command complete */
  1218. if (this->state == FL_WRITING || this->state == FL_ERASING) {
  1219. if (info->retcode == ERR_NONE)
  1220. return 0;
  1221. else
  1222. return NAND_STATUS_FAIL;
  1223. }
  1224. return NAND_STATUS_READY;
  1225. }
  1226. static int pxa3xx_nand_config_ident(struct pxa3xx_nand_info *info)
  1227. {
  1228. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1229. /* Configure default flash values */
  1230. info->reg_ndcr = 0x0; /* enable all interrupts */
  1231. info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
  1232. info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
  1233. info->reg_ndcr |= NDCR_SPARE_EN;
  1234. return 0;
  1235. }
  1236. static void pxa3xx_nand_config_tail(struct pxa3xx_nand_info *info)
  1237. {
  1238. struct pxa3xx_nand_host *host = info->host[info->cs];
  1239. struct mtd_info *mtd = nand_to_mtd(&info->host[info->cs]->chip);
  1240. struct nand_chip *chip = mtd_to_nand(mtd);
  1241. info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
  1242. info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0;
  1243. info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0;
  1244. }
  1245. static void pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
  1246. {
  1247. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1248. uint32_t ndcr = nand_readl(info, NDCR);
  1249. /* Set an initial chunk size */
  1250. info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
  1251. info->reg_ndcr = ndcr &
  1252. ~(NDCR_INT_MASK | NDCR_ND_ARB_EN | NFCV1_NDCR_ARB_CNTL);
  1253. info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
  1254. info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
  1255. info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
  1256. }
  1257. static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
  1258. {
  1259. info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
  1260. if (info->data_buff == NULL)
  1261. return -ENOMEM;
  1262. return 0;
  1263. }
  1264. static int pxa3xx_nand_sensing(struct pxa3xx_nand_host *host)
  1265. {
  1266. struct pxa3xx_nand_info *info = host->info_data;
  1267. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1268. struct mtd_info *mtd;
  1269. struct nand_chip *chip;
  1270. const struct nand_sdr_timings *timings;
  1271. int ret;
  1272. mtd = nand_to_mtd(&info->host[info->cs]->chip);
  1273. chip = mtd_to_nand(mtd);
  1274. /* configure default flash values */
  1275. info->reg_ndcr = 0x0; /* enable all interrupts */
  1276. info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
  1277. info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
  1278. info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */
  1279. /* use the common timing to make a try */
  1280. timings = onfi_async_timing_mode_to_sdr_timings(0);
  1281. if (IS_ERR(timings))
  1282. return PTR_ERR(timings);
  1283. pxa3xx_nand_set_sdr_timing(host, timings);
  1284. chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
  1285. ret = chip->waitfunc(mtd, chip);
  1286. if (ret & NAND_STATUS_FAIL)
  1287. return -ENODEV;
  1288. return 0;
  1289. }
  1290. static int pxa_ecc_init(struct pxa3xx_nand_info *info,
  1291. struct nand_ecc_ctrl *ecc,
  1292. int strength, int ecc_stepsize, int page_size)
  1293. {
  1294. if (strength == 1 && ecc_stepsize == 512 && page_size == 2048) {
  1295. info->nfullchunks = 1;
  1296. info->ntotalchunks = 1;
  1297. info->chunk_size = 2048;
  1298. info->spare_size = 40;
  1299. info->ecc_size = 24;
  1300. ecc->mode = NAND_ECC_HW;
  1301. ecc->size = 512;
  1302. ecc->strength = 1;
  1303. } else if (strength == 1 && ecc_stepsize == 512 && page_size == 512) {
  1304. info->nfullchunks = 1;
  1305. info->ntotalchunks = 1;
  1306. info->chunk_size = 512;
  1307. info->spare_size = 8;
  1308. info->ecc_size = 8;
  1309. ecc->mode = NAND_ECC_HW;
  1310. ecc->size = 512;
  1311. ecc->strength = 1;
  1312. /*
  1313. * Required ECC: 4-bit correction per 512 bytes
  1314. * Select: 16-bit correction per 2048 bytes
  1315. */
  1316. } else if (strength == 4 && ecc_stepsize == 512 && page_size == 2048) {
  1317. info->ecc_bch = 1;
  1318. info->nfullchunks = 1;
  1319. info->ntotalchunks = 1;
  1320. info->chunk_size = 2048;
  1321. info->spare_size = 32;
  1322. info->ecc_size = 32;
  1323. ecc->mode = NAND_ECC_HW;
  1324. ecc->size = info->chunk_size;
  1325. ecc->layout = &ecc_layout_2KB_bch4bit;
  1326. ecc->strength = 16;
  1327. } else if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) {
  1328. info->ecc_bch = 1;
  1329. info->nfullchunks = 2;
  1330. info->ntotalchunks = 2;
  1331. info->chunk_size = 2048;
  1332. info->spare_size = 32;
  1333. info->ecc_size = 32;
  1334. ecc->mode = NAND_ECC_HW;
  1335. ecc->size = info->chunk_size;
  1336. ecc->layout = &ecc_layout_4KB_bch4bit;
  1337. ecc->strength = 16;
  1338. } else if (strength == 4 && ecc_stepsize == 512 && page_size == 8192) {
  1339. info->ecc_bch = 1;
  1340. info->nfullchunks = 4;
  1341. info->ntotalchunks = 4;
  1342. info->chunk_size = 2048;
  1343. info->spare_size = 32;
  1344. info->ecc_size = 32;
  1345. ecc->mode = NAND_ECC_HW;
  1346. ecc->size = info->chunk_size;
  1347. ecc->layout = &ecc_layout_8KB_bch4bit;
  1348. ecc->strength = 16;
  1349. /*
  1350. * Required ECC: 8-bit correction per 512 bytes
  1351. * Select: 16-bit correction per 1024 bytes
  1352. */
  1353. } else if (strength == 8 && ecc_stepsize == 512 && page_size == 2048) {
  1354. info->ecc_bch = 1;
  1355. info->nfullchunks = 1;
  1356. info->ntotalchunks = 2;
  1357. info->chunk_size = 1024;
  1358. info->spare_size = 0;
  1359. info->last_chunk_size = 1024;
  1360. info->last_spare_size = 32;
  1361. info->ecc_size = 32;
  1362. ecc->mode = NAND_ECC_HW;
  1363. ecc->size = info->chunk_size;
  1364. ecc->layout = &ecc_layout_2KB_bch8bit;
  1365. ecc->strength = 16;
  1366. } else if (strength == 8 && ecc_stepsize == 512 && page_size == 4096) {
  1367. info->ecc_bch = 1;
  1368. info->nfullchunks = 4;
  1369. info->ntotalchunks = 5;
  1370. info->chunk_size = 1024;
  1371. info->spare_size = 0;
  1372. info->last_chunk_size = 0;
  1373. info->last_spare_size = 64;
  1374. info->ecc_size = 32;
  1375. ecc->mode = NAND_ECC_HW;
  1376. ecc->size = info->chunk_size;
  1377. ecc->layout = &ecc_layout_4KB_bch8bit;
  1378. ecc->strength = 16;
  1379. } else if (strength == 8 && ecc_stepsize == 512 && page_size == 8192) {
  1380. info->ecc_bch = 1;
  1381. info->nfullchunks = 8;
  1382. info->ntotalchunks = 9;
  1383. info->chunk_size = 1024;
  1384. info->spare_size = 0;
  1385. info->last_chunk_size = 0;
  1386. info->last_spare_size = 160;
  1387. info->ecc_size = 32;
  1388. ecc->mode = NAND_ECC_HW;
  1389. ecc->size = info->chunk_size;
  1390. ecc->layout = &ecc_layout_8KB_bch8bit;
  1391. ecc->strength = 16;
  1392. } else {
  1393. dev_err(&info->pdev->dev,
  1394. "ECC strength %d at page size %d is not supported\n",
  1395. strength, page_size);
  1396. return -ENODEV;
  1397. }
  1398. return 0;
  1399. }
  1400. static int pxa3xx_nand_scan(struct mtd_info *mtd)
  1401. {
  1402. struct nand_chip *chip = mtd_to_nand(mtd);
  1403. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1404. struct pxa3xx_nand_info *info = host->info_data;
  1405. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1406. int ret;
  1407. uint16_t ecc_strength, ecc_step;
  1408. if (pdata->keep_config) {
  1409. pxa3xx_nand_detect_config(info);
  1410. } else {
  1411. ret = pxa3xx_nand_config_ident(info);
  1412. if (ret)
  1413. return ret;
  1414. ret = pxa3xx_nand_sensing(host);
  1415. if (ret) {
  1416. dev_info(&info->pdev->dev,
  1417. "There is no chip on cs %d!\n",
  1418. info->cs);
  1419. return ret;
  1420. }
  1421. }
  1422. /* Device detection must be done with ECC disabled */
  1423. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
  1424. nand_writel(info, NDECCCTRL, 0x0);
  1425. if (nand_scan_ident(mtd, 1, NULL))
  1426. return -ENODEV;
  1427. if (!pdata->keep_config) {
  1428. ret = pxa3xx_nand_init_timings(host);
  1429. if (ret) {
  1430. dev_err(&info->pdev->dev,
  1431. "Failed to set timings: %d\n", ret);
  1432. return ret;
  1433. }
  1434. }
  1435. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  1436. /*
  1437. * We'll use a bad block table stored in-flash and don't
  1438. * allow writing the bad block marker to the flash.
  1439. */
  1440. chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB_BBM;
  1441. chip->bbt_td = &bbt_main_descr;
  1442. chip->bbt_md = &bbt_mirror_descr;
  1443. #endif
  1444. if (pdata->ecc_strength && pdata->ecc_step_size) {
  1445. ecc_strength = pdata->ecc_strength;
  1446. ecc_step = pdata->ecc_step_size;
  1447. } else {
  1448. ecc_strength = chip->ecc_strength_ds;
  1449. ecc_step = chip->ecc_step_ds;
  1450. }
  1451. /* Set default ECC strength requirements on non-ONFI devices */
  1452. if (ecc_strength < 1 && ecc_step < 1) {
  1453. ecc_strength = 1;
  1454. ecc_step = 512;
  1455. }
  1456. ret = pxa_ecc_init(info, &chip->ecc, ecc_strength,
  1457. ecc_step, mtd->writesize);
  1458. if (ret)
  1459. return ret;
  1460. /*
  1461. * If the page size is bigger than the FIFO size, let's check
  1462. * we are given the right variant and then switch to the extended
  1463. * (aka split) command handling,
  1464. */
  1465. if (mtd->writesize > info->chunk_size) {
  1466. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) {
  1467. chip->cmdfunc = nand_cmdfunc_extended;
  1468. } else {
  1469. dev_err(&info->pdev->dev,
  1470. "unsupported page size on this variant\n");
  1471. return -ENODEV;
  1472. }
  1473. }
  1474. /* calculate addressing information */
  1475. if (mtd->writesize >= 2048)
  1476. host->col_addr_cycles = 2;
  1477. else
  1478. host->col_addr_cycles = 1;
  1479. /* release the initial buffer */
  1480. kfree(info->data_buff);
  1481. /* allocate the real data + oob buffer */
  1482. info->buf_size = mtd->writesize + mtd->oobsize;
  1483. ret = pxa3xx_nand_init_buff(info);
  1484. if (ret)
  1485. return ret;
  1486. info->oob_buff = info->data_buff + mtd->writesize;
  1487. if ((mtd->size >> chip->page_shift) > 65536)
  1488. host->row_addr_cycles = 3;
  1489. else
  1490. host->row_addr_cycles = 2;
  1491. if (!pdata->keep_config)
  1492. pxa3xx_nand_config_tail(info);
  1493. return nand_scan_tail(mtd);
  1494. }
  1495. static int alloc_nand_resource(struct pxa3xx_nand_info *info)
  1496. {
  1497. struct pxa3xx_nand_platform_data *pdata;
  1498. struct pxa3xx_nand_host *host;
  1499. struct nand_chip *chip = NULL;
  1500. struct mtd_info *mtd;
  1501. int ret, cs;
  1502. pdata = info->pdata;
  1503. if (pdata->num_cs <= 0)
  1504. return -ENODEV;
  1505. info->variant = pxa3xx_nand_get_variant();
  1506. for (cs = 0; cs < pdata->num_cs; cs++) {
  1507. chip = (struct nand_chip *)
  1508. ((u8 *)&info[1] + sizeof(*host) * cs);
  1509. mtd = nand_to_mtd(chip);
  1510. host = (struct pxa3xx_nand_host *)chip;
  1511. info->host[cs] = host;
  1512. host->cs = cs;
  1513. host->info_data = info;
  1514. mtd->owner = THIS_MODULE;
  1515. nand_set_controller_data(chip, host);
  1516. chip->ecc.read_page = pxa3xx_nand_read_page_hwecc;
  1517. chip->ecc.read_page_raw = pxa3xx_nand_read_page_raw;
  1518. chip->ecc.read_oob_raw = pxa3xx_nand_read_oob_raw;
  1519. chip->ecc.write_page = pxa3xx_nand_write_page_hwecc;
  1520. chip->controller = &info->controller;
  1521. chip->waitfunc = pxa3xx_nand_waitfunc;
  1522. chip->select_chip = pxa3xx_nand_select_chip;
  1523. chip->read_word = pxa3xx_nand_read_word;
  1524. chip->read_byte = pxa3xx_nand_read_byte;
  1525. chip->read_buf = pxa3xx_nand_read_buf;
  1526. chip->write_buf = pxa3xx_nand_write_buf;
  1527. chip->options |= NAND_NO_SUBPAGE_WRITE;
  1528. chip->cmdfunc = nand_cmdfunc;
  1529. }
  1530. /* Allocate a buffer to allow flash detection */
  1531. info->buf_size = INIT_BUFFER_SIZE;
  1532. info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
  1533. if (info->data_buff == NULL) {
  1534. ret = -ENOMEM;
  1535. goto fail_disable_clk;
  1536. }
  1537. /* initialize all interrupts to be disabled */
  1538. disable_int(info, NDSR_MASK);
  1539. return 0;
  1540. kfree(info->data_buff);
  1541. fail_disable_clk:
  1542. return ret;
  1543. }
  1544. static int pxa3xx_nand_probe_dt(struct pxa3xx_nand_info *info)
  1545. {
  1546. struct pxa3xx_nand_platform_data *pdata;
  1547. const void *blob = gd->fdt_blob;
  1548. int node = -1;
  1549. pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
  1550. if (!pdata)
  1551. return -ENOMEM;
  1552. /* Get address decoding nodes from the FDT blob */
  1553. do {
  1554. node = fdt_node_offset_by_compatible(blob, node,
  1555. "marvell,mvebu-pxa3xx-nand");
  1556. if (node < 0)
  1557. break;
  1558. /* Bypass disabeld nodes */
  1559. if (!fdtdec_get_is_enabled(blob, node))
  1560. continue;
  1561. /* Get the first enabled NAND controler base address */
  1562. info->mmio_base =
  1563. (void __iomem *)fdtdec_get_addr_size_auto_noparent(
  1564. blob, node, "reg", 0, NULL, true);
  1565. pdata->num_cs = fdtdec_get_int(blob, node, "num-cs", 1);
  1566. if (pdata->num_cs != 1) {
  1567. pr_err("pxa3xx driver supports single CS only\n");
  1568. break;
  1569. }
  1570. if (fdtdec_get_bool(blob, node, "nand-enable-arbiter"))
  1571. pdata->enable_arbiter = 1;
  1572. if (fdtdec_get_bool(blob, node, "nand-keep-config"))
  1573. pdata->keep_config = 1;
  1574. /*
  1575. * ECC parameters.
  1576. * If these are not set, they will be selected according
  1577. * to the detected flash type.
  1578. */
  1579. /* ECC strength */
  1580. pdata->ecc_strength = fdtdec_get_int(blob, node,
  1581. "nand-ecc-strength", 0);
  1582. /* ECC step size */
  1583. pdata->ecc_step_size = fdtdec_get_int(blob, node,
  1584. "nand-ecc-step-size", 0);
  1585. info->pdata = pdata;
  1586. /* Currently support only a single NAND controller */
  1587. return 0;
  1588. } while (node >= 0);
  1589. return -EINVAL;
  1590. }
  1591. static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info)
  1592. {
  1593. struct pxa3xx_nand_platform_data *pdata;
  1594. int ret, cs, probe_success;
  1595. ret = pxa3xx_nand_probe_dt(info);
  1596. if (ret)
  1597. return ret;
  1598. pdata = info->pdata;
  1599. ret = alloc_nand_resource(info);
  1600. if (ret) {
  1601. dev_err(&pdev->dev, "alloc nand resource failed\n");
  1602. return ret;
  1603. }
  1604. probe_success = 0;
  1605. for (cs = 0; cs < pdata->num_cs; cs++) {
  1606. struct mtd_info *mtd = nand_to_mtd(&info->host[cs]->chip);
  1607. /*
  1608. * The mtd name matches the one used in 'mtdparts' kernel
  1609. * parameter. This name cannot be changed or otherwise
  1610. * user's mtd partitions configuration would get broken.
  1611. */
  1612. mtd->name = "pxa3xx_nand-0";
  1613. info->cs = cs;
  1614. ret = pxa3xx_nand_scan(mtd);
  1615. if (ret) {
  1616. dev_info(&pdev->dev, "failed to scan nand at cs %d\n",
  1617. cs);
  1618. continue;
  1619. }
  1620. if (nand_register(cs, mtd))
  1621. continue;
  1622. probe_success = 1;
  1623. }
  1624. if (!probe_success)
  1625. return -ENODEV;
  1626. return 0;
  1627. }
  1628. /*
  1629. * Main initialization routine
  1630. */
  1631. void board_nand_init(void)
  1632. {
  1633. struct pxa3xx_nand_info *info;
  1634. struct pxa3xx_nand_host *host;
  1635. int ret;
  1636. info = kzalloc(sizeof(*info) +
  1637. sizeof(*host) * CONFIG_SYS_MAX_NAND_DEVICE,
  1638. GFP_KERNEL);
  1639. if (!info)
  1640. return;
  1641. ret = pxa3xx_nand_probe(info);
  1642. if (ret)
  1643. return;
  1644. }