cpu.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 - 2018 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <asm/armv8/mmu.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/hardware.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <asm/cache.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. #define VERSAL_MEM_MAP_USED 5
  14. #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
  15. #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  16. #define TCM_MAP 1
  17. #else
  18. #define TCM_MAP 0
  19. #endif
  20. /* +1 is end of list which needs to be empty */
  21. #define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
  22. static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = {
  23. {
  24. .virt = 0x80000000UL,
  25. .phys = 0x80000000UL,
  26. .size = 0x70000000UL,
  27. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  28. PTE_BLOCK_NON_SHARE |
  29. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  30. }, {
  31. .virt = 0xf0000000UL,
  32. .phys = 0xf0000000UL,
  33. .size = 0x0fe00000UL,
  34. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  35. PTE_BLOCK_NON_SHARE |
  36. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  37. }, {
  38. .virt = 0x400000000UL,
  39. .phys = 0x400000000UL,
  40. .size = 0x200000000UL,
  41. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  42. PTE_BLOCK_NON_SHARE |
  43. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  44. }, {
  45. .virt = 0x600000000UL,
  46. .phys = 0x600000000UL,
  47. .size = 0x800000000UL,
  48. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  49. PTE_BLOCK_INNER_SHARE
  50. }, {
  51. .virt = 0xe00000000UL,
  52. .phys = 0xe00000000UL,
  53. .size = 0xf200000000UL,
  54. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  55. PTE_BLOCK_NON_SHARE |
  56. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  57. }
  58. };
  59. void mem_map_fill(void)
  60. {
  61. int banks = VERSAL_MEM_MAP_USED;
  62. #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  63. versal_mem_map[banks].virt = 0xffe00000UL;
  64. versal_mem_map[banks].phys = 0xffe00000UL;
  65. versal_mem_map[banks].size = 0x00200000UL;
  66. versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  67. PTE_BLOCK_INNER_SHARE;
  68. banks = banks + 1;
  69. #endif
  70. for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  71. /* Zero size means no more DDR that's this is end */
  72. if (!gd->bd->bi_dram[i].size)
  73. break;
  74. #if defined(CONFIG_VERSAL_NO_DDR)
  75. if (gd->bd->bi_dram[i].start < 0x80000000UL ||
  76. gd->bd->bi_dram[i].start > 0x100000000UL) {
  77. printf("Ignore caches over %llx/%llx\n",
  78. gd->bd->bi_dram[i].start,
  79. gd->bd->bi_dram[i].size);
  80. continue;
  81. }
  82. #endif
  83. versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
  84. versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
  85. versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
  86. versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  87. PTE_BLOCK_INNER_SHARE;
  88. banks = banks + 1;
  89. }
  90. }
  91. struct mm_region *mem_map = versal_mem_map;
  92. u64 get_page_table_size(void)
  93. {
  94. return 0x14000;
  95. }
  96. #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU)
  97. int arm_reserve_mmu(void)
  98. {
  99. tcm_init(TCM_LOCK);
  100. gd->arch.tlb_size = PGTABLE_SIZE;
  101. gd->arch.tlb_addr = VERSAL_TCM_BASE_ADDR;
  102. return 0;
  103. }
  104. #endif