cache.h 1.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2009
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. */
  7. #ifndef _ASM_CACHE_H
  8. #define _ASM_CACHE_H
  9. #include <asm/system.h>
  10. #ifndef CONFIG_ARM64
  11. /*
  12. * Invalidate L2 Cache using co-proc instruction
  13. */
  14. #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
  15. void invalidate_l2_cache(void);
  16. #else
  17. static inline void invalidate_l2_cache(void)
  18. {
  19. unsigned int val=0;
  20. asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
  21. : : "r" (val) : "cc");
  22. isb();
  23. }
  24. #endif
  25. int check_cache_range(unsigned long start, unsigned long stop);
  26. void l2_cache_enable(void);
  27. void l2_cache_disable(void);
  28. void set_section_dcache(int section, enum dcache_option option);
  29. void arm_init_before_mmu(void);
  30. void arm_init_domains(void);
  31. void cpu_cache_initialization(void);
  32. void dram_bank_mmu_setup(int bank);
  33. #endif
  34. /*
  35. * The value of the largest data cache relevant to DMA operations shall be set
  36. * for us in CONFIG_SYS_CACHELINE_SIZE. In some cases this may be a larger
  37. * value than found in the L1 cache but this is OK to use in terms of
  38. * alignment.
  39. */
  40. #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
  41. /*
  42. * arm_reserve_mmu() - Reserve memory for MMU TLB table
  43. *
  44. * Default implementation for reserving memory for MMU TLB table. It is used
  45. * during generic board init sequence in common/board_f.c. Weakly defined, so
  46. * that machines can override it if needed.
  47. *
  48. * Return: 0 if OK
  49. */
  50. int arm_reserve_mmu(void);
  51. #endif /* _ASM_CACHE_H */