s900.dtsi 8.1 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2017 Andreas Färber
  4. */
  5. #include <dt-bindings/clock/actions,s900-cmu.h>
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/interrupt-controller/arm-gic.h>
  8. #include <dt-bindings/reset/actions,s900-reset.h>
  9. / {
  10. compatible = "actions,s900";
  11. interrupt-parent = <&gic>;
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. cpus {
  15. #address-cells = <2>;
  16. #size-cells = <0>;
  17. cpu0: cpu@0 {
  18. device_type = "cpu";
  19. compatible = "arm,cortex-a53";
  20. reg = <0x0 0x0>;
  21. enable-method = "psci";
  22. };
  23. cpu1: cpu@1 {
  24. device_type = "cpu";
  25. compatible = "arm,cortex-a53";
  26. reg = <0x0 0x1>;
  27. enable-method = "psci";
  28. };
  29. cpu2: cpu@2 {
  30. device_type = "cpu";
  31. compatible = "arm,cortex-a53";
  32. reg = <0x0 0x2>;
  33. enable-method = "psci";
  34. };
  35. cpu3: cpu@3 {
  36. device_type = "cpu";
  37. compatible = "arm,cortex-a53";
  38. reg = <0x0 0x3>;
  39. enable-method = "psci";
  40. };
  41. };
  42. reserved-memory {
  43. #address-cells = <2>;
  44. #size-cells = <2>;
  45. ranges;
  46. secmon@1f000000 {
  47. reg = <0x0 0x1f000000 0x0 0x1000000>;
  48. no-map;
  49. };
  50. };
  51. psci {
  52. compatible = "arm,psci-0.2";
  53. method = "smc";
  54. };
  55. arm-pmu {
  56. compatible = "arm,cortex-a53-pmu";
  57. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  58. <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
  59. <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  60. <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  61. interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  62. };
  63. timer {
  64. compatible = "arm,armv8-timer";
  65. interrupts = <GIC_PPI 13
  66. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  67. <GIC_PPI 14
  68. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  69. <GIC_PPI 11
  70. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  71. <GIC_PPI 10
  72. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  73. };
  74. hosc: hosc {
  75. compatible = "fixed-clock";
  76. clock-frequency = <24000000>;
  77. #clock-cells = <0>;
  78. };
  79. losc: losc {
  80. compatible = "fixed-clock";
  81. clock-frequency = <32768>;
  82. #clock-cells = <0>;
  83. };
  84. diff24M: diff24M {
  85. compatible = "fixed-clock";
  86. clock-frequency = <24000000>;
  87. #clock-cells = <0>;
  88. };
  89. soc {
  90. compatible = "simple-bus";
  91. #address-cells = <2>;
  92. #size-cells = <2>;
  93. ranges;
  94. gic: interrupt-controller@e00f1000 {
  95. compatible = "arm,gic-400";
  96. reg = <0x0 0xe00f1000 0x0 0x1000>,
  97. <0x0 0xe00f2000 0x0 0x2000>,
  98. <0x0 0xe00f4000 0x0 0x2000>,
  99. <0x0 0xe00f6000 0x0 0x2000>;
  100. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  101. interrupt-controller;
  102. #interrupt-cells = <3>;
  103. };
  104. uart0: serial@e0120000 {
  105. compatible = "actions,s900-uart", "actions,owl-uart";
  106. reg = <0x0 0xe0120000 0x0 0x2000>;
  107. clocks = <&cmu CLK_UART0>;
  108. interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  109. status = "disabled";
  110. };
  111. uart1: serial@e0122000 {
  112. compatible = "actions,s900-uart", "actions,owl-uart";
  113. reg = <0x0 0xe0122000 0x0 0x2000>;
  114. clocks = <&cmu CLK_UART1>;
  115. interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  116. status = "disabled";
  117. };
  118. uart2: serial@e0124000 {
  119. compatible = "actions,s900-uart", "actions,owl-uart";
  120. reg = <0x0 0xe0124000 0x0 0x2000>;
  121. clocks = <&cmu CLK_UART2>;
  122. interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  123. status = "disabled";
  124. };
  125. uart3: serial@e0126000 {
  126. compatible = "actions,s900-uart", "actions,owl-uart";
  127. reg = <0x0 0xe0126000 0x0 0x2000>;
  128. clocks = <&cmu CLK_UART3>;
  129. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  130. status = "disabled";
  131. };
  132. uart4: serial@e0128000 {
  133. compatible = "actions,s900-uart", "actions,owl-uart";
  134. reg = <0x0 0xe0128000 0x0 0x2000>;
  135. clocks = <&cmu CLK_UART4>;
  136. interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  137. status = "disabled";
  138. };
  139. uart5: serial@e012a000 {
  140. compatible = "actions,s900-uart", "actions,owl-uart";
  141. reg = <0x0 0xe012a000 0x0 0x2000>;
  142. clocks = <&cmu CLK_UART5>;
  143. interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  144. status = "disabled";
  145. };
  146. uart6: serial@e012c000 {
  147. compatible = "actions,s900-uart", "actions,owl-uart";
  148. reg = <0x0 0xe012c000 0x0 0x2000>;
  149. clocks = <&cmu CLK_UART6>;
  150. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  151. status = "disabled";
  152. };
  153. sps: power-controller@e012e000 {
  154. compatible = "actions,s900-sps";
  155. reg = <0x0 0xe012e000 0x0 0x2000>;
  156. #power-domain-cells = <1>;
  157. };
  158. cmu: clock-controller@e0160000 {
  159. compatible = "actions,s900-cmu";
  160. reg = <0x0 0xe0160000 0x0 0x1000>;
  161. clocks = <&hosc>, <&losc>;
  162. #clock-cells = <1>;
  163. #reset-cells = <1>;
  164. };
  165. i2c0: i2c@e0170000 {
  166. compatible = "actions,s900-i2c";
  167. reg = <0 0xe0170000 0 0x1000>;
  168. clocks = <&cmu CLK_I2C0>;
  169. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  170. #address-cells = <1>;
  171. #size-cells = <0>;
  172. status = "disabled";
  173. };
  174. i2c1: i2c@e0172000 {
  175. compatible = "actions,s900-i2c";
  176. reg = <0 0xe0172000 0 0x1000>;
  177. clocks = <&cmu CLK_I2C1>;
  178. interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  179. #address-cells = <1>;
  180. #size-cells = <0>;
  181. status = "disabled";
  182. };
  183. i2c2: i2c@e0174000 {
  184. compatible = "actions,s900-i2c";
  185. reg = <0 0xe0174000 0 0x1000>;
  186. clocks = <&cmu CLK_I2C2>;
  187. interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
  188. #address-cells = <1>;
  189. #size-cells = <0>;
  190. status = "disabled";
  191. };
  192. i2c3: i2c@e0176000 {
  193. compatible = "actions,s900-i2c";
  194. reg = <0 0xe0176000 0 0x1000>;
  195. clocks = <&cmu CLK_I2C3>;
  196. interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  197. #address-cells = <1>;
  198. #size-cells = <0>;
  199. status = "disabled";
  200. };
  201. i2c4: i2c@e0178000 {
  202. compatible = "actions,s900-i2c";
  203. reg = <0 0xe0178000 0 0x1000>;
  204. clocks = <&cmu CLK_I2C4>;
  205. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  206. #address-cells = <1>;
  207. #size-cells = <0>;
  208. status = "disabled";
  209. };
  210. i2c5: i2c@e017a000 {
  211. compatible = "actions,s900-i2c";
  212. reg = <0 0xe017a000 0 0x1000>;
  213. clocks = <&cmu CLK_I2C5>;
  214. interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  215. #address-cells = <1>;
  216. #size-cells = <0>;
  217. status = "disabled";
  218. };
  219. pinctrl: pinctrl@e01b0000 {
  220. compatible = "actions,s900-pinctrl";
  221. reg = <0x0 0xe01b0000 0x0 0x1000>;
  222. clocks = <&cmu CLK_GPIO>;
  223. gpio-controller;
  224. gpio-ranges = <&pinctrl 0 0 146>;
  225. #gpio-cells = <2>;
  226. interrupt-controller;
  227. #interrupt-cells = <2>;
  228. interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
  229. <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
  230. <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
  231. <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
  232. <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
  233. <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  234. };
  235. timer: timer@e0228000 {
  236. compatible = "actions,s900-timer";
  237. reg = <0x0 0xe0228000 0x0 0x8000>;
  238. interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  239. interrupt-names = "timer1";
  240. };
  241. dma: dma-controller@e0260000 {
  242. compatible = "actions,s900-dma";
  243. reg = <0x0 0xe0260000 0x0 0x1000>;
  244. interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
  245. <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
  246. <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
  247. <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
  248. #dma-cells = <1>;
  249. dma-channels = <12>;
  250. dma-requests = <46>;
  251. clocks = <&cmu CLK_DMAC>;
  252. };
  253. mmc0: mmc@e0330000 {
  254. compatible = "actions,owl-mmc";
  255. reg = <0x0 0xe0330000 0x0 0x4000>;
  256. interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
  257. clocks = <&cmu CLK_SD0>;
  258. resets = <&cmu RESET_SD0>;
  259. dmas = <&dma 2>;
  260. dma-names = "mmc";
  261. status = "disabled";
  262. };
  263. mmc1: mmc@e0334000 {
  264. compatible = "actions,owl-mmc";
  265. reg = <0x0 0xe0334000 0x0 0x4000>;
  266. interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
  267. clocks = <&cmu CLK_SD1>;
  268. resets = <&cmu RESET_SD1>;
  269. dmas = <&dma 3>;
  270. dma-names = "mmc";
  271. status = "disabled";
  272. };
  273. mmc2: mmc@e0338000 {
  274. compatible = "actions,owl-mmc";
  275. reg = <0x0 0xe0338000 0x0 0x4000>;
  276. interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  277. clocks = <&cmu CLK_SD2>;
  278. resets = <&cmu RESET_SD2>;
  279. dmas = <&dma 4>;
  280. dma-names = "mmc";
  281. status = "disabled";
  282. };
  283. mmc3: mmc@e033c000 {
  284. compatible = "actions,owl-mmc";
  285. reg = <0x0 0xe033c000 0x0 0x4000>;
  286. interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
  287. clocks = <&cmu CLK_SD3>;
  288. resets = <&cmu RESET_SD3>;
  289. dmas = <&dma 46>;
  290. dma-names = "mmc";
  291. status = "disabled";
  292. };
  293. };
  294. };