s700.dtsi 5.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248
  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2017 Andreas Färber
  4. */
  5. #include <dt-bindings/clock/actions,s700-cmu.h>
  6. #include <dt-bindings/interrupt-controller/arm-gic.h>
  7. #include <dt-bindings/reset/actions,s700-reset.h>
  8. / {
  9. compatible = "actions,s700";
  10. interrupt-parent = <&gic>;
  11. #address-cells = <2>;
  12. #size-cells = <2>;
  13. cpus {
  14. #address-cells = <2>;
  15. #size-cells = <0>;
  16. cpu0: cpu@0 {
  17. device_type = "cpu";
  18. compatible = "arm,cortex-a53";
  19. reg = <0x0 0x0>;
  20. enable-method = "psci";
  21. };
  22. cpu1: cpu@1 {
  23. device_type = "cpu";
  24. compatible = "arm,cortex-a53";
  25. reg = <0x0 0x1>;
  26. enable-method = "psci";
  27. };
  28. cpu2: cpu@2 {
  29. device_type = "cpu";
  30. compatible = "arm,cortex-a53";
  31. reg = <0x0 0x2>;
  32. enable-method = "psci";
  33. };
  34. cpu3: cpu@3 {
  35. device_type = "cpu";
  36. compatible = "arm,cortex-a53";
  37. reg = <0x0 0x3>;
  38. enable-method = "psci";
  39. };
  40. };
  41. reserved-memory {
  42. #address-cells = <2>;
  43. #size-cells = <2>;
  44. ranges;
  45. secmon@1f000000 {
  46. reg = <0x0 0x1f000000 0x0 0x1000000>;
  47. no-map;
  48. };
  49. };
  50. psci {
  51. compatible = "arm,psci-0.2";
  52. method = "smc";
  53. };
  54. arm-pmu {
  55. compatible = "arm,cortex-a53-pmu";
  56. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  57. <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
  58. <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  59. <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  60. interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  61. };
  62. timer {
  63. compatible = "arm,armv8-timer";
  64. interrupts = <GIC_PPI 13
  65. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  66. <GIC_PPI 14
  67. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  68. <GIC_PPI 11
  69. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  70. <GIC_PPI 10
  71. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  72. };
  73. hosc: hosc {
  74. compatible = "fixed-clock";
  75. clock-frequency = <24000000>;
  76. #clock-cells = <0>;
  77. };
  78. losc: losc {
  79. compatible = "fixed-clock";
  80. clock-frequency = <32768>;
  81. #clock-cells = <0>;
  82. };
  83. soc {
  84. compatible = "simple-bus";
  85. #address-cells = <2>;
  86. #size-cells = <2>;
  87. ranges;
  88. gic: interrupt-controller@e00f1000 {
  89. compatible = "arm,gic-400";
  90. reg = <0x0 0xe00f1000 0x0 0x1000>,
  91. <0x0 0xe00f2000 0x0 0x2000>,
  92. <0x0 0xe00f4000 0x0 0x2000>,
  93. <0x0 0xe00f6000 0x0 0x2000>;
  94. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  95. interrupt-controller;
  96. #interrupt-cells = <3>;
  97. };
  98. uart0: serial@e0120000 {
  99. compatible = "actions,s900-uart", "actions,owl-uart";
  100. reg = <0x0 0xe0120000 0x0 0x2000>;
  101. clocks = <&cmu CLK_UART0>;
  102. interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  103. status = "disabled";
  104. };
  105. uart1: serial@e0122000 {
  106. compatible = "actions,s900-uart", "actions,owl-uart";
  107. reg = <0x0 0xe0122000 0x0 0x2000>;
  108. clocks = <&cmu CLK_UART1>;
  109. interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  110. status = "disabled";
  111. };
  112. uart2: serial@e0124000 {
  113. compatible = "actions,s900-uart", "actions,owl-uart";
  114. reg = <0x0 0xe0124000 0x0 0x2000>;
  115. clocks = <&cmu CLK_UART2>;
  116. interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  117. status = "disabled";
  118. };
  119. uart3: serial@e0126000 {
  120. compatible = "actions,s900-uart", "actions,owl-uart";
  121. reg = <0x0 0xe0126000 0x0 0x2000>;
  122. clocks = <&cmu CLK_UART3>;
  123. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  124. status = "disabled";
  125. };
  126. uart4: serial@e0128000 {
  127. compatible = "actions,s900-uart", "actions,owl-uart";
  128. reg = <0x0 0xe0128000 0x0 0x2000>;
  129. clocks = <&cmu CLK_UART4>;
  130. interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  131. status = "disabled";
  132. };
  133. uart5: serial@e012a000 {
  134. compatible = "actions,s900-uart", "actions,owl-uart";
  135. reg = <0x0 0xe012a000 0x0 0x2000>;
  136. clocks = <&cmu CLK_UART5>;
  137. interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  138. status = "disabled";
  139. };
  140. uart6: serial@e012c000 {
  141. compatible = "actions,s900-uart", "actions,owl-uart";
  142. reg = <0x0 0xe012c000 0x0 0x2000>;
  143. clocks = <&cmu CLK_UART6>;
  144. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  145. status = "disabled";
  146. };
  147. cmu: clock-controller@e0168000 {
  148. compatible = "actions,s700-cmu";
  149. reg = <0x0 0xe0168000 0x0 0x1000>;
  150. clocks = <&hosc>, <&losc>;
  151. #clock-cells = <1>;
  152. #reset-cells = <1>;
  153. };
  154. i2c0: i2c@e0170000 {
  155. compatible = "actions,s700-i2c";
  156. reg = <0 0xe0170000 0 0x1000>;
  157. clocks = <&cmu CLK_I2C0>;
  158. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  159. #address-cells = <1>;
  160. #size-cells = <0>;
  161. status = "disabled";
  162. };
  163. i2c1: i2c@e0174000 {
  164. compatible = "actions,s700-i2c";
  165. reg = <0 0xe0174000 0 0x1000>;
  166. clocks = <&cmu CLK_I2C1>;
  167. interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  168. #address-cells = <1>;
  169. #size-cells = <0>;
  170. status = "disabled";
  171. };
  172. i2c2: i2c@e0178000 {
  173. compatible = "actions,s700-i2c";
  174. reg = <0 0xe0178000 0 0x1000>;
  175. clocks = <&cmu CLK_I2C2>;
  176. interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
  177. #address-cells = <1>;
  178. #size-cells = <0>;
  179. status = "disabled";
  180. };
  181. i2c3: i2c@e017c000 {
  182. compatible = "actions,s700-i2c";
  183. reg = <0 0xe017c000 0 0x1000>;
  184. clocks = <&cmu CLK_I2C3>;
  185. interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  186. #address-cells = <1>;
  187. #size-cells = <0>;
  188. status = "disabled";
  189. };
  190. sps: power-controller@e01b0100 {
  191. compatible = "actions,s700-sps";
  192. reg = <0x0 0xe01b0100 0x0 0x100>;
  193. #power-domain-cells = <1>;
  194. };
  195. timer: timer@e024c000 {
  196. compatible = "actions,s700-timer";
  197. reg = <0x0 0xe024c000 0x0 0x4000>;
  198. interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  199. interrupt-names = "timer1";
  200. };
  201. pinctrl: pinctrl@e01b0000 {
  202. compatible = "actions,s700-pinctrl";
  203. reg = <0x0 0xe01b0000 0x0 0x1000>;
  204. clocks = <&cmu CLK_GPIO>;
  205. gpio-controller;
  206. gpio-ranges = <&pinctrl 0 0 136>;
  207. #gpio-cells = <2>;
  208. interrupt-controller;
  209. #interrupt-cells = <2>;
  210. interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
  211. <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
  212. <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
  213. <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
  214. <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
  215. };
  216. };
  217. };