mvtwsi.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Driver for the TWSI (i2c) controller found on the Marvell
  4. * orion5x and kirkwood SoC families.
  5. *
  6. * Author: Albert Aribaud <albert.u.boot@aribaud.net>
  7. * Copyright (c) 2010 Albert Aribaud.
  8. */
  9. #include <common.h>
  10. #include <i2c.h>
  11. #include <log.h>
  12. #include <linux/delay.h>
  13. #include <linux/errno.h>
  14. #include <asm/io.h>
  15. #include <linux/bitops.h>
  16. #include <linux/compat.h>
  17. #ifdef CONFIG_DM_I2C
  18. #include <dm.h>
  19. #endif
  20. DECLARE_GLOBAL_DATA_PTR;
  21. /*
  22. * Include a file that will provide CONFIG_I2C_MVTWSI_BASE*, and possibly other
  23. * settings
  24. */
  25. #ifndef CONFIG_DM_I2C
  26. #if defined(CONFIG_ARCH_ORION5X)
  27. #include <asm/arch/orion5x.h>
  28. #elif (defined(CONFIG_ARCH_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU))
  29. #include <asm/arch/soc.h>
  30. #elif defined(CONFIG_ARCH_SUNXI)
  31. #include <asm/arch/i2c.h>
  32. #else
  33. #error Driver mvtwsi not supported by SoC or board
  34. #endif
  35. #endif /* CONFIG_DM_I2C */
  36. /*
  37. * On SUNXI, we get CONFIG_SYS_TCLK from this include, so we want to
  38. * always have it.
  39. */
  40. #if defined(CONFIG_DM_I2C) && defined(CONFIG_ARCH_SUNXI)
  41. #include <asm/arch/i2c.h>
  42. #endif
  43. /*
  44. * TWSI register structure
  45. */
  46. #ifdef CONFIG_ARCH_SUNXI
  47. struct mvtwsi_registers {
  48. u32 slave_address;
  49. u32 xtnd_slave_addr;
  50. u32 data;
  51. u32 control;
  52. u32 status;
  53. u32 baudrate;
  54. u32 soft_reset;
  55. u32 debug; /* Dummy field for build compatibility with mvebu */
  56. };
  57. #else
  58. struct mvtwsi_registers {
  59. u32 slave_address;
  60. u32 data;
  61. u32 control;
  62. union {
  63. u32 status; /* When reading */
  64. u32 baudrate; /* When writing */
  65. };
  66. u32 xtnd_slave_addr;
  67. u32 reserved0[2];
  68. u32 soft_reset;
  69. u32 reserved1[27];
  70. u32 debug;
  71. };
  72. #endif
  73. #ifdef CONFIG_DM_I2C
  74. struct mvtwsi_i2c_dev {
  75. /* TWSI Register base for the device */
  76. struct mvtwsi_registers *base;
  77. /* Number of the device (determined from cell-index property) */
  78. int index;
  79. /* The I2C slave address for the device */
  80. u8 slaveadd;
  81. /* The configured I2C speed in Hz */
  82. uint speed;
  83. /* The current length of a clock period (depending on speed) */
  84. uint tick;
  85. };
  86. #endif /* CONFIG_DM_I2C */
  87. /*
  88. * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control
  89. * register
  90. */
  91. enum mvtwsi_ctrl_register_fields {
  92. /* Acknowledge bit */
  93. MVTWSI_CONTROL_ACK = 0x00000004,
  94. /* Interrupt flag */
  95. MVTWSI_CONTROL_IFLG = 0x00000008,
  96. /* Stop bit */
  97. MVTWSI_CONTROL_STOP = 0x00000010,
  98. /* Start bit */
  99. MVTWSI_CONTROL_START = 0x00000020,
  100. /* I2C enable */
  101. MVTWSI_CONTROL_TWSIEN = 0x00000040,
  102. /* Interrupt enable */
  103. MVTWSI_CONTROL_INTEN = 0x00000080,
  104. };
  105. /*
  106. * On sun6i and newer, IFLG is a write-clear bit, which is cleared by writing 1;
  107. * on other platforms, it is a normal r/w bit, which is cleared by writing 0.
  108. */
  109. #ifdef CONFIG_SUNXI_GEN_SUN6I
  110. #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008
  111. #else
  112. #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000
  113. #endif
  114. /*
  115. * enum mvstwsi_status_values - Possible values of I2C controller's status
  116. * register
  117. *
  118. * Only those statuses expected in normal master operation on
  119. * non-10-bit-address devices are specified.
  120. *
  121. * Every status that's unexpected during normal operation (bus errors,
  122. * arbitration losses, missing ACKs...) is passed back to the caller as an error
  123. * code.
  124. */
  125. enum mvstwsi_status_values {
  126. /* START condition transmitted */
  127. MVTWSI_STATUS_START = 0x08,
  128. /* Repeated START condition transmitted */
  129. MVTWSI_STATUS_REPEATED_START = 0x10,
  130. /* Address + write bit transmitted, ACK received */
  131. MVTWSI_STATUS_ADDR_W_ACK = 0x18,
  132. /* Data transmitted, ACK received */
  133. MVTWSI_STATUS_DATA_W_ACK = 0x28,
  134. /* Address + read bit transmitted, ACK received */
  135. MVTWSI_STATUS_ADDR_R_ACK = 0x40,
  136. /* Address + read bit transmitted, ACK not received */
  137. MVTWSI_STATUS_ADDR_R_NAK = 0x48,
  138. /* Data received, ACK transmitted */
  139. MVTWSI_STATUS_DATA_R_ACK = 0x50,
  140. /* Data received, ACK not transmitted */
  141. MVTWSI_STATUS_DATA_R_NAK = 0x58,
  142. /* No relevant status */
  143. MVTWSI_STATUS_IDLE = 0xF8,
  144. };
  145. /*
  146. * enum mvstwsi_ack_flags - Determine whether a read byte should be
  147. * acknowledged or not.
  148. */
  149. enum mvtwsi_ack_flags {
  150. /* Send NAK after received byte */
  151. MVTWSI_READ_NAK = 0,
  152. /* Send ACK after received byte */
  153. MVTWSI_READ_ACK = 1,
  154. };
  155. /*
  156. * calc_tick() - Calculate the duration of a clock cycle from the I2C speed
  157. *
  158. * @speed: The speed in Hz to calculate the clock cycle duration for.
  159. * @return The duration of a clock cycle in ns.
  160. */
  161. inline uint calc_tick(uint speed)
  162. {
  163. /* One tick = the duration of a period at the specified speed in ns (we
  164. * add 100 ns to be on the safe side) */
  165. return (1000000000u / speed) + 100;
  166. }
  167. #ifndef CONFIG_DM_I2C
  168. /*
  169. * twsi_get_base() - Get controller register base for specified adapter
  170. *
  171. * @adap: Adapter to get the register base for.
  172. * @return Register base for the specified adapter.
  173. */
  174. static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
  175. {
  176. switch (adap->hwadapnr) {
  177. #ifdef CONFIG_I2C_MVTWSI_BASE0
  178. case 0:
  179. return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0;
  180. #endif
  181. #ifdef CONFIG_I2C_MVTWSI_BASE1
  182. case 1:
  183. return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1;
  184. #endif
  185. #ifdef CONFIG_I2C_MVTWSI_BASE2
  186. case 2:
  187. return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE2;
  188. #endif
  189. #ifdef CONFIG_I2C_MVTWSI_BASE3
  190. case 3:
  191. return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE3;
  192. #endif
  193. #ifdef CONFIG_I2C_MVTWSI_BASE4
  194. case 4:
  195. return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE4;
  196. #endif
  197. #ifdef CONFIG_I2C_MVTWSI_BASE5
  198. case 5:
  199. return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE5;
  200. #endif
  201. default:
  202. printf("Missing mvtwsi controller %d base\n", adap->hwadapnr);
  203. break;
  204. }
  205. return NULL;
  206. }
  207. #endif
  208. /*
  209. * enum mvtwsi_error_class - types of I2C errors
  210. */
  211. enum mvtwsi_error_class {
  212. /* The controller returned a different status than expected */
  213. MVTWSI_ERROR_WRONG_STATUS = 0x01,
  214. /* The controller timed out */
  215. MVTWSI_ERROR_TIMEOUT = 0x02,
  216. };
  217. /*
  218. * mvtwsi_error() - Build I2C return code from error information
  219. *
  220. * For debugging purposes, this function packs some information of an occurred
  221. * error into a return code. These error codes are returned from I2C API
  222. * functions (i2c_{read,write}, dm_i2c_{read,write}, etc.).
  223. *
  224. * @ec: The error class of the error (enum mvtwsi_error_class).
  225. * @lc: The last value of the control register.
  226. * @ls: The last value of the status register.
  227. * @es: The expected value of the status register.
  228. * @return The generated error code.
  229. */
  230. inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es)
  231. {
  232. return ((ec << 24) & 0xFF000000)
  233. | ((lc << 16) & 0x00FF0000)
  234. | ((ls << 8) & 0x0000FF00)
  235. | (es & 0xFF);
  236. }
  237. /*
  238. * twsi_wait() - Wait for I2C bus interrupt flag and check status, or time out.
  239. *
  240. * @return Zero if status is as expected, or a non-zero code if either a time
  241. * out occurred, or the status was not the expected one.
  242. */
  243. static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status,
  244. uint tick)
  245. {
  246. int control, status;
  247. int timeout = 1000;
  248. do {
  249. control = readl(&twsi->control);
  250. if (control & MVTWSI_CONTROL_IFLG) {
  251. /*
  252. * On Armada 38x it seems that the controller works as
  253. * if it first set the MVTWSI_CONTROL_IFLAG in the
  254. * control register and only after that it changed the
  255. * status register.
  256. * This sometimes caused weird bugs which only appeared
  257. * on selected I2C speeds and even then only sometimes.
  258. * We therefore add here a simple ndealy(100), which
  259. * seems to fix this weird bug.
  260. */
  261. ndelay(100);
  262. status = readl(&twsi->status);
  263. if (status == expected_status)
  264. return 0;
  265. else
  266. return mvtwsi_error(
  267. MVTWSI_ERROR_WRONG_STATUS,
  268. control, status, expected_status);
  269. }
  270. ndelay(tick); /* One clock cycle */
  271. } while (timeout--);
  272. status = readl(&twsi->status);
  273. return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status,
  274. expected_status);
  275. }
  276. /*
  277. * twsi_start() - Assert a START condition on the bus.
  278. *
  279. * This function is used in both single I2C transactions and inside
  280. * back-to-back transactions (repeated starts).
  281. *
  282. * @twsi: The MVTWSI register structure to use.
  283. * @expected_status: The I2C bus status expected to be asserted after the
  284. * operation completion.
  285. * @tick: The duration of a clock cycle at the current I2C speed.
  286. * @return Zero if status is as expected, or a non-zero code if either a time
  287. * out occurred or the status was not the expected one.
  288. */
  289. static int twsi_start(struct mvtwsi_registers *twsi, int expected_status,
  290. uint tick)
  291. {
  292. /* Assert START */
  293. writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_START |
  294. MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
  295. /* Wait for controller to process START */
  296. return twsi_wait(twsi, expected_status, tick);
  297. }
  298. /*
  299. * twsi_send() - Send a byte on the I2C bus.
  300. *
  301. * The byte may be part of an address byte or data.
  302. *
  303. * @twsi: The MVTWSI register structure to use.
  304. * @byte: The byte to send.
  305. * @expected_status: The I2C bus status expected to be asserted after the
  306. * operation completion.
  307. * @tick: The duration of a clock cycle at the current I2C speed.
  308. * @return Zero if status is as expected, or a non-zero code if either a time
  309. * out occurred or the status was not the expected one.
  310. */
  311. static int twsi_send(struct mvtwsi_registers *twsi, u8 byte,
  312. int expected_status, uint tick)
  313. {
  314. /* Write byte to data register for sending */
  315. writel(byte, &twsi->data);
  316. /* Clear any pending interrupt -- that will cause sending */
  317. writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_CLEAR_IFLG,
  318. &twsi->control);
  319. /* Wait for controller to receive byte, and check ACK */
  320. return twsi_wait(twsi, expected_status, tick);
  321. }
  322. /*
  323. * twsi_recv() - Receive a byte on the I2C bus.
  324. *
  325. * The static variable mvtwsi_control_flags controls whether we ack or nak.
  326. *
  327. * @twsi: The MVTWSI register structure to use.
  328. * @byte: The byte to send.
  329. * @ack_flag: Flag that determines whether the received byte should
  330. * be acknowledged by the controller or not (sent ACK/NAK).
  331. * @tick: The duration of a clock cycle at the current I2C speed.
  332. * @return Zero if status is as expected, or a non-zero code if either a time
  333. * out occurred or the status was not the expected one.
  334. */
  335. static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag,
  336. uint tick)
  337. {
  338. int expected_status, status, control;
  339. /* Compute expected status based on passed ACK flag */
  340. expected_status = ack_flag ? MVTWSI_STATUS_DATA_R_ACK :
  341. MVTWSI_STATUS_DATA_R_NAK;
  342. /* Acknowledge *previous state*, and launch receive */
  343. control = MVTWSI_CONTROL_TWSIEN;
  344. control |= ack_flag == MVTWSI_READ_ACK ? MVTWSI_CONTROL_ACK : 0;
  345. writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
  346. /* Wait for controller to receive byte, and assert ACK or NAK */
  347. status = twsi_wait(twsi, expected_status, tick);
  348. /* If we did receive the expected byte, store it */
  349. if (status == 0)
  350. *byte = readl(&twsi->data);
  351. return status;
  352. }
  353. /*
  354. * twsi_stop() - Assert a STOP condition on the bus.
  355. *
  356. * This function is also used to force the bus back to idle state (SDA =
  357. * SCL = 1).
  358. *
  359. * @twsi: The MVTWSI register structure to use.
  360. * @tick: The duration of a clock cycle at the current I2C speed.
  361. * @return Zero if the operation succeeded, or a non-zero code if a time out
  362. * occurred.
  363. */
  364. static int twsi_stop(struct mvtwsi_registers *twsi, uint tick)
  365. {
  366. int control, stop_status;
  367. int status = 0;
  368. int timeout = 1000;
  369. /* Assert STOP */
  370. control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP;
  371. writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
  372. /* Wait for IDLE; IFLG won't rise, so we can't use twsi_wait() */
  373. do {
  374. stop_status = readl(&twsi->status);
  375. if (stop_status == MVTWSI_STATUS_IDLE)
  376. break;
  377. ndelay(tick); /* One clock cycle */
  378. } while (timeout--);
  379. control = readl(&twsi->control);
  380. if (stop_status != MVTWSI_STATUS_IDLE)
  381. status = mvtwsi_error(MVTWSI_ERROR_TIMEOUT,
  382. control, status, MVTWSI_STATUS_IDLE);
  383. return status;
  384. }
  385. /*
  386. * twsi_calc_freq() - Compute I2C frequency depending on m and n parameters.
  387. *
  388. * @n: Parameter 'n' for the frequency calculation algorithm.
  389. * @m: Parameter 'm' for the frequency calculation algorithm.
  390. * @return The I2C frequency corresponding to the passed m and n parameters.
  391. */
  392. static uint twsi_calc_freq(const int n, const int m)
  393. {
  394. #ifdef CONFIG_ARCH_SUNXI
  395. return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
  396. #else
  397. return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
  398. #endif
  399. }
  400. /*
  401. * twsi_reset() - Reset the I2C controller.
  402. *
  403. * Resetting the controller also resets the baud rate and slave address, hence
  404. * they must be re-established after the reset.
  405. *
  406. * @twsi: The MVTWSI register structure to use.
  407. */
  408. static void twsi_reset(struct mvtwsi_registers *twsi)
  409. {
  410. /* Reset controller */
  411. writel(0, &twsi->soft_reset);
  412. /* Wait 2 ms -- this is what the Marvell LSP does */
  413. udelay(20000);
  414. }
  415. /*
  416. * __twsi_i2c_set_bus_speed() - Set the speed of the I2C controller.
  417. *
  418. * This function sets baud rate to the highest possible value that does not
  419. * exceed the requested rate.
  420. *
  421. * @twsi: The MVTWSI register structure to use.
  422. * @requested_speed: The desired frequency the controller should run at
  423. * in Hz.
  424. * @return The actual frequency the controller was configured to.
  425. */
  426. static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi,
  427. uint requested_speed)
  428. {
  429. uint tmp_speed, highest_speed, n, m;
  430. uint baud = 0x44; /* Baud rate after controller reset */
  431. highest_speed = 0;
  432. /* Successively try m, n combinations, and use the combination
  433. * resulting in the largest speed that's not above the requested
  434. * speed */
  435. for (n = 0; n < 8; n++) {
  436. for (m = 0; m < 16; m++) {
  437. tmp_speed = twsi_calc_freq(n, m);
  438. if ((tmp_speed <= requested_speed) &&
  439. (tmp_speed > highest_speed)) {
  440. highest_speed = tmp_speed;
  441. baud = (m << 3) | n;
  442. }
  443. }
  444. }
  445. writel(baud, &twsi->baudrate);
  446. /* Wait for controller for one tick */
  447. #ifdef CONFIG_DM_I2C
  448. ndelay(calc_tick(highest_speed));
  449. #else
  450. ndelay(10000);
  451. #endif
  452. return highest_speed;
  453. }
  454. /*
  455. * __twsi_i2c_init() - Initialize the I2C controller.
  456. *
  457. * @twsi: The MVTWSI register structure to use.
  458. * @speed: The initial frequency the controller should run at
  459. * in Hz.
  460. * @slaveadd: The I2C address to be set for the I2C master.
  461. * @actual_speed: A output parameter that receives the actual frequency
  462. * in Hz the controller was set to by the function.
  463. * @return Zero if the operation succeeded, or a non-zero code if a time out
  464. * occurred.
  465. */
  466. static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed,
  467. int slaveadd, uint *actual_speed)
  468. {
  469. uint tmp_speed;
  470. /* Reset controller */
  471. twsi_reset(twsi);
  472. /* Set speed */
  473. tmp_speed = __twsi_i2c_set_bus_speed(twsi, speed);
  474. if (actual_speed)
  475. *actual_speed = tmp_speed;
  476. /* Set slave address; even though we don't use it */
  477. writel(slaveadd, &twsi->slave_address);
  478. writel(0, &twsi->xtnd_slave_addr);
  479. /* Assert STOP, but don't care for the result */
  480. #ifdef CONFIG_DM_I2C
  481. (void) twsi_stop(twsi, calc_tick(*actual_speed));
  482. #else
  483. (void) twsi_stop(twsi, 10000);
  484. #endif
  485. }
  486. /*
  487. * i2c_begin() - Start a I2C transaction.
  488. *
  489. * Begin a I2C transaction with a given expected start status and chip address.
  490. * A START is asserted, and the address byte is sent to the I2C controller. The
  491. * expected address status will be derived from the direction bit (bit 0) of
  492. * the address byte.
  493. *
  494. * @twsi: The MVTWSI register structure to use.
  495. * @expected_start_status: The I2C status the controller is expected to
  496. * assert after the address byte was sent.
  497. * @addr: The address byte to be sent.
  498. * @tick: The duration of a clock cycle at the current
  499. * I2C speed.
  500. * @return Zero if the operation succeeded, or a non-zero code if a time out or
  501. * unexpected I2C status occurred.
  502. */
  503. static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status,
  504. u8 addr, uint tick)
  505. {
  506. int status, expected_addr_status;
  507. /* Compute the expected address status from the direction bit in
  508. * the address byte */
  509. if (addr & 1) /* Reading */
  510. expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK;
  511. else /* Writing */
  512. expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
  513. /* Assert START */
  514. status = twsi_start(twsi, expected_start_status, tick);
  515. /* Send out the address if the start went well */
  516. if (status == 0)
  517. status = twsi_send(twsi, addr, expected_addr_status, tick);
  518. /* Return 0, or the status of the first failure */
  519. return status;
  520. }
  521. /*
  522. * __twsi_i2c_probe_chip() - Probe the given I2C chip address.
  523. *
  524. * This function begins a I2C read transaction, does a dummy read and NAKs; if
  525. * the procedure succeeds, the chip is considered to be present.
  526. *
  527. * @twsi: The MVTWSI register structure to use.
  528. * @chip: The chip address to probe.
  529. * @tick: The duration of a clock cycle at the current I2C speed.
  530. * @return Zero if the operation succeeded, or a non-zero code if a time out or
  531. * unexpected I2C status occurred.
  532. */
  533. static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip,
  534. uint tick)
  535. {
  536. u8 dummy_byte;
  537. int status;
  538. /* Begin i2c read */
  539. status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1) | 1, tick);
  540. /* Dummy read was accepted: receive byte, but NAK it. */
  541. if (status == 0)
  542. status = twsi_recv(twsi, &dummy_byte, MVTWSI_READ_NAK, tick);
  543. /* Stop transaction */
  544. twsi_stop(twsi, tick);
  545. /* Return 0, or the status of the first failure */
  546. return status;
  547. }
  548. /*
  549. * __twsi_i2c_read() - Read data from a I2C chip.
  550. *
  551. * This function begins a I2C write transaction, and transmits the address
  552. * bytes; then begins a I2C read transaction, and receives the data bytes.
  553. *
  554. * NOTE: Some devices want a stop right before the second start, while some
  555. * will choke if it is there. Since deciding this is not yet supported in
  556. * higher level APIs, we need to make a decision here, and for the moment that
  557. * will be a repeated start without a preceding stop.
  558. *
  559. * @twsi: The MVTWSI register structure to use.
  560. * @chip: The chip address to read from.
  561. * @addr: The address bytes to send.
  562. * @alen: The length of the address bytes in bytes.
  563. * @data: The buffer to receive the data read from the chip (has to have
  564. * a size of at least 'length' bytes).
  565. * @length: The amount of data to be read from the chip in bytes.
  566. * @tick: The duration of a clock cycle at the current I2C speed.
  567. * @return Zero if the operation succeeded, or a non-zero code if a time out or
  568. * unexpected I2C status occurred.
  569. */
  570. static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
  571. u8 *addr, int alen, uchar *data, int length,
  572. uint tick)
  573. {
  574. int status = 0;
  575. int stop_status;
  576. int expected_start = MVTWSI_STATUS_START;
  577. if (alen > 0) {
  578. /* Begin i2c write to send the address bytes */
  579. status = i2c_begin(twsi, expected_start, (chip << 1), tick);
  580. /* Send address bytes */
  581. while ((status == 0) && alen--)
  582. status = twsi_send(twsi, addr[alen],
  583. MVTWSI_STATUS_DATA_W_ACK, tick);
  584. /* Send repeated STARTs after the initial START */
  585. expected_start = MVTWSI_STATUS_REPEATED_START;
  586. }
  587. /* Begin i2c read to receive data bytes */
  588. if (status == 0)
  589. status = i2c_begin(twsi, expected_start, (chip << 1) | 1, tick);
  590. /* Receive actual data bytes; set NAK if we if we have nothing more to
  591. * read */
  592. while ((status == 0) && length--)
  593. status = twsi_recv(twsi, data++,
  594. length > 0 ?
  595. MVTWSI_READ_ACK : MVTWSI_READ_NAK, tick);
  596. /* Stop transaction */
  597. stop_status = twsi_stop(twsi, tick);
  598. /* Return 0, or the status of the first failure */
  599. return status != 0 ? status : stop_status;
  600. }
  601. /*
  602. * __twsi_i2c_write() - Send data to a I2C chip.
  603. *
  604. * This function begins a I2C write transaction, and transmits the address
  605. * bytes; then begins a new I2C write transaction, and sends the data bytes.
  606. *
  607. * @twsi: The MVTWSI register structure to use.
  608. * @chip: The chip address to read from.
  609. * @addr: The address bytes to send.
  610. * @alen: The length of the address bytes in bytes.
  611. * @data: The buffer containing the data to be sent to the chip.
  612. * @length: The length of data to be sent to the chip in bytes.
  613. * @tick: The duration of a clock cycle at the current I2C speed.
  614. * @return Zero if the operation succeeded, or a non-zero code if a time out or
  615. * unexpected I2C status occurred.
  616. */
  617. static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip,
  618. u8 *addr, int alen, uchar *data, int length,
  619. uint tick)
  620. {
  621. int status, stop_status;
  622. /* Begin i2c write to send first the address bytes, then the
  623. * data bytes */
  624. status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1), tick);
  625. /* Send address bytes */
  626. while ((status == 0) && (alen-- > 0))
  627. status = twsi_send(twsi, addr[alen], MVTWSI_STATUS_DATA_W_ACK,
  628. tick);
  629. /* Send data bytes */
  630. while ((status == 0) && (length-- > 0))
  631. status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK,
  632. tick);
  633. /* Stop transaction */
  634. stop_status = twsi_stop(twsi, tick);
  635. /* Return 0, or the status of the first failure */
  636. return status != 0 ? status : stop_status;
  637. }
  638. #ifndef CONFIG_DM_I2C
  639. static void twsi_i2c_init(struct i2c_adapter *adap, int speed,
  640. int slaveadd)
  641. {
  642. struct mvtwsi_registers *twsi = twsi_get_base(adap);
  643. __twsi_i2c_init(twsi, speed, slaveadd, NULL);
  644. }
  645. static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
  646. uint requested_speed)
  647. {
  648. struct mvtwsi_registers *twsi = twsi_get_base(adap);
  649. __twsi_i2c_set_bus_speed(twsi, requested_speed);
  650. return 0;
  651. }
  652. static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
  653. {
  654. struct mvtwsi_registers *twsi = twsi_get_base(adap);
  655. return __twsi_i2c_probe_chip(twsi, chip, 10000);
  656. }
  657. static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
  658. int alen, uchar *data, int length)
  659. {
  660. struct mvtwsi_registers *twsi = twsi_get_base(adap);
  661. u8 addr_bytes[4];
  662. addr_bytes[0] = (addr >> 0) & 0xFF;
  663. addr_bytes[1] = (addr >> 8) & 0xFF;
  664. addr_bytes[2] = (addr >> 16) & 0xFF;
  665. addr_bytes[3] = (addr >> 24) & 0xFF;
  666. return __twsi_i2c_read(twsi, chip, addr_bytes, alen, data, length,
  667. 10000);
  668. }
  669. static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
  670. int alen, uchar *data, int length)
  671. {
  672. struct mvtwsi_registers *twsi = twsi_get_base(adap);
  673. u8 addr_bytes[4];
  674. addr_bytes[0] = (addr >> 0) & 0xFF;
  675. addr_bytes[1] = (addr >> 8) & 0xFF;
  676. addr_bytes[2] = (addr >> 16) & 0xFF;
  677. addr_bytes[3] = (addr >> 24) & 0xFF;
  678. return __twsi_i2c_write(twsi, chip, addr_bytes, alen, data, length,
  679. 10000);
  680. }
  681. #ifdef CONFIG_I2C_MVTWSI_BASE0
  682. U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe,
  683. twsi_i2c_read, twsi_i2c_write,
  684. twsi_i2c_set_bus_speed,
  685. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
  686. #endif
  687. #ifdef CONFIG_I2C_MVTWSI_BASE1
  688. U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe,
  689. twsi_i2c_read, twsi_i2c_write,
  690. twsi_i2c_set_bus_speed,
  691. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1)
  692. #endif
  693. #ifdef CONFIG_I2C_MVTWSI_BASE2
  694. U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe,
  695. twsi_i2c_read, twsi_i2c_write,
  696. twsi_i2c_set_bus_speed,
  697. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2)
  698. #endif
  699. #ifdef CONFIG_I2C_MVTWSI_BASE3
  700. U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe,
  701. twsi_i2c_read, twsi_i2c_write,
  702. twsi_i2c_set_bus_speed,
  703. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3)
  704. #endif
  705. #ifdef CONFIG_I2C_MVTWSI_BASE4
  706. U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe,
  707. twsi_i2c_read, twsi_i2c_write,
  708. twsi_i2c_set_bus_speed,
  709. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4)
  710. #endif
  711. #ifdef CONFIG_I2C_MVTWSI_BASE5
  712. U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe,
  713. twsi_i2c_read, twsi_i2c_write,
  714. twsi_i2c_set_bus_speed,
  715. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5)
  716. #endif
  717. #else /* CONFIG_DM_I2C */
  718. static int mvtwsi_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
  719. u32 chip_flags)
  720. {
  721. struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
  722. return __twsi_i2c_probe_chip(dev->base, chip_addr, dev->tick);
  723. }
  724. static int mvtwsi_i2c_set_bus_speed(struct udevice *bus, uint speed)
  725. {
  726. struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
  727. dev->speed = __twsi_i2c_set_bus_speed(dev->base, speed);
  728. dev->tick = calc_tick(dev->speed);
  729. return 0;
  730. }
  731. static int mvtwsi_i2c_of_to_plat(struct udevice *bus)
  732. {
  733. struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
  734. dev->base = dev_read_addr_ptr(bus);
  735. if (!dev->base)
  736. return -ENOMEM;
  737. dev->index = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
  738. "cell-index", -1);
  739. dev->slaveadd = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
  740. "u-boot,i2c-slave-addr", 0x0);
  741. dev->speed = dev_read_u32_default(bus, "clock-frequency",
  742. I2C_SPEED_STANDARD_RATE);
  743. return 0;
  744. }
  745. static void twsi_disable_i2c_slave(struct mvtwsi_registers *twsi)
  746. {
  747. clrbits_le32(&twsi->debug, BIT(18));
  748. }
  749. static int mvtwsi_i2c_bind(struct udevice *bus)
  750. {
  751. struct mvtwsi_registers *twsi = dev_read_addr_ptr(bus);
  752. /* Disable the hidden slave in i2c0 of these platforms */
  753. if ((IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARCH_KIRKWOOD)
  754. || IS_ENABLED(CONFIG_ARMADA_8K))
  755. && bus->req_seq == 0)
  756. twsi_disable_i2c_slave(twsi);
  757. return 0;
  758. }
  759. static int mvtwsi_i2c_probe(struct udevice *bus)
  760. {
  761. struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
  762. uint actual_speed;
  763. __twsi_i2c_init(dev->base, dev->speed, dev->slaveadd, &actual_speed);
  764. dev->speed = actual_speed;
  765. dev->tick = calc_tick(dev->speed);
  766. return 0;
  767. }
  768. static int mvtwsi_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  769. {
  770. struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
  771. struct i2c_msg *dmsg, *omsg, dummy;
  772. memset(&dummy, 0, sizeof(struct i2c_msg));
  773. /* We expect either two messages (one with an offset and one with the
  774. * actual data) or one message (just data or offset/data combined) */
  775. if (nmsgs > 2 || nmsgs == 0) {
  776. debug("%s: Only one or two messages are supported.", __func__);
  777. return -1;
  778. }
  779. omsg = nmsgs == 1 ? &dummy : msg;
  780. dmsg = nmsgs == 1 ? msg : msg + 1;
  781. if (dmsg->flags & I2C_M_RD)
  782. return __twsi_i2c_read(dev->base, dmsg->addr, omsg->buf,
  783. omsg->len, dmsg->buf, dmsg->len,
  784. dev->tick);
  785. else
  786. return __twsi_i2c_write(dev->base, dmsg->addr, omsg->buf,
  787. omsg->len, dmsg->buf, dmsg->len,
  788. dev->tick);
  789. }
  790. static const struct dm_i2c_ops mvtwsi_i2c_ops = {
  791. .xfer = mvtwsi_i2c_xfer,
  792. .probe_chip = mvtwsi_i2c_probe_chip,
  793. .set_bus_speed = mvtwsi_i2c_set_bus_speed,
  794. };
  795. static const struct udevice_id mvtwsi_i2c_ids[] = {
  796. { .compatible = "marvell,mv64xxx-i2c", },
  797. { .compatible = "marvell,mv78230-i2c", },
  798. { .compatible = "allwinner,sun6i-a31-i2c", },
  799. { /* sentinel */ }
  800. };
  801. U_BOOT_DRIVER(i2c_mvtwsi) = {
  802. .name = "i2c_mvtwsi",
  803. .id = UCLASS_I2C,
  804. .of_match = mvtwsi_i2c_ids,
  805. .bind = mvtwsi_i2c_bind,
  806. .probe = mvtwsi_i2c_probe,
  807. .of_to_plat = mvtwsi_i2c_of_to_plat,
  808. .priv_auto = sizeof(struct mvtwsi_i2c_dev),
  809. .ops = &mvtwsi_i2c_ops,
  810. };
  811. #endif /* CONFIG_DM_I2C */