sdram_gen5.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright Altera Corporation (C) 2014-2015
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <errno.h>
  8. #include <div64.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <ram.h>
  12. #include <reset.h>
  13. #include <watchdog.h>
  14. #include <asm/arch/fpga_manager.h>
  15. #include <asm/arch/reset_manager.h>
  16. #include <asm/arch/sdram.h>
  17. #include <asm/arch/system_manager.h>
  18. #include <asm/bitops.h>
  19. #include <asm/io.h>
  20. #include <dm/device_compat.h>
  21. #include "sequencer.h"
  22. #ifdef CONFIG_SPL_BUILD
  23. struct altera_gen5_sdram_priv {
  24. struct ram_info info;
  25. };
  26. struct altera_gen5_sdram_platdata {
  27. struct socfpga_sdr *sdr;
  28. };
  29. struct sdram_prot_rule {
  30. u32 sdram_start; /* SDRAM start address */
  31. u32 sdram_end; /* SDRAM end address */
  32. u32 rule; /* SDRAM protection rule number: 0-19 */
  33. int valid; /* Rule valid or not? 1 - valid, 0 not*/
  34. u32 security;
  35. u32 portmask;
  36. u32 result;
  37. u32 lo_prot_id;
  38. u32 hi_prot_id;
  39. };
  40. static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl);
  41. /**
  42. * get_errata_rows() - Up the number of DRAM rows to cover entire address space
  43. * @cfg: SDRAM controller configuration data
  44. *
  45. * SDRAM Failure happens when accessing non-existent memory. Artificially
  46. * increase the number of rows so that the memory controller thinks it has
  47. * 4GB of RAM. This function returns such amount of rows.
  48. */
  49. static int get_errata_rows(const struct socfpga_sdram_config *cfg)
  50. {
  51. /* Define constant for 4G memory - used for SDRAM errata workaround */
  52. #define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
  53. const unsigned long long memsize = MEMSIZE_4G;
  54. const unsigned int cs =
  55. ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
  56. SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
  57. const unsigned int rows =
  58. (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
  59. SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
  60. const unsigned int banks =
  61. (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
  62. SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
  63. const unsigned int cols =
  64. (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
  65. SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
  66. const unsigned int width = 8;
  67. unsigned long long newrows;
  68. int bits, inewrowslog2;
  69. debug("workaround rows - memsize %lld\n", memsize);
  70. debug("workaround rows - cs %d\n", cs);
  71. debug("workaround rows - width %d\n", width);
  72. debug("workaround rows - rows %d\n", rows);
  73. debug("workaround rows - banks %d\n", banks);
  74. debug("workaround rows - cols %d\n", cols);
  75. newrows = lldiv(memsize, cs * (width / 8));
  76. debug("rows workaround - term1 %lld\n", newrows);
  77. newrows = lldiv(newrows, (1 << banks) * (1 << cols));
  78. debug("rows workaround - term2 %lld\n", newrows);
  79. /*
  80. * Compute the hamming weight - same as number of bits set.
  81. * Need to see if result is ordinal power of 2 before
  82. * attempting log2 of result.
  83. */
  84. bits = generic_hweight32(newrows);
  85. debug("rows workaround - bits %d\n", bits);
  86. if (bits != 1) {
  87. printf("SDRAM workaround failed, bits set %d\n", bits);
  88. return rows;
  89. }
  90. if (newrows > UINT_MAX) {
  91. printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
  92. return rows;
  93. }
  94. inewrowslog2 = __ilog2(newrows);
  95. debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
  96. if (inewrowslog2 == -1) {
  97. printf("SDRAM workaround failed, newrows %lld\n", newrows);
  98. return rows;
  99. }
  100. return inewrowslog2;
  101. }
  102. /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
  103. static void sdram_set_rule(struct socfpga_sdr_ctrl *sdr_ctrl,
  104. struct sdram_prot_rule *prule)
  105. {
  106. u32 lo_addr_bits;
  107. u32 hi_addr_bits;
  108. int ruleno = prule->rule;
  109. /* Select the rule */
  110. writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
  111. /* Obtain the address bits */
  112. lo_addr_bits = prule->sdram_start >> 20ULL;
  113. hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
  114. debug("sdram set rule start %x, %d\n", lo_addr_bits,
  115. prule->sdram_start);
  116. debug("sdram set rule end %x, %d\n", hi_addr_bits,
  117. prule->sdram_end);
  118. /* Set rule addresses */
  119. writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
  120. /* Set rule protection ids */
  121. writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
  122. &sdr_ctrl->prot_rule_id);
  123. /* Set the rule data */
  124. writel(prule->security | (prule->valid << 2) |
  125. (prule->portmask << 3) | (prule->result << 13),
  126. &sdr_ctrl->prot_rule_data);
  127. /* write the rule */
  128. writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr);
  129. /* Set rule number to 0 by default */
  130. writel(0, &sdr_ctrl->prot_rule_rdwr);
  131. }
  132. static void sdram_get_rule(struct socfpga_sdr_ctrl *sdr_ctrl,
  133. struct sdram_prot_rule *prule)
  134. {
  135. u32 addr;
  136. u32 id;
  137. u32 data;
  138. int ruleno = prule->rule;
  139. /* Read the rule */
  140. writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
  141. writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr);
  142. /* Get the addresses */
  143. addr = readl(&sdr_ctrl->prot_rule_addr);
  144. prule->sdram_start = (addr & 0xFFF) << 20;
  145. prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
  146. /* Get the configured protection IDs */
  147. id = readl(&sdr_ctrl->prot_rule_id);
  148. prule->lo_prot_id = id & 0xFFF;
  149. prule->hi_prot_id = (id >> 12) & 0xFFF;
  150. /* Get protection data */
  151. data = readl(&sdr_ctrl->prot_rule_data);
  152. prule->security = data & 0x3;
  153. prule->valid = (data >> 2) & 0x1;
  154. prule->portmask = (data >> 3) & 0x3FF;
  155. prule->result = (data >> 13) & 0x1;
  156. }
  157. static void
  158. sdram_set_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl,
  159. const u32 sdram_start, const u32 sdram_end)
  160. {
  161. struct sdram_prot_rule rule;
  162. int rules;
  163. /* Start with accepting all SDRAM transaction */
  164. writel(0x0, &sdr_ctrl->protport_default);
  165. /* Clear all protection rules for warm boot case */
  166. memset(&rule, 0, sizeof(rule));
  167. for (rules = 0; rules < 20; rules++) {
  168. rule.rule = rules;
  169. sdram_set_rule(sdr_ctrl, &rule);
  170. }
  171. /* new rule: accept SDRAM */
  172. rule.sdram_start = sdram_start;
  173. rule.sdram_end = sdram_end;
  174. rule.lo_prot_id = 0x0;
  175. rule.hi_prot_id = 0xFFF;
  176. rule.portmask = 0x3FF;
  177. rule.security = 0x3;
  178. rule.result = 0;
  179. rule.valid = 1;
  180. rule.rule = 0;
  181. /* set new rule */
  182. sdram_set_rule(sdr_ctrl, &rule);
  183. /* default rule: reject everything */
  184. writel(0x3ff, &sdr_ctrl->protport_default);
  185. }
  186. static void sdram_dump_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl)
  187. {
  188. struct sdram_prot_rule rule;
  189. int rules;
  190. debug("SDRAM Prot rule, default %x\n",
  191. readl(&sdr_ctrl->protport_default));
  192. for (rules = 0; rules < 20; rules++) {
  193. rule.rule = rules;
  194. sdram_get_rule(sdr_ctrl, &rule);
  195. debug("Rule %d, rules ...\n", rules);
  196. debug(" sdram start %x\n", rule.sdram_start);
  197. debug(" sdram end %x\n", rule.sdram_end);
  198. debug(" low prot id %d, hi prot id %d\n",
  199. rule.lo_prot_id,
  200. rule.hi_prot_id);
  201. debug(" portmask %x\n", rule.portmask);
  202. debug(" security %d\n", rule.security);
  203. debug(" result %d\n", rule.result);
  204. debug(" valid %d\n", rule.valid);
  205. }
  206. }
  207. /**
  208. * sdram_write_verify() - write to register and verify the write.
  209. * @addr: Register address
  210. * @val: Value to be written and verified
  211. *
  212. * This function writes to a register, reads back the value and compares
  213. * the result with the written value to check if the data match.
  214. */
  215. static unsigned sdram_write_verify(const u32 *addr, const u32 val)
  216. {
  217. u32 rval;
  218. debug(" Write - Address 0x%p Data 0x%08x\n", addr, val);
  219. writel(val, addr);
  220. debug(" Read and verify...");
  221. rval = readl(addr);
  222. if (rval != val) {
  223. debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n",
  224. addr, val, rval);
  225. return -EINVAL;
  226. }
  227. debug("correct!\n");
  228. return 0;
  229. }
  230. /**
  231. * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register
  232. * @cfg: SDRAM controller configuration data
  233. *
  234. * Return the value of DRAM CTRLCFG register.
  235. */
  236. static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
  237. {
  238. const u32 csbits =
  239. ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
  240. SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
  241. u32 addrorder =
  242. (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
  243. SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
  244. u32 ctrl_cfg = cfg->ctrl_cfg;
  245. /*
  246. * SDRAM Failure When Accessing Non-Existent Memory
  247. * Set the addrorder field of the SDRAM control register
  248. * based on the CSBITs setting.
  249. */
  250. if (csbits == 1) {
  251. if (addrorder != 0)
  252. debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
  253. addrorder = 0;
  254. } else if (csbits == 2) {
  255. if (addrorder != 2)
  256. debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
  257. addrorder = 2;
  258. }
  259. ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
  260. ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
  261. return ctrl_cfg;
  262. }
  263. /**
  264. * sdr_get_addr_rw() - Get the value of DRAM ADDRW register
  265. * @cfg: SDRAM controller configuration data
  266. *
  267. * Return the value of DRAM ADDRW register.
  268. */
  269. static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
  270. {
  271. /*
  272. * SDRAM Failure When Accessing Non-Existent Memory
  273. * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
  274. * log2(number of chip select bits). Since there's only
  275. * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
  276. * which is the same as "chip selects" - 1.
  277. */
  278. const int rows = get_errata_rows(cfg);
  279. u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
  280. return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
  281. }
  282. /**
  283. * sdr_load_regs() - Load SDRAM controller registers
  284. * @cfg: SDRAM controller configuration data
  285. *
  286. * This function loads the register values into the SDRAM controller block.
  287. */
  288. static void sdr_load_regs(struct socfpga_sdr_ctrl *sdr_ctrl,
  289. const struct socfpga_sdram_config *cfg)
  290. {
  291. const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
  292. const u32 dram_addrw = sdr_get_addr_rw(cfg);
  293. debug("\nConfiguring CTRLCFG\n");
  294. writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
  295. debug("Configuring DRAMTIMING1\n");
  296. writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
  297. debug("Configuring DRAMTIMING2\n");
  298. writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
  299. debug("Configuring DRAMTIMING3\n");
  300. writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
  301. debug("Configuring DRAMTIMING4\n");
  302. writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
  303. debug("Configuring LOWPWRTIMING\n");
  304. writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
  305. debug("Configuring DRAMADDRW\n");
  306. writel(dram_addrw, &sdr_ctrl->dram_addrw);
  307. debug("Configuring DRAMIFWIDTH\n");
  308. writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
  309. debug("Configuring DRAMDEVWIDTH\n");
  310. writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
  311. debug("Configuring LOWPWREQ\n");
  312. writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
  313. debug("Configuring DRAMINTR\n");
  314. writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
  315. debug("Configuring STATICCFG\n");
  316. writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
  317. debug("Configuring CTRLWIDTH\n");
  318. writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
  319. debug("Configuring PORTCFG\n");
  320. writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
  321. debug("Configuring FIFOCFG\n");
  322. writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
  323. debug("Configuring MPPRIORITY\n");
  324. writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
  325. debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
  326. writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
  327. writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
  328. writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
  329. writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
  330. debug("Configuring MPPACING_MPPACING_0\n");
  331. writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
  332. writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
  333. writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
  334. writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
  335. debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
  336. writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
  337. writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
  338. writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
  339. debug("Configuring PHYCTRL_PHYCTRL_0\n");
  340. writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
  341. debug("Configuring CPORTWIDTH\n");
  342. writel(cfg->cport_width, &sdr_ctrl->cport_width);
  343. debug("Configuring CPORTWMAP\n");
  344. writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
  345. debug("Configuring CPORTRMAP\n");
  346. writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
  347. debug("Configuring RFIFOCMAP\n");
  348. writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
  349. debug("Configuring WFIFOCMAP\n");
  350. writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
  351. debug("Configuring CPORTRDWR\n");
  352. writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
  353. debug("Configuring DRAMODT\n");
  354. writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
  355. if (dram_is_ddr(3)) {
  356. debug("Configuring EXTRATIME1\n");
  357. writel(cfg->extratime1, &sdr_ctrl->extratime1);
  358. }
  359. }
  360. /**
  361. * sdram_mmr_init_full() - Function to initialize SDRAM MMR
  362. * @sdr_phy_reg: Value of the PHY control register 0
  363. *
  364. * Initialize the SDRAM MMR.
  365. */
  366. int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
  367. unsigned int sdr_phy_reg)
  368. {
  369. const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
  370. const unsigned int rows =
  371. (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
  372. SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
  373. int ret;
  374. writel(rows,
  375. socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
  376. sdr_load_regs(sdr_ctrl, cfg);
  377. /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
  378. writel(cfg->fpgaport_rst,
  379. socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(3));
  380. /* only enable if the FPGA is programmed */
  381. if (fpgamgr_test_fpga_ready()) {
  382. ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst,
  383. cfg->fpgaport_rst);
  384. if (ret)
  385. return ret;
  386. }
  387. /* Restore the SDR PHY Register if valid */
  388. if (sdr_phy_reg != 0xffffffff)
  389. writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
  390. /* Final step - apply configuration changes */
  391. debug("Configuring STATICCFG\n");
  392. clrsetbits_le32(&sdr_ctrl->static_cfg,
  393. SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
  394. 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
  395. sdram_set_protection_config(sdr_ctrl, 0,
  396. sdram_calculate_size(sdr_ctrl) - 1);
  397. sdram_dump_protection_config(sdr_ctrl);
  398. return 0;
  399. }
  400. /**
  401. * sdram_calculate_size() - Calculate SDRAM size
  402. *
  403. * Calculate SDRAM device size based on SDRAM controller parameters.
  404. * Size is specified in bytes.
  405. */
  406. static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl)
  407. {
  408. unsigned long temp;
  409. unsigned long row, bank, col, cs, width;
  410. const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
  411. const unsigned int csbits =
  412. ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
  413. SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
  414. const unsigned int rowbits =
  415. (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
  416. SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
  417. temp = readl(&sdr_ctrl->dram_addrw);
  418. col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
  419. SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
  420. /*
  421. * SDRAM Failure When Accessing Non-Existent Memory
  422. * Use ROWBITS from Quartus/QSys to calculate SDRAM size
  423. * since the FB specifies we modify ROWBITs to work around SDRAM
  424. * controller issue.
  425. */
  426. row = readl(socfpga_get_sysmgr_addr() +
  427. SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
  428. if (row == 0)
  429. row = rowbits;
  430. /*
  431. * If the stored handoff value for rows is greater than
  432. * the field width in the sdr.dramaddrw register then
  433. * something is very wrong. Revert to using the the #define
  434. * value handed off by the SOCEDS tool chain instead of
  435. * using a broken value.
  436. */
  437. if (row > 31)
  438. row = rowbits;
  439. bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
  440. SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
  441. /*
  442. * SDRAM Failure When Accessing Non-Existent Memory
  443. * Use CSBITs from Quartus/QSys to calculate SDRAM size
  444. * since the FB specifies we modify CSBITs to work around SDRAM
  445. * controller issue.
  446. */
  447. cs = csbits;
  448. width = readl(&sdr_ctrl->dram_if_width);
  449. /* ECC would not be calculated as its not addressible */
  450. if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
  451. width = 32;
  452. if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
  453. width = 16;
  454. /* calculate the SDRAM size base on this info */
  455. temp = 1 << (row + bank + col);
  456. temp = temp * cs * (width / 8);
  457. debug("%s returns %ld\n", __func__, temp);
  458. return temp;
  459. }
  460. static int altera_gen5_sdram_of_to_plat(struct udevice *dev)
  461. {
  462. struct altera_gen5_sdram_platdata *plat = dev->plat;
  463. plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0);
  464. if (!plat->sdr)
  465. return -ENODEV;
  466. return 0;
  467. }
  468. static int altera_gen5_sdram_probe(struct udevice *dev)
  469. {
  470. int ret;
  471. unsigned long sdram_size;
  472. struct altera_gen5_sdram_platdata *plat = dev->plat;
  473. struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
  474. struct socfpga_sdr_ctrl *sdr_ctrl = &plat->sdr->sdr_ctrl;
  475. struct reset_ctl_bulk resets;
  476. ret = reset_get_bulk(dev, &resets);
  477. if (ret) {
  478. dev_err(dev, "Can't get reset: %d\n", ret);
  479. return -ENODEV;
  480. }
  481. reset_deassert_bulk(&resets);
  482. if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff) != 0) {
  483. puts("SDRAM init failed.\n");
  484. goto failed;
  485. }
  486. debug("SDRAM: Calibrating PHY\n");
  487. /* SDRAM calibration */
  488. if (sdram_calibration_full(plat->sdr) == 0) {
  489. puts("SDRAM calibration failed.\n");
  490. goto failed;
  491. }
  492. sdram_size = sdram_calculate_size(sdr_ctrl);
  493. debug("SDRAM: %ld MiB\n", sdram_size >> 20);
  494. /* Sanity check ensure correct SDRAM size specified */
  495. if (get_ram_size(0, sdram_size) != sdram_size) {
  496. puts("SDRAM size check failed!\n");
  497. goto failed;
  498. }
  499. priv->info.base = 0;
  500. priv->info.size = sdram_size;
  501. return 0;
  502. failed:
  503. reset_release_bulk(&resets);
  504. return -ENODEV;
  505. }
  506. static int altera_gen5_sdram_get_info(struct udevice *dev,
  507. struct ram_info *info)
  508. {
  509. struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
  510. info->base = priv->info.base;
  511. info->size = priv->info.size;
  512. return 0;
  513. }
  514. static const struct ram_ops altera_gen5_sdram_ops = {
  515. .get_info = altera_gen5_sdram_get_info,
  516. };
  517. static const struct udevice_id altera_gen5_sdram_ids[] = {
  518. { .compatible = "altr,sdr-ctl" },
  519. { /* sentinel */ }
  520. };
  521. U_BOOT_DRIVER(altera_gen5_sdram) = {
  522. .name = "altr_sdr_ctl",
  523. .id = UCLASS_RAM,
  524. .of_match = altera_gen5_sdram_ids,
  525. .ops = &altera_gen5_sdram_ops,
  526. .of_to_plat = altera_gen5_sdram_of_to_plat,
  527. .plat_auto = sizeof(struct altera_gen5_sdram_platdata),
  528. .probe = altera_gen5_sdram_probe,
  529. .priv_auto = sizeof(struct altera_gen5_sdram_priv),
  530. };
  531. #endif /* CONFIG_SPL_BUILD */