clk_rk3036.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2015 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <clk-uclass.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <syscon.h>
  12. #include <asm/io.h>
  13. #include <asm/arch-rockchip/clock.h>
  14. #include <asm/arch-rockchip/cru_rk3036.h>
  15. #include <asm/arch-rockchip/hardware.h>
  16. #include <dm/lists.h>
  17. #include <dt-bindings/clock/rk3036-cru.h>
  18. #include <linux/delay.h>
  19. #include <linux/log2.h>
  20. #include <linux/stringify.h>
  21. enum {
  22. VCO_MAX_HZ = 2400U * 1000000,
  23. VCO_MIN_HZ = 600 * 1000000,
  24. OUTPUT_MAX_HZ = 2400U * 1000000,
  25. OUTPUT_MIN_HZ = 24 * 1000000,
  26. };
  27. #define RATE_TO_DIV(input_rate, output_rate) \
  28. ((input_rate) / (output_rate) - 1);
  29. #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
  30. #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  31. .refdiv = _refdiv,\
  32. .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  33. .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
  34. _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
  35. OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
  36. #hz "Hz cannot be hit with PLL "\
  37. "divisors on line " __stringify(__LINE__));
  38. /* use integer mode*/
  39. static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
  40. static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
  41. static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
  42. const struct pll_div *div)
  43. {
  44. int pll_id = rk_pll_id(clk_id);
  45. struct rk3036_pll *pll = &cru->pll[pll_id];
  46. /* All PLLs have same VCO and output frequency range restrictions. */
  47. uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
  48. uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
  49. debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\
  50. vco=%u Hz, output=%u Hz\n",
  51. pll, div->fbdiv, div->refdiv, div->postdiv1,
  52. div->postdiv2, vco_hz, output_hz);
  53. assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
  54. output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
  55. /* use integer mode */
  56. rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
  57. rk_clrsetreg(&pll->con0,
  58. PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
  59. (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
  60. rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
  61. (div->postdiv2 << PLL_POSTDIV2_SHIFT |
  62. div->refdiv << PLL_REFDIV_SHIFT));
  63. /* waiting for pll lock */
  64. while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
  65. udelay(1);
  66. return 0;
  67. }
  68. static void rkclk_init(struct rk3036_cru *cru)
  69. {
  70. u32 aclk_div;
  71. u32 hclk_div;
  72. u32 pclk_div;
  73. /* pll enter slow-mode */
  74. rk_clrsetreg(&cru->cru_mode_con,
  75. GPLL_MODE_MASK | APLL_MODE_MASK,
  76. GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
  77. APLL_MODE_SLOW << APLL_MODE_SHIFT);
  78. /* init pll */
  79. rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
  80. rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
  81. /*
  82. * select apll as cpu/core clock pll source and
  83. * set up dependent divisors for PERI and ACLK clocks.
  84. * core hz : apll = 1:1
  85. */
  86. aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
  87. assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
  88. pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
  89. assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
  90. rk_clrsetreg(&cru->cru_clksel_con[0],
  91. CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
  92. CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
  93. 0 << CORE_DIV_CON_SHIFT);
  94. rk_clrsetreg(&cru->cru_clksel_con[1],
  95. CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
  96. aclk_div << CORE_ACLK_DIV_SHIFT |
  97. pclk_div << CORE_PERI_DIV_SHIFT);
  98. /*
  99. * select apll as pd_bus bus clock source and
  100. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  101. */
  102. aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
  103. assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
  104. pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1;
  105. assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
  106. hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1;
  107. assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
  108. rk_clrsetreg(&cru->cru_clksel_con[0],
  109. BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
  110. BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
  111. aclk_div << BUS_ACLK_DIV_SHIFT);
  112. rk_clrsetreg(&cru->cru_clksel_con[1],
  113. BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
  114. pclk_div << BUS_PCLK_DIV_SHIFT |
  115. hclk_div << BUS_HCLK_DIV_SHIFT);
  116. /*
  117. * select gpll as pd_peri bus clock source and
  118. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  119. */
  120. aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
  121. assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
  122. hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
  123. assert((1 << hclk_div) * PERI_HCLK_HZ ==
  124. PERI_ACLK_HZ && (hclk_div < 0x4));
  125. pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
  126. assert((1 << pclk_div) * PERI_PCLK_HZ ==
  127. PERI_ACLK_HZ && pclk_div < 0x8);
  128. rk_clrsetreg(&cru->cru_clksel_con[10],
  129. PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
  130. PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
  131. PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
  132. pclk_div << PERI_PCLK_DIV_SHIFT |
  133. hclk_div << PERI_HCLK_DIV_SHIFT |
  134. aclk_div << PERI_ACLK_DIV_SHIFT);
  135. /* PLL enter normal-mode */
  136. rk_clrsetreg(&cru->cru_mode_con,
  137. GPLL_MODE_MASK | APLL_MODE_MASK,
  138. GPLL_MODE_NORM << GPLL_MODE_SHIFT |
  139. APLL_MODE_NORM << APLL_MODE_SHIFT);
  140. }
  141. /* Get pll rate by id */
  142. static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru,
  143. enum rk_clk_id clk_id)
  144. {
  145. uint32_t refdiv, fbdiv, postdiv1, postdiv2;
  146. uint32_t con;
  147. int pll_id = rk_pll_id(clk_id);
  148. struct rk3036_pll *pll = &cru->pll[pll_id];
  149. static u8 clk_shift[CLK_COUNT] = {
  150. 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
  151. GPLL_MODE_SHIFT, 0xff
  152. };
  153. static u32 clk_mask[CLK_COUNT] = {
  154. 0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff,
  155. GPLL_MODE_MASK, 0xffffffff
  156. };
  157. uint shift;
  158. uint mask;
  159. con = readl(&cru->cru_mode_con);
  160. shift = clk_shift[clk_id];
  161. mask = clk_mask[clk_id];
  162. switch ((con & mask) >> shift) {
  163. case GPLL_MODE_SLOW:
  164. return OSC_HZ;
  165. case GPLL_MODE_NORM:
  166. /* normal mode */
  167. con = readl(&pll->con0);
  168. postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
  169. fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
  170. con = readl(&pll->con1);
  171. postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
  172. refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
  173. return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
  174. case GPLL_MODE_DEEP:
  175. default:
  176. return 32768;
  177. }
  178. }
  179. static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate,
  180. int periph)
  181. {
  182. uint src_rate;
  183. uint div, mux;
  184. u32 con;
  185. switch (periph) {
  186. case HCLK_EMMC:
  187. case SCLK_EMMC:
  188. con = readl(&cru->cru_clksel_con[12]);
  189. mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
  190. div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
  191. break;
  192. case HCLK_SDIO:
  193. case SCLK_SDIO:
  194. con = readl(&cru->cru_clksel_con[12]);
  195. mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
  196. div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
  197. break;
  198. default:
  199. return -EINVAL;
  200. }
  201. src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
  202. return DIV_TO_RATE(src_rate, div) / 2;
  203. }
  204. static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
  205. int periph, uint freq)
  206. {
  207. int src_clk_div;
  208. int mux;
  209. debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
  210. /* mmc clock auto divide 2 in internal */
  211. src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
  212. if (src_clk_div > 128) {
  213. src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
  214. assert(src_clk_div - 1 < 128);
  215. mux = EMMC_SEL_24M;
  216. } else {
  217. mux = EMMC_SEL_GPLL;
  218. }
  219. switch (periph) {
  220. case HCLK_EMMC:
  221. case SCLK_EMMC:
  222. rk_clrsetreg(&cru->cru_clksel_con[12],
  223. EMMC_PLL_MASK | EMMC_DIV_MASK,
  224. mux << EMMC_PLL_SHIFT |
  225. (src_clk_div - 1) << EMMC_DIV_SHIFT);
  226. break;
  227. case HCLK_SDIO:
  228. case SCLK_SDIO:
  229. rk_clrsetreg(&cru->cru_clksel_con[11],
  230. MMC0_PLL_MASK | MMC0_DIV_MASK,
  231. mux << MMC0_PLL_SHIFT |
  232. (src_clk_div - 1) << MMC0_DIV_SHIFT);
  233. break;
  234. default:
  235. return -EINVAL;
  236. }
  237. return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
  238. }
  239. static ulong rk3036_clk_get_rate(struct clk *clk)
  240. {
  241. struct rk3036_clk_priv *priv = dev_get_priv(clk->dev);
  242. switch (clk->id) {
  243. case 0 ... 63:
  244. return rkclk_pll_get_rate(priv->cru, clk->id);
  245. default:
  246. return -ENOENT;
  247. }
  248. }
  249. static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate)
  250. {
  251. struct rk3036_clk_priv *priv = dev_get_priv(clk->dev);
  252. ulong new_rate, gclk_rate;
  253. gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
  254. switch (clk->id) {
  255. case 0 ... 63:
  256. return 0;
  257. case HCLK_EMMC:
  258. case SCLK_EMMC:
  259. new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
  260. clk->id, rate);
  261. break;
  262. default:
  263. return -ENOENT;
  264. }
  265. return new_rate;
  266. }
  267. static struct clk_ops rk3036_clk_ops = {
  268. .get_rate = rk3036_clk_get_rate,
  269. .set_rate = rk3036_clk_set_rate,
  270. };
  271. static int rk3036_clk_of_to_plat(struct udevice *dev)
  272. {
  273. struct rk3036_clk_priv *priv = dev_get_priv(dev);
  274. priv->cru = dev_read_addr_ptr(dev);
  275. return 0;
  276. }
  277. static int rk3036_clk_probe(struct udevice *dev)
  278. {
  279. struct rk3036_clk_priv *priv = dev_get_priv(dev);
  280. rkclk_init(priv->cru);
  281. return 0;
  282. }
  283. static int rk3036_clk_bind(struct udevice *dev)
  284. {
  285. int ret;
  286. struct udevice *sys_child;
  287. struct sysreset_reg *priv;
  288. /* The reset driver does not have a device node, so bind it here */
  289. ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
  290. &sys_child);
  291. if (ret) {
  292. debug("Warning: No sysreset driver: ret=%d\n", ret);
  293. } else {
  294. priv = malloc(sizeof(struct sysreset_reg));
  295. priv->glb_srst_fst_value = offsetof(struct rk3036_cru,
  296. cru_glb_srst_fst_value);
  297. priv->glb_srst_snd_value = offsetof(struct rk3036_cru,
  298. cru_glb_srst_snd_value);
  299. sys_child->priv = priv;
  300. }
  301. #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
  302. ret = offsetof(struct rk3036_cru, cru_softrst_con[0]);
  303. ret = rockchip_reset_bind(dev, ret, 9);
  304. if (ret)
  305. debug("Warning: software reset driver bind faile\n");
  306. #endif
  307. return 0;
  308. }
  309. static const struct udevice_id rk3036_clk_ids[] = {
  310. { .compatible = "rockchip,rk3036-cru" },
  311. { }
  312. };
  313. U_BOOT_DRIVER(rockchip_rk3036_cru) = {
  314. .name = "clk_rk3036",
  315. .id = UCLASS_CLK,
  316. .of_match = rk3036_clk_ids,
  317. .priv_auto = sizeof(struct rk3036_clk_priv),
  318. .of_to_plat = rk3036_clk_of_to_plat,
  319. .ops = &rk3036_clk_ops,
  320. .bind = rk3036_clk_bind,
  321. .probe = rk3036_clk_probe,
  322. };