mtk_ahci.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * MTK SATA platform driver
  4. *
  5. * Copyright (C) 2020 MediaTek Inc.
  6. *
  7. * Author: Ryder Lee <ryder.lee@mediatek.com>
  8. * Author: Frank Wunderlich <frank-w@public-files.de>
  9. */
  10. #include <common.h>
  11. #include <ahci.h>
  12. #include <asm/io.h>
  13. #include <dm.h>
  14. #include <dm/of_access.h>
  15. #include <generic-phy.h>
  16. #include <linux/err.h>
  17. #include <regmap.h>
  18. #include <reset.h>
  19. #include <sata.h>
  20. #include <scsi.h>
  21. #include <syscon.h>
  22. #define SYS_CFG 0x14
  23. #define SYS_CFG_SATA_MSK GENMASK(31, 30)
  24. #define SYS_CFG_SATA_EN BIT(31)
  25. struct mtk_ahci_priv {
  26. void *base;
  27. struct ahci_uc_priv ahci_priv;
  28. struct regmap *mode;
  29. struct reset_ctl_bulk rst_bulk;
  30. };
  31. static int mtk_ahci_bind(struct udevice *dev)
  32. {
  33. struct udevice *scsi_dev;
  34. return ahci_bind_scsi(dev, &scsi_dev);
  35. }
  36. static int mtk_ahci_of_to_plat(struct udevice *dev)
  37. {
  38. struct mtk_ahci_priv *priv = dev_get_priv(dev);
  39. priv->base = devfdt_remap_addr_index(dev, 0);
  40. return 0;
  41. }
  42. static int mtk_ahci_parse_property(struct ahci_uc_priv *hpriv,
  43. struct udevice *dev)
  44. {
  45. struct mtk_ahci_priv *plat = dev_get_priv(dev);
  46. const void *fdt = gd->fdt_blob;
  47. /* enable SATA function if needed */
  48. if (fdt_get_property(fdt, dev_of_offset(dev),
  49. "mediatek,phy-mode", NULL)) {
  50. plat->mode = syscon_regmap_lookup_by_phandle(dev,
  51. "mediatek,phy-mode");
  52. if (IS_ERR(plat->mode)) {
  53. dev_err(dev, "missing phy-mode phandle\n");
  54. return PTR_ERR(plat->mode);
  55. }
  56. regmap_update_bits(plat->mode, SYS_CFG,
  57. SYS_CFG_SATA_MSK, SYS_CFG_SATA_EN);
  58. }
  59. ofnode_read_u32(dev->node, "ports-implemented", &hpriv->port_map);
  60. return 0;
  61. }
  62. static int mtk_ahci_probe(struct udevice *dev)
  63. {
  64. struct mtk_ahci_priv *priv = dev_get_priv(dev);
  65. int ret;
  66. struct phy phy;
  67. ret = mtk_ahci_parse_property(&priv->ahci_priv, dev);
  68. if (ret)
  69. return ret;
  70. ret = reset_get_bulk(dev, &priv->rst_bulk);
  71. if (!ret) {
  72. reset_assert_bulk(&priv->rst_bulk);
  73. reset_deassert_bulk(&priv->rst_bulk);
  74. } else {
  75. dev_err(dev, "Failed to get reset: %d\n", ret);
  76. }
  77. ret = generic_phy_get_by_name(dev, "sata-phy", &phy);
  78. if (ret) {
  79. pr_err("can't get the phy from DT\n");
  80. return ret;
  81. }
  82. ret = generic_phy_init(&phy);
  83. if (ret) {
  84. pr_err("unable to initialize the sata phy\n");
  85. return ret;
  86. }
  87. ret = generic_phy_power_on(&phy);
  88. if (ret) {
  89. pr_err("unable to power on the sata phy\n");
  90. return ret;
  91. }
  92. return ahci_probe_scsi(dev, (ulong)priv->base);
  93. }
  94. static const struct udevice_id mtk_ahci_ids[] = {
  95. { .compatible = "mediatek,mtk-ahci" },
  96. { }
  97. };
  98. U_BOOT_DRIVER(mtk_ahci) = {
  99. .name = "mtk_ahci",
  100. .id = UCLASS_AHCI,
  101. .of_match = mtk_ahci_ids,
  102. .bind = mtk_ahci_bind,
  103. .of_to_plat = mtk_ahci_of_to_plat,
  104. .ops = &scsi_ops,
  105. .probe = mtk_ahci_probe,
  106. .priv_auto = sizeof(struct mtk_ahci_priv),
  107. };