adsp.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Support for Intel Application Digital Signal Processor
  4. *
  5. * Copyright 2019 Google LLC
  6. *
  7. * Modified from coreboot file of the same name
  8. */
  9. #define LOG_CATEGORY UCLASS_SYSCON
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <log.h>
  13. #include <pci.h>
  14. #include <asm/io.h>
  15. #include <asm/cpu.h>
  16. #include <asm/intel_regs.h>
  17. #include <asm/arch/adsp.h>
  18. #include <asm/arch/pch.h>
  19. #include <asm/arch/rcb.h>
  20. enum pci_type_t {
  21. LYNX_POINT,
  22. WILDCAT_POINT,
  23. };
  24. struct broadwell_adsp_priv {
  25. bool adsp_d3_pg_enable;
  26. bool adsp_sram_pg_enable;
  27. bool sio_acpi_mode;
  28. };
  29. static int broadwell_adsp_probe(struct udevice *dev)
  30. {
  31. struct broadwell_adsp_priv *priv = dev_get_priv(dev);
  32. enum pci_type_t type;
  33. u32 bar0, bar1;
  34. u32 tmp32;
  35. /* Find BAR0 and BAR1 */
  36. bar0 = dm_pci_read_bar32(dev, 0);
  37. if (!bar0)
  38. return -EINVAL;
  39. bar1 = dm_pci_read_bar32(dev, 1);
  40. if (!bar1)
  41. return -EINVAL;
  42. /*
  43. * Set LTR value in DSP shim LTR control register to 3ms
  44. * SNOOP_REQ[13]=1b SNOOP_SCALE[12:10]=100b (1ms) SNOOP_VAL[9:0]=3h
  45. */
  46. type = dev_get_driver_data(dev);
  47. tmp32 = type == WILDCAT_POINT ? ADSP_SHIM_BASE_WPT : ADSP_SHIM_BASE_LPT;
  48. writel(ADSP_SHIM_LTRC_VALUE, bar0 + tmp32);
  49. /* Program VDRTCTL2 D19:F0:A8[31:0] = 0x00000fff */
  50. dm_pci_write_config32(dev, ADSP_PCI_VDRTCTL2, ADSP_VDRTCTL2_VALUE);
  51. /* Program ADSP IOBP VDLDAT1 to 0x040100 */
  52. pch_iobp_write(ADSP_IOBP_VDLDAT1, ADSP_VDLDAT1_VALUE);
  53. /* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */
  54. dm_pci_read_config32(dev, ADSP_PCI_VDRTCTL0, &tmp32);
  55. if (type == WILDCAT_POINT) {
  56. if (priv->adsp_d3_pg_enable) {
  57. tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
  58. if (priv->adsp_sram_pg_enable)
  59. tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
  60. else
  61. tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT;
  62. } else {
  63. tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT;
  64. }
  65. } else {
  66. if (priv->adsp_d3_pg_enable) {
  67. tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT;
  68. if (priv->adsp_sram_pg_enable)
  69. tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
  70. else
  71. tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT;
  72. } else {
  73. tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT;
  74. }
  75. }
  76. dm_pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32);
  77. /* Set PSF Snoop to SA, RCBA+0x3350[10]=1b */
  78. setbits_le32(RCB_REG(0x3350), 1 << 10);
  79. /* Set DSP IOBP PMCTL 0x1e0=0x3f */
  80. pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE);
  81. if (priv->sio_acpi_mode) {
  82. /* Configure for ACPI mode */
  83. log_info("ADSP: Enable ACPI Mode IRQ3\n");
  84. /* Set interrupt de-assert/assert opcode override to IRQ3 */
  85. pch_iobp_write(ADSP_IOBP_VDLDAT2, ADSP_IOBP_ACPI_IRQ3);
  86. /* Enable IRQ3 in RCBA */
  87. setbits_le32(RCB_REG(ACPIIRQEN), ADSP_ACPI_IRQEN);
  88. /* Set ACPI Interrupt Enable Bit */
  89. pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~ADSP_PCICFGCTL_SPCBAD,
  90. ADSP_PCICFGCTL_ACPIIE);
  91. /* Put ADSP in D3hot */
  92. clrbits_le32(bar1 + PCH_PCS, PCH_PCS_PS_D3HOT);
  93. } else {
  94. log_info("ADSP: Enable PCI Mode IRQ23\n");
  95. /* Configure for PCI mode */
  96. dm_pci_write_config32(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ);
  97. /* Clear ACPI Interrupt Enable Bit */
  98. pch_iobp_update(ADSP_IOBP_PCICFGCTL,
  99. ~(ADSP_PCICFGCTL_SPCBAD |
  100. ADSP_PCICFGCTL_ACPIIE), 0);
  101. }
  102. return 0;
  103. }
  104. static int broadwell_adsp_of_to_plat(struct udevice *dev)
  105. {
  106. struct broadwell_adsp_priv *priv = dev_get_priv(dev);
  107. priv->adsp_d3_pg_enable = dev_read_bool(dev, "intel,adsp-d3-pg-enable");
  108. priv->adsp_sram_pg_enable = dev_read_bool(dev,
  109. "intel,adsp-sram-pg-enable");
  110. priv->sio_acpi_mode = dev_read_bool(dev, "intel,sio-acpi-mode");
  111. return 0;
  112. }
  113. static const struct udevice_id broadwell_adsp_ids[] = {
  114. { .compatible = "intel,wildcatpoint-adsp", .data = WILDCAT_POINT },
  115. { }
  116. };
  117. U_BOOT_DRIVER(broadwell_adsp_drv) = {
  118. .name = "adsp",
  119. .id = UCLASS_SYSCON,
  120. .of_to_plat = broadwell_adsp_of_to_plat,
  121. .of_match = broadwell_adsp_ids,
  122. .bind = dm_scan_fdt_dev,
  123. .probe = broadwell_adsp_probe,
  124. };
  125. static struct pci_device_id broadwell_adsp_supported[] = {
  126. { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
  127. PCI_DEVICE_ID_INTEL_WILDCATPOINT_ADSP) },
  128. { },
  129. };
  130. U_BOOT_PCI_DEVICE(broadwell_adsp_drv, broadwell_adsp_supported);