s5p4418-nanopi2.dts 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2020 Stefan Bosch <stefan_b@posteo.net>
  4. *
  5. * (C) Copyright 2017 FriendlyElec Computer Tech. Co., Ltd.
  6. * (http://www.friendlyarm.com)
  7. *
  8. * (C) Copyright 2016 Nexell
  9. * Youngbok, Park <park@nexell.co.kr>
  10. */
  11. /dts-v1/;
  12. #include "s5p4418.dtsi"
  13. / {
  14. model = "FriendlyElec boards based on Nexell s5p4418";
  15. cpu-model = "S5p4418";
  16. compatible = "friendlyelec,nanopi2",
  17. "nexell,s5p4418";
  18. aliases {
  19. mmc0 = "/mmc@c0069000";
  20. mmc1 = "/mmc@c0062000";
  21. i2c0 = "/i2c@c00a4000";
  22. i2c1 = "/i2c@c00a5000";
  23. i2c2 = "/i2c@c00a6000";
  24. };
  25. mmc0:mmc@c0062000 {
  26. frequency = <50000000>;
  27. drive_dly = <0x0>;
  28. drive_shift = <0x03>;
  29. sample_dly = <0x00>;
  30. sample_shift = <0x02>;
  31. mmcboost = <0>;
  32. status = "okay";
  33. };
  34. mmc2:mmc@c0069000 {
  35. frequency = <50000000>;
  36. drive_dly = <0x0>;
  37. drive_shift = <0x03>;
  38. sample_dly = <0x00>;
  39. sample_shift = <0x02>;
  40. mmcboost = <0>;
  41. status = "okay";
  42. };
  43. /* NanoPi2: Header "CON2", NanoPC-T2: EEPROM (MAC-Addr.) and Audio */
  44. i2c0:i2c@c00a4000 {
  45. status ="okay";
  46. };
  47. /* NanoPi2: Header "CON2" and HDMI, NanoPC-T2: HDMI */
  48. i2c1:i2c@c00a5000 {
  49. status ="okay";
  50. };
  51. /* NanoPi2: LCD interface, NanoPC-T2: LCD, LVDS and MIPI interfaces */
  52. i2c2:i2c@c00a6000 {
  53. status ="okay";
  54. };
  55. dp0:dp@c0102800 {
  56. status = "okay";
  57. module = <0>;
  58. lcd-type = "lvds";
  59. dp-device {
  60. format = <0>; /* 0:VESA, 1:JEIDA */
  61. };
  62. dp-sync {
  63. h_active_len = <1024>;
  64. h_front_porch = <84>;
  65. h_back_porch = <84>;
  66. h_sync_width = <88>;
  67. h_sync_invert = <0>;
  68. v_active_len = <600>;
  69. v_front_porch = <10>;
  70. v_back_porch = <10>;
  71. v_sync_width = <20>;
  72. v_sync_invert = <0>;
  73. };
  74. dp-ctrl {
  75. clk_src_lv0 = <3>;
  76. clk_div_lv0 = <16>;
  77. clk_src_lv1 = <7>;
  78. clk_div_lv1 = <1>;
  79. out_format = <2>;
  80. };
  81. dp-planes {
  82. layer_top {
  83. screen_width = <1024>;
  84. screen_height = <600>;
  85. back_color = <0x0>;
  86. };
  87. layer_1 { /* RGB 1 */
  88. width = <1024>;
  89. height = <600>;
  90. format = <0x06530000>;
  91. pixel_byte = <4>;
  92. };
  93. };
  94. };
  95. };