st_smi.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2009
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. */
  6. #ifndef ST_SMI_H
  7. #define ST_SMI_H
  8. /* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */
  9. /* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */
  10. #define FLASH_START_ADDRESS CONFIG_SYS_FLASH_BASE
  11. #define FLASH_BANK_SIZE CONFIG_SYS_FLASH_BANK_SIZE
  12. #define SMIBANK0_BASE (FLASH_START_ADDRESS)
  13. #define SMIBANK1_BASE (SMIBANK0_BASE + FLASH_BANK_SIZE)
  14. #define SMIBANK2_BASE (SMIBANK1_BASE + FLASH_BANK_SIZE)
  15. #define SMIBANK3_BASE (SMIBANK2_BASE + FLASH_BANK_SIZE)
  16. #define BANK0 0
  17. #define BANK1 1
  18. #define BANK2 2
  19. #define BANK3 3
  20. struct smi_regs {
  21. u32 smi_cr1;
  22. u32 smi_cr2;
  23. u32 smi_sr;
  24. u32 smi_tr;
  25. u32 smi_rr;
  26. };
  27. /* CONTROL REG 1 */
  28. #define BANK_EN 0x0000000F /* enables all banks */
  29. #define DSEL_TIME 0x00000060 /* Deselect time */
  30. #define PRESCAL5 0x00000500 /* AHB_CK prescaling value */
  31. #define PRESCALA 0x00000A00 /* AHB_CK prescaling value */
  32. #define PRESCAL3 0x00000300 /* AHB_CK prescaling value */
  33. #define PRESCAL4 0x00000400 /* AHB_CK prescaling value */
  34. #define SW_MODE 0x10000000 /* enables SW Mode */
  35. #define WB_MODE 0x20000000 /* Write Burst Mode */
  36. #define FAST_MODE 0x00008000 /* Fast Mode */
  37. #define HOLD1 0x00010000
  38. /* CONTROL REG 2 */
  39. #define RD_STATUS_REG 0x00000400 /* reads status reg */
  40. #define WE 0x00000800 /* Write Enable */
  41. #define BANK0_SEL 0x00000000 /* Select Banck0 */
  42. #define BANK1_SEL 0x00001000 /* Select Banck1 */
  43. #define BANK2_SEL 0x00002000 /* Select Banck2 */
  44. #define BANK3_SEL 0x00003000 /* Select Banck3 */
  45. #define BANKSEL_SHIFT 12
  46. #define SEND 0x00000080 /* Send data */
  47. #define TX_LEN_1 0x00000001 /* data length = 1 byte */
  48. #define TX_LEN_2 0x00000002 /* data length = 2 byte */
  49. #define TX_LEN_3 0x00000003 /* data length = 3 byte */
  50. #define TX_LEN_4 0x00000004 /* data length = 4 byte */
  51. #define RX_LEN_1 0x00000010 /* data length = 1 byte */
  52. #define RX_LEN_2 0x00000020 /* data length = 2 byte */
  53. #define RX_LEN_3 0x00000030 /* data length = 3 byte */
  54. #define RX_LEN_4 0x00000040 /* data length = 4 byte */
  55. #define TFIE 0x00000100 /* Tx Flag Interrupt Enable */
  56. #define WCIE 0x00000200 /* WCF Interrupt Enable */
  57. /* STATUS_REG */
  58. #define INT_WCF_CLR 0xFFFFFDFF /* clear: WCF clear */
  59. #define INT_TFF_CLR 0xFFFFFEFF /* clear: TFF clear */
  60. #define WIP_BIT 0x00000001 /* WIP Bit of SPI SR */
  61. #define WEL_BIT 0x00000002 /* WEL Bit of SPI SR */
  62. #define RSR 0x00000005 /* Read Status regiser */
  63. #define TFF 0x00000100 /* Transfer Finished FLag */
  64. #define WCF 0x00000200 /* Transfer Finished FLag */
  65. #define ERF1 0x00000400 /* Error Flag 1 */
  66. #define ERF2 0x00000800 /* Error Flag 2 */
  67. #define WM0 0x00001000 /* WM Bank 0 */
  68. #define WM1 0x00002000 /* WM Bank 1 */
  69. #define WM2 0x00004000 /* WM Bank 2 */
  70. #define WM3 0x00008000 /* WM Bank 3 */
  71. #define WM_SHIFT 12
  72. /* TR REG */
  73. #define READ_ID 0x0000009F /* Read Identification */
  74. #define BULK_ERASE 0x000000C7 /* BULK erase */
  75. #define SECTOR_ERASE 0x000000D8 /* SECTOR erase */
  76. #define WRITE_ENABLE 0x00000006 /* Wenable command to FLASH */
  77. struct flash_dev {
  78. u32 density;
  79. ulong size;
  80. ushort sector_count;
  81. };
  82. #define SFLASH_PAGE_SIZE 0x100 /* flash page size */
  83. #define XFER_FINISH_TOUT 15 /* xfer finish timeout(in ms) */
  84. #define WMODE_TOUT 15 /* write enable timeout(in ms) */
  85. extern void smi_init(void);
  86. #endif