st_smi.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com.
  5. */
  6. #include <common.h>
  7. #include <flash.h>
  8. #include <linux/delay.h>
  9. #include <linux/err.h>
  10. #include <linux/mtd/st_smi.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/hardware.h>
  13. #if defined(CONFIG_MTD_NOR_FLASH)
  14. static struct smi_regs *const smicntl =
  15. (struct smi_regs * const)CONFIG_SYS_SMI_BASE;
  16. static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] =
  17. CONFIG_SYS_FLASH_ADDR_BASE;
  18. flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
  19. /* data structure to maintain flash ids from different vendors */
  20. struct flash_device {
  21. char *name;
  22. u8 erase_cmd;
  23. u32 device_id;
  24. u32 pagesize;
  25. unsigned long sectorsize;
  26. unsigned long size_in_bytes;
  27. };
  28. #define FLASH_ID(n, es, id, psize, ssize, size) \
  29. { \
  30. .name = n, \
  31. .erase_cmd = es, \
  32. .device_id = id, \
  33. .pagesize = psize, \
  34. .sectorsize = ssize, \
  35. .size_in_bytes = size \
  36. }
  37. /*
  38. * List of supported flash devices.
  39. * Currently the erase_cmd field is not used in this driver.
  40. */
  41. static struct flash_device flash_devices[] = {
  42. FLASH_ID("st m25p16" , 0xd8, 0x00152020, 0x100, 0x10000, 0x200000),
  43. FLASH_ID("st m25p32" , 0xd8, 0x00162020, 0x100, 0x10000, 0x400000),
  44. FLASH_ID("st m25p64" , 0xd8, 0x00172020, 0x100, 0x10000, 0x800000),
  45. FLASH_ID("st m25p128" , 0xd8, 0x00182020, 0x100, 0x40000, 0x1000000),
  46. FLASH_ID("st m25p05" , 0xd8, 0x00102020, 0x80 , 0x8000 , 0x10000),
  47. FLASH_ID("st m25p10" , 0xd8, 0x00112020, 0x80 , 0x8000 , 0x20000),
  48. FLASH_ID("st m25p20" , 0xd8, 0x00122020, 0x100, 0x10000, 0x40000),
  49. FLASH_ID("st m25p40" , 0xd8, 0x00132020, 0x100, 0x10000, 0x80000),
  50. FLASH_ID("st m25p80" , 0xd8, 0x00142020, 0x100, 0x10000, 0x100000),
  51. FLASH_ID("st m45pe10" , 0xd8, 0x00114020, 0x100, 0x10000, 0x20000),
  52. FLASH_ID("st m45pe20" , 0xd8, 0x00124020, 0x100, 0x10000, 0x40000),
  53. FLASH_ID("st m45pe40" , 0xd8, 0x00134020, 0x100, 0x10000, 0x80000),
  54. FLASH_ID("st m45pe80" , 0xd8, 0x00144020, 0x100, 0x10000, 0x100000),
  55. FLASH_ID("sp s25fl004" , 0xd8, 0x00120201, 0x100, 0x10000, 0x80000),
  56. FLASH_ID("sp s25fl008" , 0xd8, 0x00130201, 0x100, 0x10000, 0x100000),
  57. FLASH_ID("sp s25fl016" , 0xd8, 0x00140201, 0x100, 0x10000, 0x200000),
  58. FLASH_ID("sp s25fl032" , 0xd8, 0x00150201, 0x100, 0x10000, 0x400000),
  59. FLASH_ID("sp s25fl064" , 0xd8, 0x00160201, 0x100, 0x10000, 0x800000),
  60. FLASH_ID("mac 25l512" , 0xd8, 0x001020C2, 0x010, 0x10000, 0x10000),
  61. FLASH_ID("mac 25l1005" , 0xd8, 0x001120C2, 0x010, 0x10000, 0x20000),
  62. FLASH_ID("mac 25l2005" , 0xd8, 0x001220C2, 0x010, 0x10000, 0x40000),
  63. FLASH_ID("mac 25l4005" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000),
  64. FLASH_ID("mac 25l4005a" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000),
  65. FLASH_ID("mac 25l8005" , 0xd8, 0x001420C2, 0x010, 0x10000, 0x100000),
  66. FLASH_ID("mac 25l1605" , 0xd8, 0x001520C2, 0x100, 0x10000, 0x200000),
  67. FLASH_ID("mac 25l1605a" , 0xd8, 0x001520C2, 0x010, 0x10000, 0x200000),
  68. FLASH_ID("mac 25l3205" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000),
  69. FLASH_ID("mac 25l3205a" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000),
  70. FLASH_ID("mac 25l6405" , 0xd8, 0x001720C2, 0x100, 0x10000, 0x800000),
  71. FLASH_ID("wbd w25q128" , 0xd8, 0x001840EF, 0x100, 0x10000, 0x1000000),
  72. };
  73. /*
  74. * smi_wait_xfer_finish - Wait until TFF is set in status register
  75. * @timeout: timeout in milliseconds
  76. *
  77. * Wait until TFF is set in status register
  78. */
  79. static int smi_wait_xfer_finish(int timeout)
  80. {
  81. ulong start = get_timer(0);
  82. while (get_timer(start) < timeout) {
  83. if (readl(&smicntl->smi_sr) & TFF)
  84. return 0;
  85. /* Try after 10 ms */
  86. udelay(10);
  87. };
  88. return -1;
  89. }
  90. /*
  91. * smi_read_id - Read flash id
  92. * @info: flash_info structure pointer
  93. * @banknum: bank number
  94. *
  95. * Read the flash id present at bank #banknum
  96. */
  97. static unsigned int smi_read_id(flash_info_t *info, int banknum)
  98. {
  99. unsigned int value;
  100. writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1);
  101. writel(READ_ID, &smicntl->smi_tr);
  102. writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3,
  103. &smicntl->smi_cr2);
  104. if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
  105. return -EIO;
  106. value = (readl(&smicntl->smi_rr) & 0x00FFFFFF);
  107. writel(readl(&smicntl->smi_sr) & ~TFF, &smicntl->smi_sr);
  108. writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
  109. return value;
  110. }
  111. /*
  112. * flash_get_size - Detect the SMI flash by reading the ID.
  113. * @base: Base address of the flash area bank #banknum
  114. * @banknum: Bank number
  115. *
  116. * Detect the SMI flash by reading the ID. Initializes the flash_info structure
  117. * with size, sector count etc.
  118. */
  119. static ulong flash_get_size(ulong base, int banknum)
  120. {
  121. flash_info_t *info = &flash_info[banknum];
  122. int value;
  123. int i;
  124. value = smi_read_id(info, banknum);
  125. if (value < 0) {
  126. printf("Flash id could not be read\n");
  127. return 0;
  128. }
  129. /* Matches chip-id to entire list of 'serial-nor flash' ids */
  130. for (i = 0; i < ARRAY_SIZE(flash_devices); i++) {
  131. if (flash_devices[i].device_id == value) {
  132. info->size = flash_devices[i].size_in_bytes;
  133. info->flash_id = value;
  134. info->start[0] = base;
  135. info->sector_count =
  136. info->size/flash_devices[i].sectorsize;
  137. return info->size;
  138. }
  139. }
  140. return 0;
  141. }
  142. /*
  143. * smi_read_sr - Read status register of SMI
  144. * @bank: bank number
  145. *
  146. * This routine will get the status register of the flash chip present at the
  147. * given bank
  148. */
  149. static int smi_read_sr(int bank)
  150. {
  151. u32 ctrlreg1, val;
  152. /* store the CTRL REG1 state */
  153. ctrlreg1 = readl(&smicntl->smi_cr1);
  154. /* Program SMI in HW Mode */
  155. writel(readl(&smicntl->smi_cr1) & ~(SW_MODE | WB_MODE),
  156. &smicntl->smi_cr1);
  157. /* Performing a RSR instruction in HW mode */
  158. writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2);
  159. if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
  160. return -1;
  161. val = readl(&smicntl->smi_sr);
  162. /* Restore the CTRL REG1 state */
  163. writel(ctrlreg1, &smicntl->smi_cr1);
  164. return val;
  165. }
  166. /*
  167. * smi_wait_till_ready - Wait till last operation is over.
  168. * @bank: bank number shifted.
  169. * @timeout: timeout in milliseconds.
  170. *
  171. * This routine checks for WIP(write in progress)bit in Status register(SMSR-b0)
  172. * The routine checks for #timeout loops, each at interval of 1 milli-second.
  173. * If successful the routine returns 0.
  174. */
  175. static int smi_wait_till_ready(int bank, int timeout)
  176. {
  177. int sr;
  178. ulong start = get_timer(0);
  179. /* One chip guarantees max 5 msec wait here after page writes,
  180. but potentially three seconds (!) after page erase. */
  181. while (get_timer(start) < timeout) {
  182. sr = smi_read_sr(bank);
  183. if ((sr >= 0) && (!(sr & WIP_BIT)))
  184. return 0;
  185. /* Try again after 10 usec */
  186. udelay(10);
  187. } while (timeout--);
  188. printf("SMI controller is still in wait, timeout=%d\n", timeout);
  189. return -EIO;
  190. }
  191. /*
  192. * smi_write_enable - Enable the flash to do write operation
  193. * @bank: bank number
  194. *
  195. * Set write enable latch with Write Enable command.
  196. * Returns negative if error occurred.
  197. */
  198. static int smi_write_enable(int bank)
  199. {
  200. u32 ctrlreg1;
  201. u32 start;
  202. int timeout = WMODE_TOUT;
  203. int sr;
  204. /* Store the CTRL REG1 state */
  205. ctrlreg1 = readl(&smicntl->smi_cr1);
  206. /* Program SMI in H/W Mode */
  207. writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
  208. /* Give the Flash, Write Enable command */
  209. writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2);
  210. if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
  211. return -1;
  212. /* Restore the CTRL REG1 state */
  213. writel(ctrlreg1, &smicntl->smi_cr1);
  214. start = get_timer(0);
  215. while (get_timer(start) < timeout) {
  216. sr = smi_read_sr(bank);
  217. if ((sr >= 0) && (sr & (1 << (bank + WM_SHIFT))))
  218. return 0;
  219. /* Try again after 10 usec */
  220. udelay(10);
  221. };
  222. return -1;
  223. }
  224. /*
  225. * smi_init - SMI initialization routine
  226. *
  227. * SMI initialization routine. Sets SMI control register1.
  228. */
  229. void smi_init(void)
  230. {
  231. /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
  232. writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
  233. &smicntl->smi_cr1);
  234. }
  235. /*
  236. * smi_sector_erase - Erase flash sector
  237. * @info: flash_info structure pointer
  238. * @sector: sector number
  239. *
  240. * Set write enable latch with Write Enable command.
  241. * Returns negative if error occurred.
  242. */
  243. static int smi_sector_erase(flash_info_t *info, unsigned int sector)
  244. {
  245. int bank;
  246. unsigned int sect_add;
  247. unsigned int instruction;
  248. switch (info->start[0]) {
  249. case SMIBANK0_BASE:
  250. bank = BANK0;
  251. break;
  252. case SMIBANK1_BASE:
  253. bank = BANK1;
  254. break;
  255. case SMIBANK2_BASE:
  256. bank = BANK2;
  257. break;
  258. case SMIBANK3_BASE:
  259. bank = BANK3;
  260. break;
  261. default:
  262. return -1;
  263. }
  264. sect_add = sector * (info->size / info->sector_count);
  265. instruction = ((sect_add >> 8) & 0x0000FF00) | SECTOR_ERASE;
  266. writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr);
  267. /* Wait until finished previous write command. */
  268. if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
  269. return -EBUSY;
  270. /* Send write enable, before erase commands. */
  271. if (smi_write_enable(bank))
  272. return -EIO;
  273. /* Put SMI in SW mode */
  274. writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1);
  275. /* Send Sector Erase command in SW Mode */
  276. writel(instruction, &smicntl->smi_tr);
  277. writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4,
  278. &smicntl->smi_cr2);
  279. if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
  280. return -EIO;
  281. if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
  282. return -EBUSY;
  283. /* Put SMI in HW mode */
  284. writel(readl(&smicntl->smi_cr1) & ~SW_MODE,
  285. &smicntl->smi_cr1);
  286. return 0;
  287. }
  288. /*
  289. * smi_write - Write to SMI flash
  290. * @src_addr: source buffer
  291. * @dst_addr: destination buffer
  292. * @length: length to write in bytes
  293. * @bank: bank base address
  294. *
  295. * Write to SMI flash
  296. */
  297. static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
  298. unsigned int length, ulong bank_addr)
  299. {
  300. u8 *src_addr8 = (u8 *)src_addr;
  301. u8 *dst_addr8 = (u8 *)dst_addr;
  302. int banknum;
  303. int i;
  304. switch (bank_addr) {
  305. case SMIBANK0_BASE:
  306. banknum = BANK0;
  307. break;
  308. case SMIBANK1_BASE:
  309. banknum = BANK1;
  310. break;
  311. case SMIBANK2_BASE:
  312. banknum = BANK2;
  313. break;
  314. case SMIBANK3_BASE:
  315. banknum = BANK3;
  316. break;
  317. default:
  318. return -1;
  319. }
  320. if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT))
  321. return -EBUSY;
  322. /* Set SMI in Hardware Mode */
  323. writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
  324. if (smi_write_enable(banknum))
  325. return -EIO;
  326. /* Perform the write command */
  327. for (i = 0; i < length; i += 4) {
  328. if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) {
  329. if (smi_wait_till_ready(banknum,
  330. CONFIG_SYS_FLASH_WRITE_TOUT))
  331. return -EBUSY;
  332. if (smi_write_enable(banknum))
  333. return -EIO;
  334. }
  335. if (length < 4) {
  336. int k;
  337. /*
  338. * Handle special case, where length < 4 (redundant env)
  339. */
  340. for (k = 0; k < length; k++)
  341. *dst_addr8++ = *src_addr8++;
  342. } else {
  343. /* Normal 32bit write */
  344. *dst_addr++ = *src_addr++;
  345. }
  346. if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2)))
  347. return -EIO;
  348. }
  349. if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT))
  350. return -EBUSY;
  351. writel(readl(&smicntl->smi_sr) & ~(WCF), &smicntl->smi_sr);
  352. return 0;
  353. }
  354. /*
  355. * write_buff - Write to SMI flash
  356. * @info: flash info structure
  357. * @src: source buffer
  358. * @dest_addr: destination buffer
  359. * @length: length to write in words
  360. *
  361. * Write to SMI flash
  362. */
  363. int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length)
  364. {
  365. return smi_write((unsigned int *)src, (unsigned int *)dest_addr,
  366. length, info->start[0]);
  367. }
  368. /*
  369. * flash_init - SMI flash initialization
  370. *
  371. * SMI flash initialization
  372. */
  373. unsigned long flash_init(void)
  374. {
  375. unsigned long size = 0;
  376. int i, j;
  377. smi_init();
  378. for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
  379. flash_info[i].flash_id = FLASH_UNKNOWN;
  380. size += flash_info[i].size = flash_get_size(bank_base[i], i);
  381. }
  382. for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) {
  383. for (i = 1; i < flash_info[j].sector_count; i++)
  384. flash_info[j].start[i] =
  385. flash_info[j].start[i - 1] +
  386. flash_info->size / flash_info->sector_count;
  387. }
  388. return size;
  389. }
  390. /*
  391. * flash_print_info - Print SMI flash information
  392. *
  393. * Print SMI flash information
  394. */
  395. void flash_print_info(flash_info_t *info)
  396. {
  397. int i;
  398. if (info->flash_id == FLASH_UNKNOWN) {
  399. puts("missing or unknown FLASH type\n");
  400. return;
  401. }
  402. if (info->size >= 0x100000)
  403. printf(" Size: %ld MB in %d Sectors\n",
  404. info->size >> 20, info->sector_count);
  405. else
  406. printf(" Size: %ld KB in %d Sectors\n",
  407. info->size >> 10, info->sector_count);
  408. puts(" Sector Start Addresses:");
  409. for (i = 0; i < info->sector_count; ++i) {
  410. #ifdef CONFIG_SYS_FLASH_EMPTY_INFO
  411. int size;
  412. int erased;
  413. u32 *flash;
  414. /*
  415. * Check if whole sector is erased
  416. */
  417. size = (info->size) / (info->sector_count);
  418. flash = (u32 *) info->start[i];
  419. size = size / sizeof(int);
  420. while ((size--) && (*flash++ == ~0))
  421. ;
  422. size++;
  423. if (size)
  424. erased = 0;
  425. else
  426. erased = 1;
  427. if ((i % 5) == 0)
  428. printf("\n");
  429. printf(" %08lX%s%s",
  430. info->start[i],
  431. erased ? " E" : " ", info->protect[i] ? "RO " : " ");
  432. #else
  433. if ((i % 5) == 0)
  434. printf("\n ");
  435. printf(" %08lX%s",
  436. info->start[i], info->protect[i] ? " (RO) " : " ");
  437. #endif
  438. }
  439. putc('\n');
  440. return;
  441. }
  442. /*
  443. * flash_erase - Erase SMI flash
  444. *
  445. * Erase SMI flash
  446. */
  447. int flash_erase(flash_info_t *info, int s_first, int s_last)
  448. {
  449. int rcode = 0;
  450. int prot = 0;
  451. flash_sect_t sect;
  452. if ((s_first < 0) || (s_first > s_last)) {
  453. puts("- no sectors to erase\n");
  454. return 1;
  455. }
  456. for (sect = s_first; sect <= s_last; ++sect) {
  457. if (info->protect[sect])
  458. prot++;
  459. }
  460. if (prot) {
  461. printf("- Warning: %d protected sectors will not be erased!\n",
  462. prot);
  463. } else {
  464. putc('\n');
  465. }
  466. for (sect = s_first; sect <= s_last; sect++) {
  467. if (info->protect[sect] == 0) {
  468. if (smi_sector_erase(info, sect))
  469. rcode = 1;
  470. else
  471. putc('.');
  472. }
  473. }
  474. puts(" done\n");
  475. return rcode;
  476. }
  477. #endif