iomux-v3.h 5.8 KB

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  1. /*
  2. * Based on Linux i.MX iomux-v3.h file:
  3. * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
  4. * <armlinux@phytec.de>
  5. *
  6. * Copyright (C) 2011 Freescale Semiconductor, Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * as published by the Free Software Foundation; either version 2
  11. * of the License, or (at your option) any later version.
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  20. * MA 02110-1301, USA.
  21. */
  22. #ifndef __MACH_IOMUX_V3_H__
  23. #define __MACH_IOMUX_V3_H__
  24. #include <common.h>
  25. /*
  26. * build IOMUX_PAD structure
  27. *
  28. * This iomux scheme is based around pads, which are the physical balls
  29. * on the processor.
  30. *
  31. * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
  32. * things like driving strength and pullup/pulldown.
  33. * - Each pad can have but not necessarily does have an output routing register
  34. * (IOMUXC_SW_MUX_CTL_PAD_x).
  35. * - Each pad can have but not necessarily does have an input routing register
  36. * (IOMUXC_x_SELECT_INPUT)
  37. *
  38. * The three register sets do not have a fixed offset to each other,
  39. * hence we order this table by pad control registers (which all pads
  40. * have) and put the optional i/o routing registers into additional
  41. * fields.
  42. *
  43. * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
  44. * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
  45. *
  46. * IOMUX/PAD Bit field definitions
  47. *
  48. * MUX_CTRL_OFS: 0..11 (12)
  49. * PAD_CTRL_OFS: 12..23 (12)
  50. * SEL_INPUT_OFS: 24..35 (12)
  51. * MUX_MODE + SION: 36..40 (5)
  52. * PAD_CTRL + NO_PAD_CTRL: 41..58 (18)
  53. * SEL_INP: 59..62 (4)
  54. * reserved: 63 (1)
  55. */
  56. typedef u64 iomux_v3_cfg_t;
  57. #define MUX_CTRL_OFS_SHIFT 0
  58. #define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
  59. #define MUX_PAD_CTRL_OFS_SHIFT 12
  60. #define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
  61. MUX_PAD_CTRL_OFS_SHIFT)
  62. #define MUX_SEL_INPUT_OFS_SHIFT 24
  63. #define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
  64. MUX_SEL_INPUT_OFS_SHIFT)
  65. #define MUX_MODE_SHIFT 36
  66. #define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
  67. #define MUX_PAD_CTRL_SHIFT 41
  68. #define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
  69. #define MUX_SEL_INPUT_SHIFT 59
  70. #define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
  71. #define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
  72. #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
  73. sel_input, pad_ctrl) \
  74. (((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
  75. ((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \
  76. ((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
  77. ((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
  78. ((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \
  79. ((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
  80. #define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \
  81. MUX_PAD_CTRL(pad))
  82. #define __NA_ 0x000
  83. #define NO_MUX_I 0
  84. #define NO_PAD_I 0
  85. #define NO_PAD_CTRL (1 << 17)
  86. #ifdef CONFIG_MX6
  87. #define PAD_CTL_HYS (1 << 16)
  88. #define PAD_CTL_PUS_100K_DOWN (0 << 14 | PAD_CTL_PUE)
  89. #define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE)
  90. #define PAD_CTL_PUS_100K_UP (2 << 14 | PAD_CTL_PUE)
  91. #define PAD_CTL_PUS_22K_UP (3 << 14 | PAD_CTL_PUE)
  92. #define PAD_CTL_PUE (1 << 13 | PAD_CTL_PKE)
  93. #define PAD_CTL_PKE (1 << 12)
  94. #define PAD_CTL_ODE (1 << 11)
  95. #define PAD_CTL_SPEED_LOW (1 << 6)
  96. #define PAD_CTL_SPEED_MED (2 << 6)
  97. #define PAD_CTL_SPEED_HIGH (3 << 6)
  98. #define PAD_CTL_DSE_DISABLE (0 << 3)
  99. #define PAD_CTL_DSE_240ohm (1 << 3)
  100. #define PAD_CTL_DSE_120ohm (2 << 3)
  101. #define PAD_CTL_DSE_80ohm (3 << 3)
  102. #define PAD_CTL_DSE_60ohm (4 << 3)
  103. #define PAD_CTL_DSE_48ohm (5 << 3)
  104. #define PAD_CTL_DSE_40ohm (6 << 3)
  105. #define PAD_CTL_DSE_34ohm (7 << 3)
  106. #elif defined(CONFIG_VF610)
  107. #define PAD_MUX_MODE_SHIFT 20
  108. #define PAD_CTL_SPEED_MED (1 << 12)
  109. #define PAD_CTL_SPEED_HIGH (3 << 12)
  110. #define PAD_CTL_DSE_50ohm (3 << 6)
  111. #define PAD_CTL_DSE_25ohm (6 << 6)
  112. #define PAD_CTL_DSE_20ohm (7 << 6)
  113. #define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
  114. #define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
  115. #define PAD_CTL_PKE (1 << 3)
  116. #define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE)
  117. #define PAD_CTL_OBE_IBE_ENABLE (3 << 0)
  118. #else
  119. #define PAD_CTL_DVS (1 << 13)
  120. #define PAD_CTL_INPUT_DDR (1 << 9)
  121. #define PAD_CTL_HYS (1 << 8)
  122. #define PAD_CTL_PKE (1 << 7)
  123. #define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
  124. #define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
  125. #define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
  126. #define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
  127. #define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
  128. #define PAD_CTL_ODE (1 << 3)
  129. #define PAD_CTL_DSE_LOW (0 << 1)
  130. #define PAD_CTL_DSE_MED (1 << 1)
  131. #define PAD_CTL_DSE_HIGH (2 << 1)
  132. #define PAD_CTL_DSE_MAX (3 << 1)
  133. #endif
  134. #define PAD_CTL_SRE_SLOW (0 << 0)
  135. #define PAD_CTL_SRE_FAST (1 << 0)
  136. #define IOMUX_CONFIG_SION 0x10
  137. #define GPIO_PIN_MASK 0x1f
  138. #define GPIO_PORT_SHIFT 5
  139. #define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
  140. #define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
  141. #define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
  142. #define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
  143. #define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
  144. #define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
  145. #define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
  146. void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
  147. void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
  148. unsigned count);
  149. #endif /* __MACH_IOMUX_V3_H__*/