stm32mp157c-ed1-u-boot.dtsi 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright : STMicroelectronics 2018
  4. */
  5. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  6. #include "stm32mp15-u-boot.dtsi"
  7. #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
  8. / {
  9. aliases {
  10. i2c3 = &i2c4;
  11. };
  12. config {
  13. u-boot,boot-led = "heartbeat";
  14. u-boot,error-led = "error";
  15. u-boot,mmc-env-partition = "fip";
  16. st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
  17. st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
  18. };
  19. #if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL)
  20. config {
  21. u-boot,mmc-env-partition = "ssbl";
  22. };
  23. #endif
  24. #ifdef CONFIG_STM32MP15x_STM32IMAGE
  25. /* only needed for boot with TF-A, witout FIP support */
  26. firmware {
  27. optee {
  28. compatible = "linaro,optee-tz";
  29. method = "smc";
  30. };
  31. };
  32. reserved-memory {
  33. optee@fe000000 {
  34. reg = <0xfe000000 0x02000000>;
  35. no-map;
  36. };
  37. };
  38. #endif
  39. led {
  40. red {
  41. label = "error";
  42. gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  43. default-state = "off";
  44. status = "okay";
  45. };
  46. };
  47. };
  48. &clk_hse {
  49. st,digbypass;
  50. };
  51. &i2c4 {
  52. u-boot,dm-pre-reloc;
  53. };
  54. &i2c4_pins_a {
  55. u-boot,dm-pre-reloc;
  56. pins {
  57. u-boot,dm-pre-reloc;
  58. };
  59. };
  60. &pmic {
  61. u-boot,dm-pre-reloc;
  62. };
  63. &rcc {
  64. st,clksrc = <
  65. CLK_MPU_PLL1P
  66. CLK_AXI_PLL2P
  67. CLK_MCU_PLL3P
  68. CLK_PLL12_HSE
  69. CLK_PLL3_HSE
  70. CLK_PLL4_HSE
  71. CLK_RTC_LSE
  72. CLK_MCO1_DISABLED
  73. CLK_MCO2_DISABLED
  74. >;
  75. st,clkdiv = <
  76. 1 /*MPU*/
  77. 0 /*AXI*/
  78. 0 /*MCU*/
  79. 1 /*APB1*/
  80. 1 /*APB2*/
  81. 1 /*APB3*/
  82. 1 /*APB4*/
  83. 2 /*APB5*/
  84. 23 /*RTC*/
  85. 0 /*MCO1*/
  86. 0 /*MCO2*/
  87. >;
  88. st,pkcs = <
  89. CLK_CKPER_HSE
  90. CLK_FMC_ACLK
  91. CLK_QSPI_ACLK
  92. CLK_ETH_DISABLED
  93. CLK_SDMMC12_PLL4P
  94. CLK_DSI_DSIPLL
  95. CLK_STGEN_HSE
  96. CLK_USBPHY_HSE
  97. CLK_SPI2S1_PLL3Q
  98. CLK_SPI2S23_PLL3Q
  99. CLK_SPI45_HSI
  100. CLK_SPI6_HSI
  101. CLK_I2C46_HSI
  102. CLK_SDMMC3_PLL4P
  103. CLK_USBO_USBPHY
  104. CLK_ADC_CKPER
  105. CLK_CEC_LSE
  106. CLK_I2C12_HSI
  107. CLK_I2C35_HSI
  108. CLK_UART1_HSI
  109. CLK_UART24_HSI
  110. CLK_UART35_HSI
  111. CLK_UART6_HSI
  112. CLK_UART78_HSI
  113. CLK_SPDIF_PLL4P
  114. CLK_FDCAN_PLL4R
  115. CLK_SAI1_PLL3Q
  116. CLK_SAI2_PLL3Q
  117. CLK_SAI3_PLL3Q
  118. CLK_SAI4_PLL3Q
  119. CLK_RNG1_LSI
  120. CLK_RNG2_LSI
  121. CLK_LPTIM1_PCLK1
  122. CLK_LPTIM23_PCLK3
  123. CLK_LPTIM45_LSE
  124. >;
  125. /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
  126. pll2: st,pll@1 {
  127. compatible = "st,stm32mp1-pll";
  128. reg = <1>;
  129. cfg = < 2 65 1 0 0 PQR(1,1,1) >;
  130. frac = < 0x1400 >;
  131. u-boot,dm-pre-reloc;
  132. };
  133. /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
  134. pll3: st,pll@2 {
  135. compatible = "st,stm32mp1-pll";
  136. reg = <2>;
  137. cfg = < 1 33 1 16 36 PQR(1,1,1) >;
  138. frac = < 0x1a04 >;
  139. u-boot,dm-pre-reloc;
  140. };
  141. /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
  142. pll4: st,pll@3 {
  143. compatible = "st,stm32mp1-pll";
  144. reg = <3>;
  145. cfg = < 3 98 5 7 7 PQR(1,1,1) >;
  146. u-boot,dm-pre-reloc;
  147. };
  148. };
  149. &sdmmc1 {
  150. u-boot,dm-spl;
  151. };
  152. &sdmmc1_b4_pins_a {
  153. u-boot,dm-spl;
  154. pins1 {
  155. u-boot,dm-spl;
  156. };
  157. pins2 {
  158. u-boot,dm-spl;
  159. };
  160. };
  161. &sdmmc1_dir_pins_a {
  162. u-boot,dm-spl;
  163. pins1 {
  164. u-boot,dm-spl;
  165. };
  166. pins2 {
  167. u-boot,dm-spl;
  168. };
  169. };
  170. &sdmmc2 {
  171. u-boot,dm-spl;
  172. };
  173. &sdmmc2_b4_pins_a {
  174. u-boot,dm-spl;
  175. pins1 {
  176. u-boot,dm-spl;
  177. };
  178. pins2 {
  179. u-boot,dm-spl;
  180. };
  181. };
  182. &sdmmc2_d47_pins_a {
  183. u-boot,dm-spl;
  184. pins {
  185. u-boot,dm-spl;
  186. };
  187. };
  188. &uart4 {
  189. u-boot,dm-pre-reloc;
  190. };
  191. &uart4_pins_a {
  192. u-boot,dm-pre-reloc;
  193. pins1 {
  194. u-boot,dm-pre-reloc;
  195. };
  196. pins2 {
  197. u-boot,dm-pre-reloc;
  198. /* pull-up on rx to avoid floating level */
  199. bias-pull-up;
  200. };
  201. };