stm32mp157a-dk1-u-boot.dtsi 3.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright : STMicroelectronics 2018
  4. */
  5. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  6. #include "stm32mp15-u-boot.dtsi"
  7. #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
  8. / {
  9. aliases {
  10. i2c3 = &i2c4;
  11. usb0 = &usbotg_hs;
  12. };
  13. config {
  14. u-boot,boot-led = "heartbeat";
  15. u-boot,error-led = "error";
  16. u-boot,mmc-env-partition = "fip";
  17. st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
  18. st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
  19. st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
  20. };
  21. #if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL)
  22. config {
  23. u-boot,mmc-env-partition = "ssbl";
  24. };
  25. #endif
  26. #ifdef CONFIG_STM32MP15x_STM32IMAGE
  27. /* only needed for boot with TF-A, witout FIP support */
  28. firmware {
  29. optee {
  30. compatible = "linaro,optee-tz";
  31. method = "smc";
  32. };
  33. };
  34. reserved-memory {
  35. u-boot,dm-spl;
  36. optee@de000000 {
  37. reg = <0xde000000 0x02000000>;
  38. no-map;
  39. u-boot,dm-spl;
  40. };
  41. };
  42. #endif
  43. led {
  44. red {
  45. label = "error";
  46. gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  47. default-state = "off";
  48. status = "okay";
  49. };
  50. };
  51. };
  52. &adc {
  53. status = "okay";
  54. };
  55. &clk_hse {
  56. st,digbypass;
  57. };
  58. &i2c4 {
  59. u-boot,dm-pre-reloc;
  60. };
  61. &i2c4_pins_a {
  62. u-boot,dm-pre-reloc;
  63. pins {
  64. u-boot,dm-pre-reloc;
  65. };
  66. };
  67. &pmic {
  68. u-boot,dm-pre-reloc;
  69. };
  70. &rcc {
  71. st,clksrc = <
  72. CLK_MPU_PLL1P
  73. CLK_AXI_PLL2P
  74. CLK_MCU_PLL3P
  75. CLK_PLL12_HSE
  76. CLK_PLL3_HSE
  77. CLK_PLL4_HSE
  78. CLK_RTC_LSE
  79. CLK_MCO1_DISABLED
  80. CLK_MCO2_DISABLED
  81. >;
  82. st,clkdiv = <
  83. 1 /*MPU*/
  84. 0 /*AXI*/
  85. 0 /*MCU*/
  86. 1 /*APB1*/
  87. 1 /*APB2*/
  88. 1 /*APB3*/
  89. 1 /*APB4*/
  90. 2 /*APB5*/
  91. 23 /*RTC*/
  92. 0 /*MCO1*/
  93. 0 /*MCO2*/
  94. >;
  95. st,pkcs = <
  96. CLK_CKPER_HSE
  97. CLK_FMC_ACLK
  98. CLK_QSPI_ACLK
  99. CLK_ETH_DISABLED
  100. CLK_SDMMC12_PLL4P
  101. CLK_DSI_DSIPLL
  102. CLK_STGEN_HSE
  103. CLK_USBPHY_HSE
  104. CLK_SPI2S1_PLL3Q
  105. CLK_SPI2S23_PLL3Q
  106. CLK_SPI45_HSI
  107. CLK_SPI6_HSI
  108. CLK_I2C46_HSI
  109. CLK_SDMMC3_PLL4P
  110. CLK_USBO_USBPHY
  111. CLK_ADC_CKPER
  112. CLK_CEC_LSE
  113. CLK_I2C12_HSI
  114. CLK_I2C35_HSI
  115. CLK_UART1_HSI
  116. CLK_UART24_HSI
  117. CLK_UART35_HSI
  118. CLK_UART6_HSI
  119. CLK_UART78_HSI
  120. CLK_SPDIF_PLL4P
  121. CLK_FDCAN_PLL4R
  122. CLK_SAI1_PLL3Q
  123. CLK_SAI2_PLL3Q
  124. CLK_SAI3_PLL3Q
  125. CLK_SAI4_PLL3Q
  126. CLK_RNG1_LSI
  127. CLK_RNG2_LSI
  128. CLK_LPTIM1_PCLK1
  129. CLK_LPTIM23_PCLK3
  130. CLK_LPTIM45_LSE
  131. >;
  132. /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
  133. pll2: st,pll@1 {
  134. compatible = "st,stm32mp1-pll";
  135. reg = <1>;
  136. cfg = < 2 65 1 0 0 PQR(1,1,1) >;
  137. frac = < 0x1400 >;
  138. u-boot,dm-pre-reloc;
  139. };
  140. /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
  141. pll3: st,pll@2 {
  142. compatible = "st,stm32mp1-pll";
  143. reg = <2>;
  144. cfg = < 1 33 1 16 36 PQR(1,1,1) >;
  145. frac = < 0x1a04 >;
  146. u-boot,dm-pre-reloc;
  147. };
  148. /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
  149. pll4: st,pll@3 {
  150. compatible = "st,stm32mp1-pll";
  151. reg = <3>;
  152. cfg = < 3 98 5 7 7 PQR(1,1,1) >;
  153. u-boot,dm-pre-reloc;
  154. };
  155. };
  156. &sdmmc1 {
  157. u-boot,dm-spl;
  158. };
  159. &sdmmc1_b4_pins_a {
  160. u-boot,dm-spl;
  161. pins1 {
  162. u-boot,dm-spl;
  163. };
  164. pins2 {
  165. u-boot,dm-spl;
  166. };
  167. };
  168. &uart4 {
  169. u-boot,dm-pre-reloc;
  170. };
  171. &uart4_pins_a {
  172. u-boot,dm-pre-reloc;
  173. pins1 {
  174. u-boot,dm-pre-reloc;
  175. };
  176. pins2 {
  177. u-boot,dm-pre-reloc;
  178. /* pull-up on rx to avoid floating level */
  179. bias-pull-up;
  180. };
  181. };
  182. &usbotg_hs {
  183. u-boot,force-b-session-valid;
  184. };