zynqmp_firmware.h 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Xilinx Zynq MPSoC Firmware driver
  4. *
  5. * Copyright (C) 2018-2019 Xilinx, Inc.
  6. */
  7. #ifndef _ZYNQMP_FIRMWARE_H_
  8. #define _ZYNQMP_FIRMWARE_H_
  9. enum pm_api_id {
  10. PM_GET_API_VERSION = 1,
  11. PM_SET_CONFIGURATION = 2,
  12. PM_GET_NODE_STATUS = 3,
  13. PM_GET_OPERATING_CHARACTERISTIC = 4,
  14. PM_REGISTER_NOTIFIER = 5,
  15. /* API for suspending */
  16. PM_REQUEST_SUSPEND = 6,
  17. PM_SELF_SUSPEND = 7,
  18. PM_FORCE_POWERDOWN = 8,
  19. PM_ABORT_SUSPEND = 9,
  20. PM_REQUEST_WAKEUP = 10,
  21. PM_SET_WAKEUP_SOURCE = 11,
  22. PM_SYSTEM_SHUTDOWN = 12,
  23. PM_REQUEST_NODE = 13,
  24. PM_RELEASE_NODE = 14,
  25. PM_SET_REQUIREMENT = 15,
  26. PM_SET_MAX_LATENCY = 16,
  27. /* Direct control API functions: */
  28. PM_RESET_ASSERT = 17,
  29. PM_RESET_GET_STATUS = 18,
  30. PM_MMIO_WRITE = 19,
  31. PM_MMIO_READ = 20,
  32. PM_PM_INIT_FINALIZE = 21,
  33. PM_FPGA_LOAD = 22,
  34. PM_FPGA_GET_STATUS = 23,
  35. PM_GET_CHIPID = 24,
  36. /* ID 25 is been used by U-Boot to process secure boot images */
  37. /* Secure library generic API functions */
  38. PM_SECURE_SHA = 26,
  39. PM_SECURE_RSA = 27,
  40. PM_PINCTRL_REQUEST = 28,
  41. PM_PINCTRL_RELEASE = 29,
  42. PM_PINCTRL_GET_FUNCTION = 30,
  43. PM_PINCTRL_SET_FUNCTION = 31,
  44. PM_PINCTRL_CONFIG_PARAM_GET = 32,
  45. PM_PINCTRL_CONFIG_PARAM_SET = 33,
  46. PM_IOCTL = 34,
  47. PM_QUERY_DATA = 35,
  48. PM_CLOCK_ENABLE = 36,
  49. PM_CLOCK_DISABLE = 37,
  50. PM_CLOCK_GETSTATE = 38,
  51. PM_CLOCK_SETDIVIDER = 39,
  52. PM_CLOCK_GETDIVIDER = 40,
  53. PM_CLOCK_SETRATE = 41,
  54. PM_CLOCK_GETRATE = 42,
  55. PM_CLOCK_SETPARENT = 43,
  56. PM_CLOCK_GETPARENT = 44,
  57. PM_SECURE_IMAGE = 45,
  58. PM_FPGA_READ = 46,
  59. PM_SECURE_AES = 47,
  60. PM_CLOCK_PLL_GETPARAM = 49,
  61. /* PM_REGISTER_ACCESS API */
  62. PM_REGISTER_ACCESS = 52,
  63. PM_EFUSE_ACCESS = 53,
  64. PM_FEATURE_CHECK = 63,
  65. PM_API_MAX,
  66. };
  67. enum pm_node_id {
  68. NODE_UNKNOWN = 0,
  69. NODE_APU = 1,
  70. NODE_APU_0 = 2,
  71. NODE_APU_1 = 3,
  72. NODE_APU_2 = 4,
  73. NODE_APU_3 = 5,
  74. NODE_RPU = 6,
  75. NODE_RPU_0 = 7,
  76. NODE_RPU_1 = 8,
  77. NODE_PLD = 9,
  78. NODE_FPD = 10,
  79. NODE_OCM_BANK_0 = 11,
  80. NODE_OCM_BANK_1 = 12,
  81. NODE_OCM_BANK_2 = 13,
  82. NODE_OCM_BANK_3 = 14,
  83. NODE_TCM_0_A = 15,
  84. NODE_TCM_0_B = 16,
  85. NODE_TCM_1_A = 17,
  86. NODE_TCM_1_B = 18,
  87. NODE_L2 = 19,
  88. NODE_GPU_PP_0 = 20,
  89. NODE_GPU_PP_1 = 21,
  90. NODE_USB_0 = 22,
  91. NODE_USB_1 = 23,
  92. NODE_TTC_0 = 24,
  93. NODE_TTC_1 = 25,
  94. NODE_TTC_2 = 26,
  95. NODE_TTC_3 = 27,
  96. NODE_SATA = 28,
  97. NODE_ETH_0 = 29,
  98. NODE_ETH_1 = 30,
  99. NODE_ETH_2 = 31,
  100. NODE_ETH_3 = 32,
  101. NODE_UART_0 = 33,
  102. NODE_UART_1 = 34,
  103. NODE_SPI_0 = 35,
  104. NODE_SPI_1 = 36,
  105. NODE_I2C_0 = 37,
  106. NODE_I2C_1 = 38,
  107. NODE_SD_0 = 39,
  108. NODE_SD_1 = 40,
  109. NODE_DP = 41,
  110. NODE_GDMA = 42,
  111. NODE_ADMA = 43,
  112. NODE_NAND = 44,
  113. NODE_QSPI = 45,
  114. NODE_GPIO = 46,
  115. NODE_CAN_0 = 47,
  116. NODE_CAN_1 = 48,
  117. NODE_EXTERN = 49,
  118. NODE_APLL = 50,
  119. NODE_VPLL = 51,
  120. NODE_DPLL = 52,
  121. NODE_RPLL = 53,
  122. NODE_IOPLL = 54,
  123. NODE_DDR = 55,
  124. NODE_IPI_APU = 56,
  125. NODE_IPI_RPU_0 = 57,
  126. NODE_GPU = 58,
  127. NODE_PCIE = 59,
  128. NODE_PCAP = 60,
  129. NODE_RTC = 61,
  130. NODE_LPD = 62,
  131. NODE_VCU = 63,
  132. NODE_IPI_RPU_1 = 64,
  133. NODE_IPI_PL_0 = 65,
  134. NODE_IPI_PL_1 = 66,
  135. NODE_IPI_PL_2 = 67,
  136. NODE_IPI_PL_3 = 68,
  137. NODE_PL = 69,
  138. NODE_GEM_TSU = 70,
  139. NODE_SWDT_0 = 71,
  140. NODE_SWDT_1 = 72,
  141. NODE_CSU = 73,
  142. NODE_PJTAG = 74,
  143. NODE_TRACE = 75,
  144. NODE_TESTSCAN = 76,
  145. NODE_PMU = 77,
  146. NODE_MAX = 78,
  147. };
  148. enum tap_delay_type {
  149. PM_TAPDELAY_INPUT = 0,
  150. PM_TAPDELAY_OUTPUT = 1,
  151. };
  152. enum dll_reset_type {
  153. PM_DLL_RESET_ASSERT = 0,
  154. PM_DLL_RESET_RELEASE = 1,
  155. PM_DLL_RESET_PULSE = 2,
  156. };
  157. enum ospi_mux_select_type {
  158. PM_OSPI_MUX_SEL_DMA,
  159. PM_OSPI_MUX_SEL_LINEAR,
  160. PM_OSPI_MUX_GET_MODE,
  161. };
  162. enum pm_query_id {
  163. PM_QID_INVALID = 0,
  164. PM_QID_CLOCK_GET_NAME = 1,
  165. PM_QID_CLOCK_GET_TOPOLOGY = 2,
  166. PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
  167. PM_QID_CLOCK_GET_PARENTS = 4,
  168. PM_QID_CLOCK_GET_ATTRIBUTES = 5,
  169. PM_QID_PINCTRL_GET_NUM_PINS = 6,
  170. PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
  171. PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
  172. PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
  173. PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
  174. PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
  175. PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
  176. PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
  177. };
  178. enum pm_pinctrl_config_param {
  179. PM_PINCTRL_CONFIG_SLEW_RATE = 0,
  180. PM_PINCTRL_CONFIG_BIAS_STATUS = 1,
  181. PM_PINCTRL_CONFIG_PULL_CTRL = 2,
  182. PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,
  183. PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,
  184. PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,
  185. PM_PINCTRL_CONFIG_TRI_STATE = 6,
  186. PM_PINCTRL_CONFIG_MAX = 7,
  187. };
  188. enum pm_pinctrl_slew_rate {
  189. PM_PINCTRL_SLEW_RATE_FAST = 0,
  190. PM_PINCTRL_SLEW_RATE_SLOW = 1,
  191. };
  192. enum pm_pinctrl_bias_status {
  193. PM_PINCTRL_BIAS_DISABLE = 0,
  194. PM_PINCTRL_BIAS_ENABLE = 1,
  195. };
  196. enum pm_pinctrl_pull_ctrl {
  197. PM_PINCTRL_BIAS_PULL_DOWN = 0,
  198. PM_PINCTRL_BIAS_PULL_UP = 1,
  199. };
  200. enum pm_pinctrl_schmitt_cmos {
  201. PM_PINCTRL_INPUT_TYPE_CMOS = 0,
  202. PM_PINCTRL_INPUT_TYPE_SCHMITT = 1,
  203. };
  204. enum pm_pinctrl_drive_strength {
  205. PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
  206. PM_PINCTRL_DRIVE_STRENGTH_4MA = 1,
  207. PM_PINCTRL_DRIVE_STRENGTH_8MA = 2,
  208. PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
  209. };
  210. enum pm_pinctrl_tri_state {
  211. PM_PINCTRL_TRI_STATE_DISABLE = 0,
  212. PM_PINCTRL_TRI_STATE_ENABLE = 1,
  213. };
  214. enum zynqmp_pm_reset_action {
  215. PM_RESET_ACTION_RELEASE = 0,
  216. PM_RESET_ACTION_ASSERT = 1,
  217. PM_RESET_ACTION_PULSE = 2,
  218. };
  219. enum zynqmp_pm_reset {
  220. ZYNQMP_PM_RESET_START = 1000,
  221. ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
  222. ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
  223. ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
  224. ZYNQMP_PM_RESET_DP = 1003,
  225. ZYNQMP_PM_RESET_SWDT_CRF = 1004,
  226. ZYNQMP_PM_RESET_AFI_FM5 = 1005,
  227. ZYNQMP_PM_RESET_AFI_FM4 = 1006,
  228. ZYNQMP_PM_RESET_AFI_FM3 = 1007,
  229. ZYNQMP_PM_RESET_AFI_FM2 = 1008,
  230. ZYNQMP_PM_RESET_AFI_FM1 = 1009,
  231. ZYNQMP_PM_RESET_AFI_FM0 = 1010,
  232. ZYNQMP_PM_RESET_GDMA = 1011,
  233. ZYNQMP_PM_RESET_GPU_PP1 = 1012,
  234. ZYNQMP_PM_RESET_GPU_PP0 = 1013,
  235. ZYNQMP_PM_RESET_GPU = 1014,
  236. ZYNQMP_PM_RESET_GT = 1015,
  237. ZYNQMP_PM_RESET_SATA = 1016,
  238. ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
  239. ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
  240. ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
  241. ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
  242. ZYNQMP_PM_RESET_APU_L2 = 1021,
  243. ZYNQMP_PM_RESET_ACPU3 = 1022,
  244. ZYNQMP_PM_RESET_ACPU2 = 1023,
  245. ZYNQMP_PM_RESET_ACPU1 = 1024,
  246. ZYNQMP_PM_RESET_ACPU0 = 1025,
  247. ZYNQMP_PM_RESET_DDR = 1026,
  248. ZYNQMP_PM_RESET_APM_FPD = 1027,
  249. ZYNQMP_PM_RESET_SOFT = 1028,
  250. ZYNQMP_PM_RESET_GEM0 = 1029,
  251. ZYNQMP_PM_RESET_GEM1 = 1030,
  252. ZYNQMP_PM_RESET_GEM2 = 1031,
  253. ZYNQMP_PM_RESET_GEM3 = 1032,
  254. ZYNQMP_PM_RESET_QSPI = 1033,
  255. ZYNQMP_PM_RESET_UART0 = 1034,
  256. ZYNQMP_PM_RESET_UART1 = 1035,
  257. ZYNQMP_PM_RESET_SPI0 = 1036,
  258. ZYNQMP_PM_RESET_SPI1 = 1037,
  259. ZYNQMP_PM_RESET_SDIO0 = 1038,
  260. ZYNQMP_PM_RESET_SDIO1 = 1039,
  261. ZYNQMP_PM_RESET_CAN0 = 1040,
  262. ZYNQMP_PM_RESET_CAN1 = 1041,
  263. ZYNQMP_PM_RESET_I2C0 = 1042,
  264. ZYNQMP_PM_RESET_I2C1 = 1043,
  265. ZYNQMP_PM_RESET_TTC0 = 1044,
  266. ZYNQMP_PM_RESET_TTC1 = 1045,
  267. ZYNQMP_PM_RESET_TTC2 = 1046,
  268. ZYNQMP_PM_RESET_TTC3 = 1047,
  269. ZYNQMP_PM_RESET_SWDT_CRL = 1048,
  270. ZYNQMP_PM_RESET_NAND = 1049,
  271. ZYNQMP_PM_RESET_ADMA = 1050,
  272. ZYNQMP_PM_RESET_GPIO = 1051,
  273. ZYNQMP_PM_RESET_IOU_CC = 1052,
  274. ZYNQMP_PM_RESET_TIMESTAMP = 1053,
  275. ZYNQMP_PM_RESET_RPU_R50 = 1054,
  276. ZYNQMP_PM_RESET_RPU_R51 = 1055,
  277. ZYNQMP_PM_RESET_RPU_AMBA = 1056,
  278. ZYNQMP_PM_RESET_OCM = 1057,
  279. ZYNQMP_PM_RESET_RPU_PGE = 1058,
  280. ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
  281. ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
  282. ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
  283. ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
  284. ZYNQMP_PM_RESET_USB0_APB = 1063,
  285. ZYNQMP_PM_RESET_USB1_APB = 1064,
  286. ZYNQMP_PM_RESET_IPI = 1065,
  287. ZYNQMP_PM_RESET_APM_LPD = 1066,
  288. ZYNQMP_PM_RESET_RTC = 1067,
  289. ZYNQMP_PM_RESET_SYSMON = 1068,
  290. ZYNQMP_PM_RESET_AFI_FM6 = 1069,
  291. ZYNQMP_PM_RESET_LPD_SWDT = 1070,
  292. ZYNQMP_PM_RESET_FPD = 1071,
  293. ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
  294. ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
  295. ZYNQMP_PM_RESET_DBG_LPD = 1074,
  296. ZYNQMP_PM_RESET_DBG_FPD = 1075,
  297. ZYNQMP_PM_RESET_APLL = 1076,
  298. ZYNQMP_PM_RESET_DPLL = 1077,
  299. ZYNQMP_PM_RESET_VPLL = 1078,
  300. ZYNQMP_PM_RESET_IOPLL = 1079,
  301. ZYNQMP_PM_RESET_RPLL = 1080,
  302. ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
  303. ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
  304. ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
  305. ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
  306. ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
  307. ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
  308. ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
  309. ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
  310. ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
  311. ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
  312. ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
  313. ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
  314. ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
  315. ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
  316. ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
  317. ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
  318. ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
  319. ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
  320. ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
  321. ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
  322. ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
  323. ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
  324. ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
  325. ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
  326. ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
  327. ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
  328. ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
  329. ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
  330. ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
  331. ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
  332. ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
  333. ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
  334. ZYNQMP_PM_RESET_RPU_LS = 1113,
  335. ZYNQMP_PM_RESET_PS_ONLY = 1114,
  336. ZYNQMP_PM_RESET_PL = 1115,
  337. ZYNQMP_PM_RESET_PS_PL0 = 1116,
  338. ZYNQMP_PM_RESET_PS_PL1 = 1117,
  339. ZYNQMP_PM_RESET_PS_PL2 = 1118,
  340. ZYNQMP_PM_RESET_PS_PL3 = 1119,
  341. ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
  342. };
  343. enum pm_ioctl_id {
  344. IOCTL_GET_RPU_OPER_MODE = 0,
  345. IOCTL_SET_RPU_OPER_MODE = 1,
  346. IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
  347. IOCTL_TCM_COMB_CONFIG = 3,
  348. IOCTL_SET_TAPDELAY_BYPASS = 4,
  349. IOCTL_SET_SGMII_MODE = 5,
  350. IOCTL_SD_DLL_RESET = 6,
  351. IOCTL_SET_SD_TAPDELAY = 7,
  352. IOCTL_SET_PLL_FRAC_MODE = 8,
  353. IOCTL_GET_PLL_FRAC_MODE = 9,
  354. IOCTL_SET_PLL_FRAC_DATA = 10,
  355. IOCTL_GET_PLL_FRAC_DATA = 11,
  356. IOCTL_WRITE_GGS = 12,
  357. IOCTL_READ_GGS = 13,
  358. IOCTL_WRITE_PGGS = 14,
  359. IOCTL_READ_PGGS = 15,
  360. /* IOCTL for ULPI reset */
  361. IOCTL_ULPI_RESET = 16,
  362. /* Set healthy bit value*/
  363. IOCTL_SET_BOOT_HEALTH_STATUS = 17,
  364. IOCTL_AFI = 18,
  365. /* Probe counter read/write */
  366. IOCTL_PROBE_COUNTER_READ = 19,
  367. IOCTL_PROBE_COUNTER_WRITE = 20,
  368. IOCTL_OSPI_MUX_SELECT = 21,
  369. /* IOCTL for USB power request */
  370. IOCTL_USB_SET_STATE = 22,
  371. /* IOCTL to get last reset reason */
  372. IOCTL_GET_LAST_RESET_REASON = 23,
  373. /* AIE ISR Clear */
  374. IOCTL_AIE_ISR_CLEAR = 24,
  375. /* Register SGI to ATF */
  376. IOCTL_REGISTER_SGI = 25,
  377. /* Runtime feature configuration */
  378. IOCTL_SET_FEATURE_CONFIG = 26,
  379. IOCTL_GET_FEATURE_CONFIG = 27,
  380. /* IOCTL for Secure Read/Write Interface */
  381. IOCTL_READ_REG = 28,
  382. IOCTL_MASK_WRITE_REG = 29,
  383. /* Dynamic SD/GEM/USB configuration */
  384. IOCTL_SET_SD_CONFIG = 30,
  385. IOCTL_SET_GEM_CONFIG = 31,
  386. IOCTL_SET_USB_CONFIG = 32,
  387. /* AIE/AIEML Operations */
  388. IOCTL_AIE_OPS = 33,
  389. /* IOCTL to get default/current QoS */
  390. IOCTL_GET_QOS = 34,
  391. };
  392. enum pm_sd_config_type {
  393. SD_CONFIG_EMMC_SEL = 1, /* To set SD_EMMC_SEL in CTRL_REG_SD */
  394. SD_CONFIG_BASECLK = 2, /* To set SD_BASECLK in SD_CONFIG_REG1 */
  395. SD_CONFIG_8BIT = 3, /* To set SD_8BIT in SD_CONFIG_REG2 */
  396. SD_CONFIG_FIXED = 4, /* To set fixed config registers */
  397. };
  398. enum pm_gem_config_type {
  399. GEM_CONFIG_SGMII_MODE = 1, /* To set GEM_SGMII_MODE in GEM_CLK_CTRL */
  400. GEM_CONFIG_FIXED = 2, /* To set fixed config registers */
  401. };
  402. #define PM_SIP_SVC 0xc2000000
  403. #define ZYNQMP_PM_VERSION_MAJOR 1
  404. #define ZYNQMP_PM_VERSION_MINOR 0
  405. #define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
  406. #define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
  407. #define ZYNQMP_PM_VERSION \
  408. ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
  409. ZYNQMP_PM_VERSION_MINOR)
  410. #define ZYNQMP_PM_VERSION_INVALID ~0
  411. #define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
  412. #define PMIO_NODE_ID_BASE 0x1410801B
  413. /*
  414. * Return payload size
  415. * Not every firmware call expects the same amount of return bytes, however the
  416. * firmware driver always copies 5 bytes from RX buffer to the ret_payload
  417. * buffer. Therefore allocating with this defined value is recommended to avoid
  418. * overflows.
  419. */
  420. #define PAYLOAD_ARG_CNT 5U
  421. unsigned int zynqmp_firmware_version(void);
  422. int zynqmp_pmufw_node(u32 id);
  423. int zynqmp_pmufw_config_close(void);
  424. int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
  425. int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
  426. u32 arg3, u32 *ret_payload);
  427. int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
  428. int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
  429. u32 value);
  430. int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
  431. int zynqmp_mmio_read(const u32 address, u32 *value);
  432. int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
  433. /* Type of Config Object */
  434. #define PM_CONFIG_OBJECT_TYPE_BASE 0x1U
  435. #define PM_CONFIG_OBJECT_TYPE_OVERLAY 0x2U
  436. /* Section Id */
  437. #define PM_CONFIG_SLAVE_SECTION_ID 0x102U
  438. #define PM_CONFIG_SET_CONFIG_SECTION_ID 0x107U
  439. /* Flag Option */
  440. #define PM_SLAVE_FLAG_IS_SHAREABLE 0x1U
  441. #define PM_MASTER_USING_SLAVE_MASK 0x2U
  442. /* IPI Mask for Master */
  443. #define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK 0x00000001
  444. #define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK 0x00000100
  445. #define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK 0x00000200
  446. enum zynqmp_pm_request_ack {
  447. ZYNQMP_PM_REQUEST_ACK_NO = 1,
  448. ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
  449. ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
  450. };
  451. /* Node capabilities */
  452. #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
  453. #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
  454. #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
  455. #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
  456. #define ZYNQMP_PM_MAX_QOS 100U
  457. /* Firmware feature check version mask */
  458. #define FIRMWARE_VERSION_MASK GENMASK(15, 0)
  459. /* PM API versions */
  460. #define PM_API_VERSION_2 2
  461. struct zynqmp_ipi_msg {
  462. size_t len;
  463. u32 *buf;
  464. };
  465. #endif /* _ZYNQMP_FIRMWARE_H_ */