tsec.h 10 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * tsec.h
  4. *
  5. * Driver for the Motorola Triple Speed Ethernet Controller
  6. *
  7. * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
  8. * (C) Copyright 2003, Motorola, Inc.
  9. * maintained by Xianghua Xiao (x.xiao@motorola.com)
  10. * author Andy Fleming
  11. */
  12. #ifndef __TSEC_H
  13. #define __TSEC_H
  14. #include <net.h>
  15. #include <config.h>
  16. #include <phy.h>
  17. #define TSEC_MDIO_REGS_OFFSET 0x520
  18. #define MAC_ADDR_LEN 6
  19. /* #define TSEC_TIMEOUT 1000000 */
  20. #define TSEC_TIMEOUT 1000
  21. #define TOUT_LOOP 1000000
  22. /* TBI register addresses */
  23. #define TBI_CR 0x00
  24. #define TBI_SR 0x01
  25. #define TBI_ANA 0x04
  26. #define TBI_ANLPBPA 0x05
  27. #define TBI_ANEX 0x06
  28. #define TBI_TBICON 0x11
  29. /* TBI MDIO register bit fields*/
  30. #define TBICON_CLK_SELECT 0x0020
  31. #define TBIANA_ASYMMETRIC_PAUSE 0x0100
  32. #define TBIANA_SYMMETRIC_PAUSE 0x0080
  33. #define TBIANA_HALF_DUPLEX 0x0040
  34. #define TBIANA_FULL_DUPLEX 0x0020
  35. #define TBICR_PHY_RESET 0x8000
  36. #define TBICR_ANEG_ENABLE 0x1000
  37. #define TBICR_RESTART_ANEG 0x0200
  38. #define TBICR_FULL_DUPLEX 0x0100
  39. #define TBICR_SPEED1_SET 0x0040
  40. /* MAC register bits */
  41. #define MACCFG1_SOFT_RESET 0x80000000
  42. #define MACCFG1_RESET_RX_MC 0x00080000
  43. #define MACCFG1_RESET_TX_MC 0x00040000
  44. #define MACCFG1_RESET_RX_FUN 0x00020000
  45. #define MACCFG1_RESET_TX_FUN 0x00010000
  46. #define MACCFG1_LOOPBACK 0x00000100
  47. #define MACCFG1_RX_FLOW 0x00000020
  48. #define MACCFG1_TX_FLOW 0x00000010
  49. #define MACCFG1_SYNCD_RX_EN 0x00000008
  50. #define MACCFG1_RX_EN 0x00000004
  51. #define MACCFG1_SYNCD_TX_EN 0x00000002
  52. #define MACCFG1_TX_EN 0x00000001
  53. #define MACCFG2_INIT_SETTINGS 0x00007205
  54. #define MACCFG2_FULL_DUPLEX 0x00000001
  55. #define MACCFG2_IF 0x00000300
  56. #define MACCFG2_GMII 0x00000200
  57. #define MACCFG2_MII 0x00000100
  58. #define ECNTRL_INIT_SETTINGS 0x00001000
  59. #define ECNTRL_TBI_MODE 0x00000020
  60. #define ECNTRL_REDUCED_MODE 0x00000010
  61. #define ECNTRL_R100 0x00000008
  62. #define ECNTRL_REDUCED_MII_MODE 0x00000004
  63. #define ECNTRL_SGMII_MODE 0x00000002
  64. #define RCTRL_PROM 0x00000008
  65. #ifndef CFG_SYS_TBIPA_VALUE
  66. # define CFG_SYS_TBIPA_VALUE 0x1f
  67. #endif
  68. #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
  69. #define MINFLR_INIT_SETTINGS 0x00000040
  70. #define DMACTRL_INIT_SETTINGS 0x000000c3
  71. #define DMACTRL_GRS 0x00000010
  72. #define DMACTRL_GTS 0x00000008
  73. #define DMACTRL_LE 0x00008000
  74. #define TSTAT_CLEAR_THALT 0x80000000
  75. #define RSTAT_CLEAR_RHALT 0x00800000
  76. #define IEVENT_INIT_CLEAR 0xffffffff
  77. #define IEVENT_BABR 0x80000000
  78. #define IEVENT_RXC 0x40000000
  79. #define IEVENT_BSY 0x20000000
  80. #define IEVENT_EBERR 0x10000000
  81. #define IEVENT_MSRO 0x04000000
  82. #define IEVENT_GTSC 0x02000000
  83. #define IEVENT_BABT 0x01000000
  84. #define IEVENT_TXC 0x00800000
  85. #define IEVENT_TXE 0x00400000
  86. #define IEVENT_TXB 0x00200000
  87. #define IEVENT_TXF 0x00100000
  88. #define IEVENT_IE 0x00080000
  89. #define IEVENT_LC 0x00040000
  90. #define IEVENT_CRL 0x00020000
  91. #define IEVENT_XFUN 0x00010000
  92. #define IEVENT_RXB0 0x00008000
  93. #define IEVENT_GRSC 0x00000100
  94. #define IEVENT_RXF0 0x00000080
  95. #define IMASK_INIT_CLEAR 0x00000000
  96. #define IMASK_TXEEN 0x00400000
  97. #define IMASK_TXBEN 0x00200000
  98. #define IMASK_TXFEN 0x00100000
  99. #define IMASK_RXFEN0 0x00000080
  100. /* Default Attribute fields */
  101. #define ATTR_INIT_SETTINGS 0x000000c0
  102. #define ATTRELI_INIT_SETTINGS 0x00000000
  103. /* TxBD status field bits */
  104. #define TXBD_READY 0x8000
  105. #define TXBD_PADCRC 0x4000
  106. #define TXBD_WRAP 0x2000
  107. #define TXBD_INTERRUPT 0x1000
  108. #define TXBD_LAST 0x0800
  109. #define TXBD_CRC 0x0400
  110. #define TXBD_DEF 0x0200
  111. #define TXBD_HUGEFRAME 0x0080
  112. #define TXBD_LATECOLLISION 0x0080
  113. #define TXBD_RETRYLIMIT 0x0040
  114. #define TXBD_RETRYCOUNTMASK 0x003c
  115. #define TXBD_UNDERRUN 0x0002
  116. #define TXBD_STATS 0x03ff
  117. /* RxBD status field bits */
  118. #define RXBD_EMPTY 0x8000
  119. #define RXBD_RO1 0x4000
  120. #define RXBD_WRAP 0x2000
  121. #define RXBD_INTERRUPT 0x1000
  122. #define RXBD_LAST 0x0800
  123. #define RXBD_FIRST 0x0400
  124. #define RXBD_MISS 0x0100
  125. #define RXBD_BROADCAST 0x0080
  126. #define RXBD_MULTICAST 0x0040
  127. #define RXBD_LARGE 0x0020
  128. #define RXBD_NONOCTET 0x0010
  129. #define RXBD_SHORT 0x0008
  130. #define RXBD_CRCERR 0x0004
  131. #define RXBD_OVERRUN 0x0002
  132. #define RXBD_TRUNCATED 0x0001
  133. #define RXBD_STATS 0x003f
  134. struct txbd8 {
  135. uint16_t status; /* Status Fields */
  136. uint16_t length; /* Buffer length */
  137. uint32_t bufptr; /* Buffer Pointer */
  138. };
  139. struct rxbd8 {
  140. uint16_t status; /* Status Fields */
  141. uint16_t length; /* Buffer Length */
  142. uint32_t bufptr; /* Buffer Pointer */
  143. };
  144. struct tsec_rmon_mib {
  145. /* Transmit and Receive Counters */
  146. u32 tr64; /* Tx/Rx 64-byte Frame Counter */
  147. u32 tr127; /* Tx/Rx 65-127 byte Frame Counter */
  148. u32 tr255; /* Tx/Rx 128-255 byte Frame Counter */
  149. u32 tr511; /* Tx/Rx 256-511 byte Frame Counter */
  150. u32 tr1k; /* Tx/Rx 512-1023 byte Frame Counter */
  151. u32 trmax; /* Tx/Rx 1024-1518 byte Frame Counter */
  152. u32 trmgv; /* Tx/Rx 1519-1522 byte Good VLAN Frame */
  153. /* Receive Counters */
  154. u32 rbyt; /* Receive Byte Counter */
  155. u32 rpkt; /* Receive Packet Counter */
  156. u32 rfcs; /* Receive FCS Error Counter */
  157. u32 rmca; /* Receive Multicast Packet (Counter) */
  158. u32 rbca; /* Receive Broadcast Packet */
  159. u32 rxcf; /* Receive Control Frame Packet */
  160. u32 rxpf; /* Receive Pause Frame Packet */
  161. u32 rxuo; /* Receive Unknown OP Code */
  162. u32 raln; /* Receive Alignment Error */
  163. u32 rflr; /* Receive Frame Length Error */
  164. u32 rcde; /* Receive Code Error */
  165. u32 rcse; /* Receive Carrier Sense Error */
  166. u32 rund; /* Receive Undersize Packet */
  167. u32 rovr; /* Receive Oversize Packet */
  168. u32 rfrg; /* Receive Fragments */
  169. u32 rjbr; /* Receive Jabber */
  170. u32 rdrp; /* Receive Drop */
  171. /* Transmit Counters */
  172. u32 tbyt; /* Transmit Byte Counter */
  173. u32 tpkt; /* Transmit Packet */
  174. u32 tmca; /* Transmit Multicast Packet */
  175. u32 tbca; /* Transmit Broadcast Packet */
  176. u32 txpf; /* Transmit Pause Control Frame */
  177. u32 tdfr; /* Transmit Deferral Packet */
  178. u32 tedf; /* Transmit Excessive Deferral Packet */
  179. u32 tscl; /* Transmit Single Collision Packet */
  180. /* (0x2_n700) */
  181. u32 tmcl; /* Transmit Multiple Collision Packet */
  182. u32 tlcl; /* Transmit Late Collision Packet */
  183. u32 txcl; /* Transmit Excessive Collision Packet */
  184. u32 tncl; /* Transmit Total Collision */
  185. u32 res2;
  186. u32 tdrp; /* Transmit Drop Frame */
  187. u32 tjbr; /* Transmit Jabber Frame */
  188. u32 tfcs; /* Transmit FCS Error */
  189. u32 txcf; /* Transmit Control Frame */
  190. u32 tovr; /* Transmit Oversize Frame */
  191. u32 tund; /* Transmit Undersize Frame */
  192. u32 tfrg; /* Transmit Fragments Frame */
  193. /* General Registers */
  194. u32 car1; /* Carry Register One */
  195. u32 car2; /* Carry Register Two */
  196. u32 cam1; /* Carry Register One Mask */
  197. u32 cam2; /* Carry Register Two Mask */
  198. };
  199. struct tsec_hash_regs {
  200. u32 iaddr0; /* Individual Address Register 0 */
  201. u32 iaddr1; /* Individual Address Register 1 */
  202. u32 iaddr2; /* Individual Address Register 2 */
  203. u32 iaddr3; /* Individual Address Register 3 */
  204. u32 iaddr4; /* Individual Address Register 4 */
  205. u32 iaddr5; /* Individual Address Register 5 */
  206. u32 iaddr6; /* Individual Address Register 6 */
  207. u32 iaddr7; /* Individual Address Register 7 */
  208. u32 res1[24];
  209. u32 gaddr0; /* Group Address Register 0 */
  210. u32 gaddr1; /* Group Address Register 1 */
  211. u32 gaddr2; /* Group Address Register 2 */
  212. u32 gaddr3; /* Group Address Register 3 */
  213. u32 gaddr4; /* Group Address Register 4 */
  214. u32 gaddr5; /* Group Address Register 5 */
  215. u32 gaddr6; /* Group Address Register 6 */
  216. u32 gaddr7; /* Group Address Register 7 */
  217. u32 res2[24];
  218. };
  219. struct tsec {
  220. /* General Control and Status Registers (0x2_n000) */
  221. u32 res000[4];
  222. u32 ievent; /* Interrupt Event */
  223. u32 imask; /* Interrupt Mask */
  224. u32 edis; /* Error Disabled */
  225. u32 res01c;
  226. u32 ecntrl; /* Ethernet Control */
  227. u32 minflr; /* Minimum Frame Length */
  228. u32 ptv; /* Pause Time Value */
  229. u32 dmactrl; /* DMA Control */
  230. u32 tbipa; /* TBI PHY Address */
  231. u32 res034[3];
  232. u32 res040[48];
  233. /* Transmit Control and Status Registers (0x2_n100) */
  234. u32 tctrl; /* Transmit Control */
  235. u32 tstat; /* Transmit Status */
  236. u32 res108;
  237. u32 tbdlen; /* Tx BD Data Length */
  238. u32 res110[5];
  239. u32 ctbptr; /* Current TxBD Pointer */
  240. u32 res128[23];
  241. u32 tbptr; /* TxBD Pointer */
  242. u32 res188[30];
  243. /* (0x2_n200) */
  244. u32 res200;
  245. u32 tbase; /* TxBD Base Address */
  246. u32 res208[42];
  247. u32 ostbd; /* Out of Sequence TxBD */
  248. u32 ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
  249. u32 res2b8[18];
  250. /* Receive Control and Status Registers (0x2_n300) */
  251. u32 rctrl; /* Receive Control */
  252. u32 rstat; /* Receive Status */
  253. u32 res308;
  254. u32 rbdlen; /* RxBD Data Length */
  255. u32 res310[4];
  256. u32 res320;
  257. u32 crbptr; /* Current Receive Buffer Pointer */
  258. u32 res328[6];
  259. u32 mrblr; /* Maximum Receive Buffer Length */
  260. u32 res344[16];
  261. u32 rbptr; /* RxBD Pointer */
  262. u32 res388[30];
  263. /* (0x2_n400) */
  264. u32 res400;
  265. u32 rbase; /* RxBD Base Address */
  266. u32 res408[62];
  267. /* MAC Registers (0x2_n500) */
  268. u32 maccfg1; /* MAC Configuration #1 */
  269. u32 maccfg2; /* MAC Configuration #2 */
  270. u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
  271. u32 hafdup; /* Half-duplex */
  272. u32 maxfrm; /* Maximum Frame */
  273. u32 res514;
  274. u32 res518;
  275. u32 res51c;
  276. u32 resmdio[6];
  277. u32 res538;
  278. u32 ifstat; /* Interface Status */
  279. u32 macstnaddr1; /* Station Address, part 1 */
  280. u32 macstnaddr2; /* Station Address, part 2 */
  281. u32 res548[46];
  282. /* (0x2_n600) */
  283. u32 res600[32];
  284. /* RMON MIB Registers (0x2_n680-0x2_n73c) */
  285. struct tsec_rmon_mib rmon;
  286. u32 res740[48];
  287. /* Hash Function Registers (0x2_n800) */
  288. struct tsec_hash_regs hash;
  289. u32 res900[128];
  290. /* Pattern Registers (0x2_nb00) */
  291. u32 resb00[62];
  292. u32 attr; /* Default Attribute Register */
  293. u32 attreli; /* Default Attribute Extract Length and Index */
  294. /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
  295. u32 resc00[256];
  296. };
  297. #define TSEC_GIGABIT (1 << 0)
  298. /* These flags currently only have meaning if we're using the eTSEC */
  299. #define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */
  300. #define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */
  301. #define TX_BUF_CNT 2
  302. struct tsec_data {
  303. u32 mdio_regs_off;
  304. };
  305. struct tsec_private {
  306. struct txbd8 __iomem txbd[TX_BUF_CNT];
  307. struct rxbd8 __iomem rxbd[PKTBUFSRX];
  308. struct tsec __iomem *regs;
  309. struct tsec_mii_mng __iomem *phyregs_sgmii;
  310. struct phy_device *phydev;
  311. phy_interface_t interface;
  312. struct mii_dev *bus;
  313. uint phyaddr;
  314. uint tbiaddr;
  315. char mii_devname[16];
  316. u32 flags;
  317. uint rx_idx; /* index of the current RX buffer */
  318. uint tx_idx; /* index of the current TX buffer */
  319. struct udevice *dev;
  320. };
  321. struct tsec_info_struct {
  322. struct tsec __iomem *regs;
  323. struct tsec_mii_mng __iomem *miiregs_sgmii;
  324. char *devname;
  325. char *mii_devname;
  326. phy_interface_t interface;
  327. unsigned int phyaddr;
  328. u32 flags;
  329. };
  330. #endif /* __TSEC_H */