mpc85xx.h 1.7 KB

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  1. /*
  2. * Copyright 2004, 2007 Freescale Semiconductor.
  3. * Copyright(c) 2003 Motorola Inc.
  4. */
  5. #ifndef __MPC85xx_H__
  6. #define __MPC85xx_H__
  7. #if defined(CONFIG_E500)
  8. #include <e500.h>
  9. #endif
  10. /*
  11. * SCCR - System Clock Control Register, 9-8
  12. */
  13. #define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
  14. #define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */
  15. #define SCCR_DFBRG_SHIFT 0
  16. #define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */
  17. #define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */
  18. #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
  19. #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
  20. /*
  21. * Define default values for some CCSR macros to make header files cleaner*
  22. *
  23. * To completely disable CCSR relocation in a board header file, define
  24. * CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE. This will force CFG_SYS_CCSRBAR_PHYS
  25. * to a value that is the same as CFG_SYS_CCSRBAR.
  26. */
  27. #ifdef CFG_SYS_CCSRBAR_PHYS
  28. #error "Do not define CFG_SYS_CCSRBAR_PHYS directly. Use \
  29. CFG_SYS_CCSRBAR_PHYS_LOW and/or CFG_SYS_CCSRBAR_PHYS_HIGH instead."
  30. #endif
  31. #if CONFIG_IS_ENABLED(SYS_CCSR_DO_NOT_RELOCATE)
  32. #undef CFG_SYS_CCSRBAR_PHYS_HIGH
  33. #undef CFG_SYS_CCSRBAR_PHYS_LOW
  34. #define CFG_SYS_CCSRBAR_PHYS_HIGH 0
  35. #endif
  36. #ifndef CFG_SYS_CCSRBAR
  37. #define CFG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
  38. #endif
  39. #ifndef CFG_SYS_CCSRBAR_PHYS_HIGH
  40. #ifdef CONFIG_PHYS_64BIT
  41. #define CFG_SYS_CCSRBAR_PHYS_HIGH 0xf
  42. #else
  43. #define CFG_SYS_CCSRBAR_PHYS_HIGH 0
  44. #endif
  45. #endif
  46. #ifndef CFG_SYS_CCSRBAR_PHYS_LOW
  47. #define CFG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
  48. #endif
  49. #define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
  50. CFG_SYS_CCSRBAR_PHYS_LOW)
  51. #endif /* __MPC85xx_H__ */